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MODULE – III
BASIC COMPUTER ORGANIZATION
 INSTRUCTION CODES/INSTRUCTION FORMATS

The organization of the computer is defined by its internal registers, the timing and
control structure, and the set of instructions that it uses.
 Program: set of instructions that specify the operations, operands, and the
sequence by which processing has to occur.
 Instruction: a binary code that specifies a sequence of micro-operations for
the computer.
 Instruction Code: group of bits that instruct the computer to perform specific
operation.

Instruction code is usually divided into two parts: Opcode and address(operand)
 Operation Code (opcode): A group of bits that define the operation. E.g.,
add, subtract, multiply, shift, complement. No. of bits required for opcode
depends on no. of operations available in computer. n bit opcode >= 2 n (or
less) operations
 Address (operand): specifies the location of operands (registers or
memory words). Memory words are specified by their address. Registers
are specified by their k-bit binary code. k-bit address >= 2k registers.

 COMPUTER REGISTERS

Registers are a type of computer memory used to quickly accept, store, and transfer
data and instructions that are being used immediately by the CPU. The registers used
by the CPU are often termed as Processor registers.

A processor register may hold an instruction, a storage address, or any data (such as
bit sequence or individual characters). The computer needs processor registers for
manipulating data and a register for holding a memory address. The register holding
the memory location is used to calculate the address of the next instruction after the
execution of the current instruction is completed.

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Register Symbol Purpose

Accumulator A Holds the results of all operations.
Instruction Register IR Holds the program currently in execution
Program Counter PC Holds the address of next instruction
Temporary Register TR Holds temporary data
Input Register INPR Holds input character
Output Register OUTR Holds output character
Data Register DR Hold memory operands
Address Register AR Holds address

 The data register (DR) holds the operand read from memory.
 The accumulator (AC) register is a general-purpose processing register.
 The instruction read from memory is placed in the instruction register (IR).
 The temporary register (TR) is used for holding temporary data during the processing.
 The memory address register (AR) has 12 bits since this is the width of a memory
address.
 The program counter (PC) also has 12 bits and it holds the address of the next
instruction to be read from memory after the current instruction is executed.
 Two registers are used for input and output-
o The input register (INPR) receives an 8-bit character from an input device.
o The output register (OUTR) holds an 8-bit character for an output device.

 INSTRUCTION CYCLE

A program residing in the memory unit of the computer consists of a sequence of

instructions. The program is executed in the computer by going through a cycle for
each instruction. Each instruction cycle in turn is subdivided into a sequence of sub
cycles or phases.
In the basic computer each instruction cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect
address.
4. Execute the instruction.
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Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and
execute the next instruction.

 COMPUTER INSTRUCTIONS
Computer instructions are a set of machine language instructions that a particular
processor understands and executes. A computer performs tasks on the basis of the
instruction provided. An instruction comprises of groups called fields. These fields
include:
 The operation code (Opcode) field which specifies the operation to be performed.
 The Address field which contains the location of the operand, i.e., register or memory
location.
 The Mode field which specifies how the operand will be located.

A basic computer has three instruction code formats which are:

 Memory - reference instruction
 Register - reference instruction
 Input-Output instruction

 Memory - reference instruction

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In Memory-reference instruction, 12 bits of memory is used to specify an address and

one bit to specify the addressing mode 'I'.

 Register - reference instruction

A Register-reference instruction specifies an operation on or a test of the AC

(Accumulator) register.
 Input-Output instruction

Just like the Register-reference instruction, an Input-Output instruction does not need
a reference to memory and is recognized by the operation code 111 with a 1 in the
leftmost bit of the instruction. The remaining 12 bits are used to specify the type of
the input-output operation or test performed.

 TIMING AND CONTROL

A control unit, or CU, is circuitry within a computer's processor that directs operations. It
instructs the memory, logic unit, and both output and input devices of the computer on how to
respond to the program's instructions. CPUs and GPUs are examples of devices that use
control units.
The Control Unit is classified into two major categories:

1. Hardwired Control
2. Microprogrammed Control

 Hardwired Control - The Hardwired Control organization involves the control logic
to be implemented with gates, flip-flops, decoders, and other digital circuits.

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o A Hard-wired Control consists of two decoders, a sequence counter, and a number of

logic gates.
o An instruction fetched from the memory unit is placed in the instruction register (IR).
o The component of an instruction register includes; I bit, the operation code, and bits 0
through 11.
o The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
o The outputs of the decoder are designated by the symbols D0 through D7.
o The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.
o The operation codes from Bits 0 through 11 are applied to the control logic gates.
o The Sequence counter (SC) can count in binary from 0 through 15.

 Micro-programmed Control- The Microprogrammed Control organization is

implemented by using the programming approach. In Microprogrammed Control, the
micro-operations are performed by executing a program consisting of micro-
instructions.

 Control Memory - The function of the control unit in a digital computer is to initiate
sequences of microoperations. The number of different types of microoperations that

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are available in a given system is finite. A control unit whose binary control variables
are stored in memory is called a microprogrammed control unit. Each word in control
memory contains within it a microinstruction. The microinstruction specifies one or
more microoperations for the system. A sequence of microinstructions constitutes a
microprogram. A computer that employs a microprogrammed control unit will have
two separate memories: a main memory and a control memory. The main memory is
available to the user for storing the programs. The contents of main memory may alter
when the data are manipulated and every time that the program is changed. The user's
program in main memory consists of machine instructions and data. While the control
memory holds a fixed microprogram that cannot be altered by the occasional user.

o The Control memory address register specifies the address of the micro-instruction.
o The Control memory is assumed to be a ROM, within which all control information is
permanently stored.
o The control register holds the microinstruction fetched from the memory.
o The micro-instruction contains a control word that specifies one or more micro-
operations for the data processor.
o While the micro-operations are being executed, the next address is computed in the
next address generator circuit and then transferred into the control address register to
read the next microinstruction.
o The next address generator is often referred to as a micro-program sequencer, as it
determines the address sequence that is read from control memory.
 INPUT-OUTPUT-INTERRUPT
In computer architecture, input-output devices act as an interface between the machine and
the user. Instructions and data stored in the memory must come from some input device. The
results are displayed to the user through some output device.

o The input-output terminals send and receive information.

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o The amount of information transferred will always have eight bits of an alphanumeric
code.
o The information generated through the keyboard is shifted into an input register
'INPR'.
o The information for the printer is stored in the output register 'OUTR'.
o Registers INPR and OUTR communicate with a communication interface serially and
with the AC in parallel.
o The transmitter interface receives information from the keyboard and transmits it to
INPR.
o The receiver interface receives information from OUTR and sends it to the printer
serially.

 DESIGN OF A BASIC COMPUTER

A basic computer consists of the following hardware components -

 A memory unit with 4096 words of 16 bits each
 Registers: AC (Accumulator), DR (Data register), AR (Address register), IR
(Instruction register), PC (Program counter), TR (Temporary register), SC (Sequence
Counter), INPR (Input register), and OUTR (Output register).
 Flip-Flops: I, S, E, R, IEN, FGI and FGO

 Two decoders: a 3 x 8 operation decoder and 4 x 16 timing decoder

 A 16-bit common bus
 Control Logic Gates
 The Logic and Adder circuits connected to the input of AC.

 DESIGN OF ACCUMULATOR LOGIC

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The adder and logic circuit has three sets of inputs. One set of 16 inputs comes from the
outputs of AC. Another set of 16 inputs come from the data register DR. A third set of eight
inputs comes from the input register INPR. The outputs of the adder and logic circuit
provide the data inputs for the register. In addition, it is necessary to include logic gates for
controlling the LD, INR, and CLR in the register and for controlling the operation of the
adder and logic circuit.

The transfer statements that will change the contents in Accumulator

 CENTRAL PROCESSING UNIT: INTRODUCTION

The CPU is made up of three major parts-

 The register set stores intermediate data used during the execution of the
instructions.
 The arithmetic-logic unit (ALU) performs the required microoperations for
executing the instructions.
 The control unit supervises the transfer of information among the registers and
instructs the ALU as to which operation to perform.

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 GENERAL REGISTER ORGANIZATION

The output of each register is connected to two multiplexers (MUX) to form the two buses
A and B. The selection lines in each multiplexer select one register or the input data for the
particular bus. The A and B buses form the inputs to a common arithmetic logic unit (ALU).
The operation selected in the ALU determines the arithmetic or logic micro-operation that is
to be performed. The result of the micro-operation is available for output data and also goes
into the inputs of all the registers. The register that receives the information from the output
bus is selected by a decoder. The decoder activates one of the register load inputs, thus
providing a transfer path between the data in the output bus and the inputs of the selected
destination register.
The control unit that operates the CPU bus system directs the information flow through the
registers and ALU by selecting the various components in the system.

For example, to perform the operation R 1 <--R2 + R3 the control must provide binary
selection variables to the following selector inputs:
 MUX A selector (SELA): to place the content of R2 into bus A.
 MUX B selector (SELB): to place the content o f R 3 into bus B
 ALU operation selector (OPR): to provide the arithmetic addition A + B.
 Decoder destination selector (SELD): to transfer the content of the output bus
into R1.

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The four control selection variables are generated in the control unit and must be available at
the beginning of a clock cycle. The data from the two source registers propagate through the
gates in the multiplexers and the ALU, to the output bus, and into the inputs of the destination
register, all during the clock cycle interval. Then, when the next clock transition occurs, the
binary information from the output bus is transferred into R 1. To achieve a fast response
time, the ALU is constructed with high-speed circuits.

 Control Word - There are 14 binary selection inputs in the unit, and their combined
value specifies a control word.

Encoding of Register Selection Field –

Encoding of ALU Operations –

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ALU Micro-Operations –

Micro-operation SELA SELB SELD OPR Control Word

R1 ← R2 – R3 R2 R3 R1 SUB 010 011 001 00101

R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010

R6 ← R6 + R1 - R6 R1 INCA 110 000 110 00001

R7 ← R1 R1 - R7 TSFA 001 000 111 00000

Output ← R2 R2 – None TSFA 010 000 000 00000

Output ← Input Input - None TSFA 000 000 000 00000

R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000

R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

 STACK ORGANIZATION
Stack is also known as the Last In First Out (LIFO) list. It is the most important feature in
the CPU. It saves data such that the element stored last is retrieved first. A stack is a memory
unit with an address register. This register influences the address for the stack, which is
known as Stack Pointer (SP). The stack pointer continually influences the address of the
element that is located at the top of the stack. It can insert an element into or delete an
element from the stack. The insertion operation is known as push operation and the deletion
operation is known as pop operation. In a computer stack, these operations are simulated by
incrementing or decrementing the SP register.
 Register Stack -
The stack can be arranged as a set of memory words or registers. Consider a 64-word register
stack arranged as displayed in the figure. The stack pointer register includes a binary number,
which is the address of the element present at the top of the stack. The three-element A, B,
and C are located in the stack.
The element C is at the top of the stack and the stack pointer holds the address of C that is 3.
The top element is popped from the stack through reading memory word at address 3 and
decrementing the stack pointer by 1. Then, B is at the top of the stack and the SP holds the
address of B that is 2. It can insert a new word; the stack is pushed by incrementing the stack
pointer by 1 and inserting a word in that incremented location.
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The stack pointer includes 6 bits, because 26 = 64, and the SP cannot exceed 63 (111111 in
binary). After all, if 63 is incremented by 1, therefore the result is 0(111111 + 1 = 1000000).
SP holds only the six least significant bits. If 000000 is decremented by 1 thus the result is
111111.

Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1. If the stack is null,
then the one-bit register ‘EMPTY’ is set to 1. The data register DR holds the binary
information which is composed into or readout of the stack.
First, the SP is set to 0, EMPTY is set to 1, and FULL is set to 0. Now, as the stack is not full
(FULL = 0), a new element is inserted using the push operation.
The push operation is executed as follows –

SP←SP + 1 It can increment stack pointer

M[SP] ← DR It can write element on top of the stack

If (SP = 0) then (FULL ← 1) Check if stack is full

EMPTY ← 0 Mark the stack not empty

The stack pointer is incremented by 1 and the address of the next higher word is saved in
the SP. The word from DR is inserted into the stack using the memory write operation. The
first element is saved at address 1 and the final element is saved at address 0. If the stack
pointer is at 0, then the stack is full and ‘FULL’ is set to 1. This is the condition when the SP
was in location 63 and after incrementing SP, the final element is saved at address 0. During
an element is saved at address 0, there are no more empty registers in the stack. The stack is
full and the ‘EMPTY’ is set to 0.

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A new element is deleted from the stack if the stack is not empty (if EMPTY = 0). The pop
operation includes the following sequence of micro-operations –

DR←M[SP] It can read an element from the top of the stack

SP ← SP – 1 It can decrement the stack pointer

If (SP = 0) then (EMPTY ← 1) Check if stack is empty

FULL ← 0 Mark the stack not full

The top element from the stack is read and transfer to DR and thus the stack pointer is
decremented. If the stack pointer reaches 0, then the stack is empty and ‘EMPTY’ is set to
1. This is the condition when the element in location 1 is read out and the SP is decremented
by 1.
 INSTRUCTION FORMATS

In computer organization, instruction formats refer to the way instructions are encoded and
represented in machine language. There are several types of instruction formats, including
zero, one, two, and three-address instructions.
Each type of instruction format has its own advantages and disadvantages in terms of code
size, execution time, and flexibility. Modern computer architectures typically use a
combination of these formats to provide a balance between simplicity and power.

Types of Instructions based on the number of addresses –

 Zero Address Instructions - These instructions do not specify any operands or

addresses. Instead, they operate on data stored in registers or memory locations
implicitly defined by the instruction. For example, a zero-address instruction might
simply add the contents of two registers together without specifying the register
names.
A stack-based computer does not use the address field in the instruction. To evaluate
an expression, it is first converted to reverse Polish Notation i.e. Postfix Notation.

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E.g., Expression: X = (A+B) * (C+D)

Postfix: X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

TOP =
MUL
(C+D)*(A+B)

POP X M[X] = TOP

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 One Address Instructions - These instructions specify two operands or

addresses, which may be memory locations or registers. The instruction operates on
the contents of both operands, and the result may be stored in the same or a different
location. For example, a two-address instruction might add the contents of two
registers together and store the result in one of the registers.
This is common in commercial computers. Here two addresses can be specified in the
instruction. Unlike earlier in one address instruction, the result was stored in the
accumulator, here the result can be stored at different locations rather than just
accumulators, but requires a greater number of bits to represent the address.

E.g., Expression: X = (A+B) * (C+D)

AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

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 Two Address Instructions - These instructions specify two operands or

addresses, which may be memory locations or registers. The instruction operates on
the contents of both operands, and the result may be stored in the same or a different
location. For example, a two-address instruction might add the contents of two
registers together and store the result in one of the registers.
This is common in commercial computers. Here two addresses can be specified in the
instruction. Unlike earlier in one address instruction, the result was stored in the
accumulator, here the result can be stored at different locations rather than just
accumulators, but require a greater number of bits to represent the address.

E.g., Expression: X = (A+B) * (C+D)

R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = M[C]

ADD R2, D R2 = R2 + M[D]

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

 Three Address Instructions - These instructions specify three operands or

addresses, which may be memory locations or registers. The instruction operates on
the contents of all three operands, and the result may be stored in the same or a
different location. For example, a three-address instruction might multiply the

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contents of two registers together and add the contents of a third register, storing the
result in a fourth register.
This has three address fields to specify a register or a memory location. Programs
created are much short in size but number of bits per instruction increases. These
instructions make the creation of the program much easier but it does not mean that
program will run much faster because now instructions only contain more information
but each micro-operation (changing the content of the register, loading address in the
address bus etc.) will be performed in one cycle only.

E.g., Expression: X = (A+B)*(C+D)

R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

X, R1,
MUL M[X] = R1 * R2
R2

 ADDRESSING MODES

The addressing modes help us specify the way in which an operand’s effective address is
represented in any given instruction. Some addressing modes allow referring to a large
range of areas efficiently, like some linear array of addresses along with a list of addresses.
The addressing modes describe an efficient and flexible way to define complex effective
addresses.
The programs are generally written in high-level languages, as it’s a convenient way in
which one can define the variables along with the operations that a programmer performs on
the variables. This program is later compiled so as to generate the actual machine code. A
machine code includes low-level instructions.
A set of low-level instructions has operands and opcodes. An addressing mode has no
relation with the opcode part. It basically focuses on presenting the address of the operand
in the instructions.

 Implied Mode
 Immediate Mode
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 Direct Address Mode

 Indirect Address Mode

 Register Mode
 Register Indirect Mode
 Indexed Addressing Mode
Immediate Mode
In the immediate mode, we specify the operand in the instruction itself. Or, in simpler words,
instead of an address field, the immediate-mode instruction consists of an operand field. An
operand field contains the actual operand that is to be used in conjunction with an operation
that is determined in the given instruction. The immediate-mode instructions help initialize
registers to a certain constant value.
Direct Address Mode
In the direct address mode, the address part of the instruction is equal to the effective address.
The operand would reside in memory, and the address here is given directly by the
instruction’s address field. The address field would specify the actual branch address in a
branch-type instruction.
Indirect Address Mode
In an indirect address mode, the address field of an available instruction gives that address in
which the effective address gets stored in memory. The control fetches the instruction
available in the memory and then uses its address part in order to (again) access memory to
read its effective address.
Register Mode
In the register mode, the operands exist in those registers that reside within a CPU. In this
case, we select a specific register from a certain register field in the given instruction. The k-
bit field is capable of determining one 2k register.
Register Indirect Mode
In the register indirect mode, the instruction available to us defines that particular register in
the CPU whose contents provides the operand’s address in the memory. In simpler words, any
selected register would include the address of an operand instead of the operand itself.
The reference to a register is equivalent to specifying any memory address. The pros of using
this type of instruction are that an instruction’s address field would make use of fewer bits to
select a register than would be require when someone wants to directly specify a memory
address.
Implied Mode

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In the implied mode, the operands are implicitly specified in the definition of instruction. For
instance, the “complement accumulator” instruction refers to an implied-mode instruction. It
is because, in the definition of the instruction, the operand is implied in the accumulator
register. All the register reference instructions are implied-mode instructions that use an
accumulator.
Indexed Addressing Mode
In the indexed addressing mode, the content of a given index register gets added to an
instruction’s address part so as to obtain the effective address. Here, the index register refers
to a special CPU register that consists of an index value. An instruction’s address field defines
the beginning address of any data array present in memory.

 DATA TRANSFER, MANIPULATION AND PROGRAM CONTROL

Most computer instructions can be classified into three categories:
 Data transfer - Data transfer instructions cause transfer of data from one location to
another
 Data manipulation - Data manipulation performs arithmetic, logic and shift
operations.
 Program control instructions - Program control instructions provide decision making
capabilities and change the path taken by the program when executed in computer.

Data Transfer Instruction

• Typical Data Transfer Instruction:
LD -
>> Load: transfer from memory to a processor register, usually an AC (memory read)
ST -
>> Store: transfer from a processor register into memory (memory write)
MOV -
>> Move: transfer from one register to another register
XCH -
>> Exchange: swap information between two registers or a register and a memory word
IN/OUT -
>> Input/Output: transfer data among processor registers and input/output device
PUSH/POP -
>> Push/Pop: transfer data between processor registers and a memory stack

Data Manipulation Instructions:

1) Arithmetic,
2) Logical and bit manipulation,
3) Shift Instruction

module -3-ca prof. anjali soman

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RR Institute of Management Studies

(Affiliated to Bangalore University, Recognized by Karnataka Government)
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Arithmetic Instructions:

Logical and Bit Manipulation Instructions:

Shift Instructions:

module -3-ca prof. anjali soman

 PKM Educational Trust

RR Institute of Management Studies

(Affiliated to Bangalore University, Recognized by Karnataka Government)
Raja Reddy Layout, Chikkabanavara, Bengaluru-560090
COURSES OFFERED:
BBA | BBA-Aviation | BCA | MSc & BSc -Forensic Science | BCom IQAC

Program Control Instructions:

 COMPLEX INSTRUCTION SET COMPUTER(CISC) Vs REDUCED

INSTRUCTION SET COMPUTER(RISC)
Complex Instruction Set Computer (CISC)
 A large number of instructions - typically from 100 to 250 instruction
 Some instructions that perform specialized tasks and are used infrequently.
 A large variety of addressing modes - typically from 5 to 20 different modes
 Variable-length instruction formats
 Instructions that manipulate operands in memory (RISC O in register) Reduced
Instruction Set Computer (RISC)
Reduced Instruction Set Computer (CISC)
 Relatively few instructions
 Relatively few addressing modes
 Memory access limited to load and store instruction

module -3-ca prof. anjali soman

 PKM Educational Trust

RR Institute of Management Studies

(Affiliated to Bangalore University, Recognized by Karnataka Government)
Raja Reddy Layout, Chikkabanavara, Bengaluru-560090
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 All operations done within the registers of the CPU

 Fixed-length, easily decoded instruction format
 Single-cycle instruction execution
 Hardwired rather than microprogrammed control

module -3-ca prof. anjali soman