Chapter

Types of Memory

Most embedded systems use memories in various ways. Memory is required inside
embedded systems for a variety of reasons: to store the executable code, to load the
instructions to be executed as well as the associated data, to save important information
that can be changed by the user during sessions. We will introduce these causes of
memory usage inside embedded systems in this section. Then we will deal with the
techniques used to satisfy these requirements inside embedded systems.

Let us begin this chapter by giving an introduction to the types of memory used by
embedded systems. As embedded system engineers, it is always advantageous to peek
into this domain so that we can appreciate the usage of different types of memory. We
can understand the type of memory, which should be used for a specific activity. Also,
this gives tus an understanding of the capabilities of these memories and the pros and
cons in of memory. We will discuss about ROM and its kinds,
using a specific type
RAM and its types, as well as the FLASH memory. We will necessarily keep this dis-
cussion short. The interested reader is advised to consult the exhaustive literature avail-
able for memory.

Basically embedded systems require memory to store the following classes of data:
Data related to executable code in machine instruction format: This is
usually burnt*
while the device is being manufactured. This kind of data is
typically not changed dur-
ing the lifetime of the device. This kind of data
requires a write-protected or read only
emory-that is, once filled, this memory will not be changed during the lifetime of
the product.

We will soon
see how it is "burnt".
 Embedded Realtime Systems Programming
52
This data is usually the variahle
Data storing the current context ofexecution: Volalile. Since the variables
This memory
1s very
and their stacks. that the cCon
used by programs
program
is executung,
it 1s expected
when a
and stacks make
sense only turned o . However, it is also expect
is
this be lost when power
can well as writing because the
tents of memory as
access for reading
fast to
this factor. This type of mem
is
ed that this kind of m e m o r y be governed by
device will also random access mem
realtime behaviour of a in technical jargon,
and volatile-or E m b e d d e d systems use
should be fast, erasable misnomer by
the way.
ory
this n a m e is a
of device
ory. We will see later that on a m o u n t
based
ol data used, cost
random access memory
dilferent types of
and requirements on speed.

P2P to be
deterministic?

Does access to RAM need

of the device. For example, in

relates to configuration
Configuration data: This data name-telephone number
in the form
the phonebook
of off and
store switched
DECT" phones we can
to remain
intact if the phone is
Now this phonebook is expected entries can be added,
deleted and
pairs. that
However, it is also expected of being altered.
back o n again. should be capable
This kind of memory
over again. sort of mixed type
changed over and data is not lost at switch off. It is a
volatile so that the
It should not be
on
does not have very
stringent requirements
memories. This memory
of the earlier non-volatile and changeable.
should be
So this memory
speed though.
PROCEDURE
3.1 MEMORY ACCESS
into memory. This procedure
used to read and write
A access is the procedure controller to generate cor
memory involves the memory
to memory
to control each This is done based
access
used be accessed.
location needs to
which memory
rect signals to specify shows up on the data bus connected to

of data by the program. The data

on the access
device that requested it.
the processor
or any olher
a 16MB chip
and columns of data. For example,
as rows
Memory chips are organised
m e a n s that there are
4M (4,194,304) addresses
4Mx4 block. This
can be accessed as a called
locations-sometimes
4,194,304 different memory
there are
with 4 bit each; so
2 ^22, which means
equal to
cells-each of which contains
4 bits of data. 4,194,304 is in
locations. Thus,
address that number of memory
22 bits are uniquely
required to
are required.
theory 22 address lines
DECT-Digitally Enhanced Cordless Telephone.
 1ypes of Memory 53
However, in practice, memory chips do not have these many address lines. They
are instead logically organised as a "square" of rows and columns-sometimes called
hitlines and wordlines respectively. The low-order 11 bits are considered the "row"
and the high-order 11 bits the "column". First the row address is sent to the chip,
and then the column address. For example, let's suppose that we want to access
memory location 3,780,514 in this chip. This corresponds to a binary address of
1110011010111110100010". First, "11110100010" would be sent to select the "row", and
then "11100110101" would be sent to select the column. This combination selects the
unique location of memory address 3,780,514. The active row and column then sends
its data out over the data bus by the data interface.

Figure 3.1 shows at a conceptual level, an example of memory access with an 8*8 row
and column grid. Note that the grid does not have to be square, and in fact in real life
it's usually a rectangle where the number of rows is less than the number of columns.

P2P
What is the advantage of using a rectangular address grid?

Address bus Data bus

Column address
decoder

Row address
decoder

Data
Output/nput

Fig. 3.1 Memory access

 Embedded Realtime Systems Programming
54
selected and set: ro
to how a particular cell on a spreadsheet is row 34, Let us try to u
This is analogous
column "J" to find cell "J34". Similarly, for example, how do Table 3.1.
say, and then look at Anand yesterday in New V
connoisseurs track the made by Vishwanathan
moves

label the chessboard by rowsI to8, and column aa Lo Pin number

Elementary, my dear Watson, just
.

a series of digit-alphabet combinations. 1 to 5

8. Now, all m o v e s c a n be represented by
e t us now get back to the world of memory chips 9. I1 we apply common sense 6
se to
this theory, we can argue that designing memory chips in this manner is both m. 7
ore
complex and slower than just putting one address pin on the chip 1or each address line 8
required to uniquely address the chip-why not just put 22 address pins on the chins 9
ip
he answer may not surprise many people: it is all about cost finally. Especially when
nen 10
SO many embedded systems do not have hard real time constraints, we can still live by
11
with few memory-access delays if it makes the system
a By using
simpler and cheaper. 12
the row/column method, it is possible to greatly reduce the number of pins on the
DRAM chip (We will explain how this "D" came before RAM very soon ) . Here, 11 13
address pins are required instead of 22. However it should be noted that additional 14 to 16

signaling is required so that the memory chip and the accessing device are always syn
Table 3.1: Expla=
chronised about what they are expecting. This signaling pin is usually called probe or
chip select. One thing is for sure: everything else remaining constant, having to send The function
the address in two "chunks" slows down the addressing process, but by keeping the chip
Vcc TH
smaller and with fewer inputs we gain in terms of power consumption and space
of reduction in number of The pins). in further GND
(because reduction power consumption
leads to an increase in the speed of the chip, partially offsetting the loss in access speed.
a WE
chip with 8 address lines and two data lines.
Figure 3.2 shows a
typical memory selected f
and pins
means th
data is ag
the Dou
o RAS a
area are

thatat
When I

assume
synchro
This is not er
and a write op
same pin for o
Fig. 3.2 A memory chip
 55
Types of Memorn
aid of
Let us try to understand the different parts of this memory chip with the
Table 3.1.

Pin number Name Description

I to 5 A0 to A4 Address lines
6 WE Write Enable
CS Chip Select

8 Dout DATA Out

9 GND Ground
10 Din DATA IN

11 Vcc Power Source

12 RAS Row Address Select
CAS Column Address Select
13
14 to 16 A5 to A7 Address lines

Table 3.1: Explanation of Fig. 3.2

The functions of various pins are described as following:

Vcc This is the pin through which the chip receives power for functioning.

GND This is the Ground pin required for any electric circuit

aWE Write Enable. When this pin is asserted, this means that the chip has been
selected for writing. This also means that the data will be sent through the Din pin
and pins A0 to A7 specify the location of this data. When the WE pin is low, this
means that the chip has been selected for reading." In this case, the location of the
data is again specified through address pins A0 to A7. The data flows out through
the Dout pin.
a RAS and CAS As we noted before, the rows and columns inside the memory
area are addressed one at a time. Hence there must be a way of telling the chip
that at this moment, the address lines specify a row number or a column number.
When RAS is set high, a row address is specified, otherwise a column address is
assumed. As we mentioned before, these are the additional pins required for
synchronisation in order to reduce the number of pins for address bus

This is not entirely true though. Some chips have other mechanisms to distinguish between a read
and a write operation. However for simplicity reasons, and to make the concept clear. let us reuse the
Same pin for our illustration.
56 Embedded Realtime Systems Programming

With the aid of Figs. 3.3 and 3.4 respectively, let us trace the steps for read and .
Tite
operations through this chip.

RAS

CAS
Don't care
A0 ROW COL

WE

Din DATA

Fig. 3.3 Write operation in a memoy chip

For writing:
i. The address of the cell to be written to is placed on the address pins via the
address bus This is done by first setting the RAS and puting appropriate row
number followed by setting the CAS and putting appropriate column number
on the address bus.
ii. Set the Write Enable pin: The bit that needs to be stored in the chip is sent on
the Data In pin via the data bus.
iii. Chip select is activated to select the memory chip: When all these operations

are performed simultaneously, a bit on Din pin is written inside the chip at the
address specified by the address bus.

RAS

CAS
Don't care
A0-A7 ROW cOL
WE

Dout
tAC
DATA
Fig. 3.4 Read operation in a memory chip
 Types of Memory 57

For reading:

. The address of the bit to be read is put on the address pins via the address bus.
RAS and CAS pins are used appropriately.

i. Chip select is turned high to select the memory chip.

ii. Write Enable pin is turned low so that the chip knows it's being read from.
iv. When all these conditions are active simultaneously, data appears on the Dout
pin from the address specified by the address bus.
bit at time.
In actual practice, memory is accessed at least a byte at a time, and not a a

This is accomplished by stacking each such chip into blocks of eight and combining the
bit-data streams from these eight chips. When these chips need to be addressed, the
all address
Chip select is enabled on all of them, and the same address is specified
on

can again be stacked

lines. Depending on the capacity of the data bus, each such block
to make mega-blocks that can service data in multiples of a byte.

Definition
from the start of
The amount of time that it takes for the memory to produce the data required,
the access until when the valid data is available for use, is called the memory's access time,
abbreviated tAC (See Fig. 3.4).

Access time is normally measured in nanoseconds (ns). Memory available today nor-

time ranging from 5 to 70 nanoseconds.

mally has access

3.2 TYPES OF MEMORY

Let look at each below.

Figure 3.5 identifies the different types of memory. us

3.2.1 RAM
Random access memory (RAM) is a read-write memory. RAM is considered "ran-
dom access" because any memory location can be accessed directly instead of a sequen-
tial operation from the beginning of the memory. Being random access does not define
this kind of memory completely. It is sufficient to distinguish it from its opposite, serial
access memory (SAM). SAM stores data as a series of memory cells that can only be
accessed sequentially (like a cassette tape). Data is searched from the beginning of the
until it is found end-of-memory is reached. SAM works very well for
memory or

stored in the order in which it will be used

memory buffers, where the data is normally
a good example is the texture buffer memory on a video card). A random access
58 Embedded Realtime Systems Programming
memory on the other hand can directly address
particular portions of memor
makes it fast and expensive as compared to SAM. This
RAM is the place in embedded systems where usually, the
data in current use are
program, its
stack
kept so that the processor can
quickly reach it. At the bein
and
and

of execution (switch on of the

is used since it is
these
system), initial values are loaded inside RAM
R pnning
much faster to read from and write to than its distant M
cousin: the ROu
However, the data in RAM is volatile and stays there
ered up. When the
only as long as the system is Dow
system is turned off, RAM loses its data. When the
switched on again, the svstem
binary image is again loaded from ROM and all stack and s dats
is again initialised. data

Tips
Who loads this program and data inside
data and its required space inside RAM
RAM It is the job of your program to know the amount of

Memory

RAM ROM

DRAM SRAM PROM

SDRAM EPROM

ADRAM EEPROM

FLASH
DDRAM

Fig. 3.5 7ypes of memorn

 Types of Memory 59

DRAM

DRAM or the Dynamic RAM is a very volatile memory. It is not able to store iníor
mation even for a few milliseconds even if power is available to the chip. The storage
forgetting the data stored it. It periodically requires a refresh
medium keeps on on

circuit in order to prevent loss of data. Here we need to address two questions:

Why use a memory that is not able to memorize?and;

How do we make sure that the DRAM indeed stores the data correctly?
The answer to the first question is 'cost'. DRAM is one of the cheapest forms of mem
it forgets any stored data in 5 6 hundredths of a second if
ory. Typically, completely
or

a mechanism does not

exist to retain it.

need to
The answer to the second question is a subtler one. To understand it, we

introduce a little bit of techniques about electric charge and capacitors.

DRAM is implemented in the form of a series of microcapacitor-transistor pairs that

store charge inside them in order to 'remember' the data stored. The capacitor holds
one bit of information-either l or 0. The transistor is meant to manage the operation
of the capacitor reading, writing, changing state, etc.
Now, capacitors have a curious property that they cannot store charge for a long
time unless refreshed by a source of power. In
time. They tend to get discharged over

that sense, a capacitor is a sort of leaky bucket with a certain rate of outflow of charge
while storing the data. Therefore, we need a source of power anda 'refresh circuit' that
from discharging. The refresh
keeps on feeding energy in order to prevent the capacitor
circuit simply restores a full charge to those bits that were remembering to be Is. Hence
in order
typically several hundred times per second, the capacitors require reminding
io keep the memory intact.
This reminding process is called 'refreshing' the memory, and DRAMs use a wide
cruise through the vast
variety sophisticated refresh circuits which do nothing but
of
and re-
DRAM memory array polling each bit for its content before it fully forgets,
The disadvantage of this type of
eling the memory what it is supposed to remember.
structure. Having a mem-
ephemeral memory is offset by its very tiny size and simple
thus reducing cost
Ory cell so small allows us to put more of them on any given device,
considerably.
actual memory array and the
diagram containing the
asso-
1gure 3.6 shows a block
The lelt part ligure of the is the
cated circuitry to perform the refresh operation.
DKAM controller. Now, Reading from or writing to a DRAM cell relreshes its charge,
 Embedded Realtime Systems Programming
60
on reading periodically Irom each cell. For
or that rea
so the DRAM controller just keeps
The DRAM controller
son there is a
refresh timer inside the ligure. takes
care of takes
refreshes and making sure that they
don't interfere with regula
scheduling the
the processor or some DRAM
other device.
regular reads
controlla..
and writes generated by
RAS repealedly and placing a
ically sweeps through all ofthe rows by cycling
row addresses on the address bus. The upside ol a DRAM is that since it is so s
it is small in size and less expensive. The downside is that all this refreshing tab simple,
and slows down the memory, particularly as compared to its sister-the SRAM.

Note

Earlier in the chapter, we had pointed out that a DRAM dhip is usually in theform of a rectangle
instead
of being a square. Noue is the time to explain this fact. Since DRAM uses RAS to periodical
swep through the entire RAM area, this operation will be faster ifthe number of rows is less becaue
the fewer rows the chip has, the less time il takes to refresh all the rows.
Consequently, DRAM makes
design DRAMs with fewer rows than columns thus resulting ina rectangular layout.

RAS
CAS Control clock Power
WE

Refresh

Row
Memory Din
Dout
Col

Fig. 3.6 Block diagram for DRAM

As DRAMs became more sophisticated, it became common to put this refresh cr

cuit from the system board directly onto the DRAM chip itself. When this is done, from
the outside, it appears that the
memory is behaving statically since it does not requ
any refresh circuit from outside. In reality, however, it is still a DRAM since each
me
ory cell is being constantly relreshed on the chip; only the ol
position of the sour
refresh operation has changed. When the refresh circuit is DRAM
integrated with the D
chip, the device is called a Pseudostatic DRAM.
 Types of Memory 61
DRAM is of two kinds: asynchronous and synchronous. An asynchronous DRAM
has the freedom to start its operations irrespective of the clock. However, this requires
some time for co-ordination between the different pins in order to judge the change of
configurations on the pins. SDRAM or the synchronous dynamic RAM is called so
because this memory marches in step with the system clock instead of allowing itself the
asynchronous freedom to respond at its own pace and on its own schedule. SDRAM
"locks" (synchronises) the memory access to the CPU clock. This way we get faster data
transfer. While one portion of data is transported to the CPU another may be being pre-
pared for transfer. Additionally, it stays on the row containing the requested bit and
moves rapidly through the columns, reading each bit as it goes. The idea is that most
of the time, the data asked for from the device will be in consecutive locations inside
memory. To understand why, let us take a look at Fig. 3.7, where we show an asyn-
chronous operation of reading two bits.

RAS

CAS

A0-A7 ROW- coL COLy

Dout DATA DATA

Fig. 3.7 Operation of asynchronous DRAM

For each operation, synchronisation has to be maintained between RAS, CAS, etc.
In Fig. 3.8, a corresponding
operation for SDRAM has been illustrated. Data starts to
be read from contiguous memory locations after the bitline and
wordline have been
specified. Each clock tick initiates a read operation from the next wordline.

RAS

CAS

A0-A7 ROW COLx

Dout
DATA DATA DATA
Fig. 3.8 Readoperation in SDRAM
 62 Embedded Realime Systems Programming

SDRAM typically has an access time of only G-12 ns. Another variant of SDRAM
M is
called DDR RAM or a double density RAM. It is a new technology and is a cl
lock
doubled version of SDRAM, which is replacing SDRAM nowadays.

SRAM
SRAM or static RAM is so called because it retains any informaton stored in it, as lu
as
power is maintained. The data just sits there, calmly awaiting retrieval ong
by the sysite
command. Upon receiving an order to overwrite the data or to prOvide some
being retained, the SRAM is very fast to respond. That's one ol its endearing qualiti
data
lities.
SRAM uses a completely different mechanism for storage ol inlormation. An SRAM
cell is
AM
usually made up of a flip-flop gate whichfurther comprises of about 4 to 6
tran
S1stors, arranged in a configuration that traps either a binary I or a binary 0 in betw
them until that value is either written over with a new value or the tween
power goes out. This
configuration never needs refreshing unless power is switched off. This makes SRAN
much faster in response time than DRAM and
very power efficient. SRAM Can .
made with a rise time as short as 4 ns.
However, because it has more cells, each cell o
the SRAM takes more
space as compared to a DRAM cell. This means that a
not hold as
many cells as that of DRAM. This makes SRAM more
chip can.
pared to DRAM. SRAM is expensive as com.
normally
time, like for example cache.
used in places that require a
very quick response

3.2.2 ROM
ROM, or the read only
memory, as the name
suggests is
only read from. This means that ROM a
memory
can
in which we
cannot be written
ry will retain its contents even
when the power is again and again. This memo
used to store switched off. Hence this
anything
that needs to be used
after the memoryy is
on
again. What kind of information system has been switched off
and
will be executed on can this be? This is
the embedded
system. Since this
usually the actual program that
switch-ofT, it is also called nonvolatile memory." memory does not get erased at
Because of the it stores
way information (as we
compared to RAM, typically will see
having double the access time soon),
of
ROM much slower
is
One term that RAM or more. Howevel.
often confuses people is that
write and ROM is
read-only RAM is the
not random
access. This is notmemory. Hence, since RAM "opposite" of ROM because RAM
true. ROM is
also a randomstands for "random access memory15 TeROMi
can be read
in any
ories order, it is just not
introduced in the writeable. RAM gets itsaccess
memory. Inside ROM, any cation
with RAM even beginning
though it is no longer sequential, and did not allowbecause primitive read-WIToa nem
were name
relevant. random access. Ine
a
 iant of SDRAM 63
y and is Types of Memory
a Mis this limitation
clock it is expected that ROM need not be accessed as

be lived with. This,

frequently
combined with the fact that ROM is
as RAM, so

considerably cheaper as
can
to RAM per byte, definitely has its own advantage.
compared
ored in it, as
val by the long Definition

ovide somesystdatema RAMis often used to shadow parameters stored in EEPROM (RAM is mapped to
memory space) to improve performance. This technique is called 'ROM
ROM's
shadowing'.
dearing qualities, times
While the purpose of a ROM is that its contents cannot be changed, there a r e
atio. An SRAM when being able to change the contents can be very useful. Sometimes
it is desirable
bout 4 to 6 and it should be
ry O in tran that the memory remains read-only for all normal circumstances
in a mobile phone,
r between
goes out. This
possible to over-write it by specially defined processes. For example,
it will be worthwhile to store a specific type of ringer tone into such memory that cannot

makes SRAM be erased when the phone is switched off. However, it should also be possible to update

SRAM can be this tone from time to time.

lls, each cell of Similarly, the user settings inside a
washing machine need to be nonvolatile from the
that a chip can switch off point of view. However, it should be possible to set different setting for dif-
ensive as com ferent clothes (cotton, wool..) and mode of operation (spin dry, double wash...
quick response Hence, there exist a lot of ROM variants that can be changed under certain circum-
stances; these can be thought of as "writeable nonvolatile memory". The following
sections describe the different types of ROMs with a description of their relative
modifiability.
which we can
. This memo Regular ROM
is memory is A regular ROM is constructed from hardwired logic, encoded in the silicon itself, much
tched off and the way that a processor is. It is designed to perform a specific function and cannot be
program that changed. This is inflexible and so regular ROMs are generally used only for programs
get erased at that are static (not changing often) and mass-produced. ROM is analogous to a com-
mercial software CD-ROM that can be purchased in a store.
much slower While RAM uses a transistor and capacitor combination to store data, ROM uses an
r e . However, electric diode at the junction of row-column to determine whether a 1 or a 0 has been
stored at the location. When the ROM chips are "burned", the cells where a I has
M is read-
be stored have a connected diode. The cells where a 0 has to be stored have an uncon-
ory", ROMis
nected electric circuit. The diodes in these intersections allow he llow of current in
a n yl o c a t i o n

only one direction. Like all diodes, a voltage above the break over voltage (of the order
ad-writemem
name stays
of 600 mVolts) is needed so that the diode passes current. To determine whether a cell
64 Embedded Realtime Systems Programming
has a 0 or a 1, a
voltage above 600 mV is applied to a column while
grounded. If the diode is keepingng the row
connected, the current will be conducted to the groina
this method, the status of each cell can be read. d. Using
Obviously, since there is
physical presence of a diode to indicate a 1 in a coll
kind of memory cannot be changed and reused. Once the ROM is
ROM manufactured i, this
only be read. And if there are some bugs in the values, well, unfortunately, the manufactured,
chip has to be thrown. This makes the chip design process long and whole
the upside, ROM chips are cumbersome On
very cheap for mass-production, have high reliability
a
long duration and they consume very less power.

Programmable ROM (PROM)

The limitation of a regular ROM is that it can be burned only once. PROM is a tn
of ROM that can be programmed using ype
special equipment; it can be written to, but onl
once.This is useful for companies that make their own ROMs from software
they te,
because when they change their eode they can create new PROMs without
requirin
expensive equipment. This is similar to the way a CD-ROM recorder works h
"burning' programs onto blanks once and then providing the facility to read from them
many times.

Just like regular ROM, a PROM chip has a grid of rows and columns. In order to
make it changeable once, each cell has a small fuse in it, (logically the same as we
have in our homes for checking electric malfunction). In normal circumstance when
the PROM chip is created, all cells have a value of 1. An electric charge can pass
through the fuse. To change the value of a cell to 0, a high voltage is sent to the cell
thus breaking the fuse. The electric circuit is left open and a 0 gets created at this
position.
This process makes it possible to change the PROM chip, but only once. PROM
chips are very fragile but cheap. As discussed above, they are generally used lor
prototyping data for a regular ROM before committing to the costly fabrication o
ROM chip.

Erasable programmable ROM (EPROM)

ocess.
As the name suggests this kind of ROM is nonvolatile but erasable by a special pro
are

Once again, it is a mesh of rows and columns and this time inside each celltne re
sistors

two transistors technically called the control gate and floating gate. The two tran
h the
are separated by a thin oxide layer. At an erased state, electricity can pass tni
 Types of Memory 65
and a value
the row Oxide layer and link the two (hus linking the row and column)
transistors

nd. Using is used to program a value

is indicated. A process called Fowler-Nordheim tunneling
of 1 to 13 volts, is applied to the floating
cell. An electric charge, usually 10
of O inside the electron and the
gate to act like gun an
cell, this This high voltage floating
causes the
gate. At this time, the
ed, it can are pushed hrough
the oxide layer where they get trapped.
electrons is removed, electric cir
from each other and when the voltage
he whole [wo gates are insulated
detects the level of charge
and value of 0 is indicated. A cell censor
ome. On cuit becomes open
a
indicates a 0 or a 1.
the floating gate, based on which it
ility over passing through
takes care of returning the
electrons back to the floating gate.
The erasing procedure To
for this kind of ROM is also interesting and worth mentioning.
The erasing process
253.7 nanometre is shown through
the EPROM, a UV light source of wavelength
erase
source is kept about
an inch
is a type a quartz
window on top of the EPROM chip. The light
of all cells in the chip. This process is strictly speci
but only from the chip resulting in erasing
duration of the process and positioning
of light
ey write, fied in terms of intensity of UV light,
any deviations may
result in inappropriate erasing.
equiring source,

orks by Electrically erasable programmable ROM (EEPROM)

om them which be erased under software con-
The next level of erasability is the EEPROM,
can

and is now commonly used for hold

trol. This is one of the most flexible types of ROM,
meant to be retained across sessions of the embedded
order to ing configuration and status dala
but
e as we device. Here we are blurring the line a bit between what "read-only" really means,
it should be kept in mind that this rewriting is done maybe once a day or so, compared
ce when
to real read-write memory (RAM) where rewriting is done ofien many times per second!
can pass
the cell EEPROM uses the same setup as EPROM. However, in EEPROM, it is possible to
d al this erase only a portion of the chip or all at once and it is possible to perform this opera-
tion by software control. UV light is nol required for this process. EEPROM uses elec-

PROM tric charge to return the trapped electrons to their original state. No special equipment
used for is required and the chip need not be removed. This electric charge can be targeted at
ation of any data point at any time. Operationally, EEPROM chips change data one byte at a
ime, which makes them versatile but slow.

3.2.3 Flash
process.
Flash memory is similar to EEPROM in design. The dilference is that it can be erased
here are and reprogrammed in blocks instead of one byte at a time. In-circuit wiring is used
O
ansistors apply electric charge to' an entire chip or to specilic sections called blocks, each
ugh the
usualy of size 512 bytes. Being light, compact and energy-eflicient, typical uses of
66 Embedded Realtime Systems Progrumming

FLASH are in CompactFlash, SmartMedia, Memory Stick (most often found in digitsl
cameras), PCMCIA type I and type II memory cards (used as solid-state disks igjital
in
laptops). The original intended usage of FLASH memory was to replace mass storage
devices like disk drives and tapes. Flash memory in the form ol a card or stick is verrage
versatile and can be used across devices if a standard lile system is used to represe
ery
sent
data inside it. This is the concept of so-called linear flash.

There is another kind of FLASH called the ATA flash. An ATA flash memory
nod
ule interfaces with the rest of the system using the de facto "AT Attachment" slandard.
The FLASH gives the illusion that it is made up of sectors ike on a hard disk and the
same APIs can be used as for accessing a disk drive. The main advantages of ATA lash,
from the embedded system developer's perspective, are flexibility and interchange
ability with hard disks. While linear flash modules aren'i 100%o interchangeable
between devices, ATA flash overcomes this limitation by using a standard AT interface
for accessing it. ATA flash can be accessed using an operating system's standard disk
access code and the same file system APls. This aids in cross compaibility.

For example, a memory card inside a digital camera, equipped with flash memory
uses a format to store data that is compatible with the way PC Card stores it. Hence, the
card can just be inserted into a PC card slot and can be read directly by the computer.
Not only does this promote cross compatibility, it aids in debugging as well since the lim
itation of an embedded system (lack of screen and input device) are easily surmounted.

There are additional advantages. Thebuiltin file system is robust enough to perform
some housekeeping tasks. For example, it can detect areas of memory that are defective.
It can then forbid access to these regions for read-write purposes. It can have a
mechanism by which it can create virtual sectors which point to physical sectors in
memory in such a way that read and write accesses to these sectors is evenly spread on
the chip thus preventing heavy usage and associated wear of a particular portion o
the chip. As expected, everything in this world comes with a
price. ATA Flashhasso
many advantages, but all these features make it more expensive and power-hung
Because of speed limitations, flash memories incorporate built-in SRAM buflers, dupl
cating the contents of a block of memory from the flash array for fast access.

3.3 LESSONS LEARNT

Memory is used inside embedded systems in order to store executable code, loadthe
instructions to be executed a a t can

together with their data, to store information *

change between sessions (lor example user preferences). This lerent

gives rise o
 67
Types ofMemory

the
Memory chips usually arranged in
are
inside embedded systems. use the same
ypes
of memory
and columns of data. Typically, memory chips
of rectangles as r o w s
the number of lines
significantly.
form address and reduce
column
for row and
address lines and CAS pins.
read or written
based on the RAS
The data is The random a c c e s s
mem-

based on their usage.

classes of memory contents if the power
There are various and loses its
accessed in a
non-serial way
ory has
the ability to be RAM needs
consant charging

disconnected. It is of
two types: the dynamic static RAM
supply is from forgetting its data. The
it
times a second to prevent memory
is a
typically many its contents. The Read-Only
constant charging for storing o n c e and its
does nol need ROM can be used only
The regular
form of 'not-easily-erasable'
memory.
ROM is capable
after burning it once. The programmable
contents cannot be changed EPROM uses the Fowler
once through
electric current. The
similar to
of being recharged number of times. EEPROM is
contenls any
to erase its software control
Nordheim technique
contents can be erased through
that its
EPROM in operation except in
of EEPROM that can be reprogrammed
Flash is a type
through electric charge. Flash memory has
enhanced cross-compatibility
of
time.
blocks instead of one byte at a
standard AT interface.
through the usage of a
across
embedded devices
memory

3.4 REVIEW QUESTIONS

inside embedded systems? What are

What are the different types of memory

they used for?

the memory access procedure. What is the use of chip select

Describe

function?
rectangles and not squares?
chips usually arranged
as
Why are memory
from SRAM?
How is DRAM different memories?
Whal are the advantages and disadvantages of FLASH over other
which memory would you
use and why?
In orderto store user preferences,
RAM?
"What is meant by an asynchronous