THAMIRABHARANI ENGINEERING COLLEGE

(Approved by AICTE, New Delhi and Affiliated to Anna University, Chennai)

Chathirampudukulam, Chidambaranagar - Vepemkulam Road.
Thatchanallur, Tirunelveli 627 358, Tamil Nadu.

DEPARTMENT OE ELECTRONICS AND

COMMUNICATION ENGINEERING

LAB OBSERVATION

Year & Semester: III Year/V Semester

Subject Code/Name: EC3561 VLSI Laboratory

Faculty In-Charge: Mrs. M.Jenitta,
AP/ECE.

Student Name: ------------------------------------

Register Number: ------------------------------------
 INDEX

Page
S. No. Date Name of the Experiment Mark Signature
No.
 STUDY OF SIMULATION AND
IMPLEMENTATION OF XILINX TOOL

AIM:

To study the simulation and implementation procedures of Xilinx tool and FPGA

STEP1:

Click Xilinx ISE9.1

STEP2:

File ->New project and type the project name and check the top level source type as HDL

STEP3: Check the device properties and click Next

STEP4: Click New Source And Select the Verilog Module and then give the file name

STEP5:

Select the Input, Output port names and click finish.

STEP6:

Type the program and save it

STEP7: Check the synthesize XST and check syntax

STEP8: Select user constraints-> assign package pins, set port numbers and save it then
select IO Bus delimiter as XST default<>->click ok

STEP9:

Double click implement design and click generate programming file->configure

device(impact)->finish then select bit file
STEP10:

Right click on the xc3s400 figure->program->filename then click finish

and finally check the functionality in hardware

Result:

Thus the simulation and implementation procedure of Xilinx and FPGA has been studied.
Ex. No. 1 Prelab Questions Date:
1. What is Verilog HDL?
2. Differentiate simulation and synthesis.
3. What is Intrinsic and Extrinsic Semiconductor?
4. What are the advantages of IC over discrete component circuits?
5. What are four generations of Integration Circuits?
6. What is combinational circuit? Give two examples.
7. What is sequential circuit? Give two examples.
8. What is Flip flop?
9. Differentiate combinational and sequential circuits.
10. What is Multiplexer?
 Exp. No.: 1
DESIGN OF COMBINATIONAL AND
Date: SEQUENTIAL CIRCUITS

AIM:

To design, simulate and implement basic combinational and sequential circuits using Verilog
HDL

APPARATUS REQUIRED:

 PC with Windows XP.

 XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

THEORY:

HALF ADDER:

The half adder consists of two input variables designated as Augends and Addend bits. Output
variables produce the Sum and Carry. The ‘carry’ output is 1 only when both inputs are 1 and
‘sum’ is 1 if any one input is 1. The Boolean expression is given by,

sum = x ^ y carry = x & y

FULL ADDER:

A Full adder is a combinational circuit that focuses the arithmetic sum of three bits. It consists
of 3 inputs and 2 outputs. The third input is the carry from the previous Lower Significant
Position. The two outputs are designated as Sum (S) and Carry (C). The binary variable S
gives the value of the LSB of the Sum. The output S=1 only if odd number of 1’s are present
in the input and the output C=1 if two or three inputs are 1.

sum = x ^ y ^ z

carry= (x & y) | (y & z) | (x & z)

SUBTRACTOR:

In electronics, a subtractor can be designed using the same approach as that of an adder. The
binary subtraction process is summarized below. As with an adder, in the general case of
calculations on multi-bit numbers, three bits are involved in performing the subtraction for
each bit of the difference: the minuend (X_{i}), subtrahend (Y_{i}), and a borrow in from the
previous (less significant) bit order position (B_{i}). The outputs are the difference bit
(D_{i}) and borrow bit B_{i+1}. The subtractor is best understood by considering that the
subtrahend and both borrow bits have negative weights, whereas the X and D bits are
positive.
ALGORITHM:

 New project and type the project name and check the top level source type as HDL
 Enter the device properties and click Next
 Click New Source and Select the Verilog Module and then give the file name
 Give the Input and Output port names and click finish.
 Type the Verilog program and save it
 Double click the synthesize XST and check syntax
 Simulate the waveform by behavioral simulation
 For implementation Select User constraints and give input and output port pin number
 Click Implement design for Translate, map and place & route
 Generate .bit file using programming file
 Implement in FPGA through parallel-JTAG cable
 Check the behavior of design in FPGA by giving inputs

Half Adder:

Program:

Module Half add(a,b,sum,carry);

input a,b;
output sum,carry;
xor (sum,a,b);
and (carry,a,b);
endmodule

Truth table:
Half Adder

Input1 Input2 Carry Sum

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Full Adder:

Program:

module fulladd(sum, carry, a, b, c);

input a, b, c;
output sum, carry;
wire w1, w2, w3;
xor (sum, a, b, c);
and (w1, a, b);
and (w2, b, c);
and (w3, c, a);
or (carry, w1, w2, w3);
endmodule

Truth Table:

a b c carry Sum
- -
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
----- -
HALF SUBTRACTOR:

Program:

module halfSub(a, b, diff, borr);

input a, b;
output diff, borr;
wire s;
not (s, a);
xor (diff, a, b);
and (borr, s, b);
endmodule

Truth Table:

- -
Input1 Input2 Borrow Difference
-
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

FULL SUBTRACTOR:

Program:

module fullsub (a, b, cin, diff, borr);

input a, b, cin;
output diff, borr;
wire w1, w2, w3, w4, w5;
not n1(w1, a);
 not n2(w4, w3);
xor x1(w3, a, b);
xor x2(diff, w3, cin);
and a1(w2, w1, b);
and a2(w5, w4, cin);
or g1(borr, w5, w2);
endmodule

Truth Table:

A B Cin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0

D-FLIPFLOP:
PROGRAM:

Module DFF(Clock, Reset, d, q);

input Clock;
input Reset;
input d;
output q;
reg q;
always@(posedge Clock or negedge Reset)
if (~Reset)
q=1'b0;
else
q=d;
endmodule

Truth Table:

D FLIP FLOP
-
Clock Reset Input (d) Output q(~q)

0 0 0 0(1)
1 0 0 0(1)
0 0 1 0(1)
1 0 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 1 0 1(0)
1 1 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 0 0 0(1)
1 0 0 0(1)
0 0 0 0(1)

T-FLIPFLOP:
PROGRAM:

Module TFF(Clock, Reset, t, q);

input Clock;
input Reset;
input t;
output q;
reg q;
always@(posedge Clock , negedge Reset)
if(~Reset) q=0;
else if (t) q=~q;
else q=q;
endmodule

TRUTH TABLE:
-
Clock Reset Input (t) Output q(~q)

0 0 0 0(1)
1 0 0 0(1)
0 0 1 0(1)
1 0 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 1 0 1(0)
1 1 0 1(0)
0 1 1 1(0)
1 1 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 0 0 0(1)

Result:
Ex. No. 1 Postlab Questions Date:

1. Draw the full adder using two half adder.

2. What are the differences between flipflop and latch?
3. Draw the NAND based SR flip flop.
4. Write the modes of operation of MOS structure.
5. Draw the diagram for inversion mode with voltage conditions.
6. What are the different operating regions for an MOS transistor?
7. What is Enhancement mode transistor?
8. What is Depletion mode device?
9. Write meaning of Toggle in T flip flop.
10. When the channel is said to be pinched off?
Ex. No. 2 Prelab Questions Date:

1. Draw the symbol of enhancement mode and depletion mode MOSFET.

2. What is the fundamental difference between a MOSFET and BJT?
3. Explain why present VLSI circuits use MOSFETs instead of BJTs?
4. Write the formula for gate capacitance in NMOS.
5. What are the two factors we are considering while deriving the equation for Ids.
6. Write the value of Ids in all the three operating regions.
7. What is Body Effect?
8. What is Channel-length modulation
9. What is velocity saturation?
10. What is mobility degradation?
Exp. No.: 2

Date: DESIGN OF ADDER & MULTIPLIER

AIM:
To design and implement 8-bit adder and multiplier using Verilog HDL.

APPARATUS REQUIRED:

 PC with Windows XP.

 XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

ALGORITHM:

 New project and type the project name and check the top level source type as HDL
 Enter the device properties and click Next
 Click New Source and Select the Verilog Module and then give the file name
 Give the Input and Output port names and click finish.
 Type the Verilog program and save it
 Double click the synthesize XST and check syntax
 Simulate the waveform by behavioral simulation
 For implementation Select User constraints and give input and output port pin number
 Click Implement design for Translate, map and place & route
 Generate .bit file using programming file
 Implement in FPGA through parallel-JTAG cable
 Check the behavior of design in FPGA by giving inputs
PROGRAM:
ADDER
module ad(a, b, sum);
input [7:0]a, b;
output [7:0]sum;
assign sum = a+b;
endmodule

Truth Table:
A B RES

- - - - - - - -

1111111 0000000 1111111

RIPPLE CARRY ADDER:

PROGRAM:
module 8bit_fulladder(a, b, cin, sum, cout);
input [7:0]a;
input [7:0]b;
input cin;
output [7:0]sum;
output cout;
wire [7:1]c;
fulladd fa0(a[0], b[0], cin, sum[0], c[1]);
fulladd fa1(a[1], b[1], c[1], sum[1], c[2]);
fulladd fa2(a[2], b[2], c[2], sum[2], c[3]);
fulladd fa3(a[3], b[3], c[3], sum[3], c[4]);
fulladd fa4(a[4], b[4], c[4], sum[4], c[5]);
fulladd fa5(a[5], b[5], c[5], sum[5], c[6]);
fulladd fa6(a[6], b[6], c[6], sum[6], c[7]);
fulladd fa7(a[7], b[7], c[7], sum[7], cout);
endmodule

module fulladd(a, b, c, sum, carry);

input a, b, c;
output sum, carry;
wire w1, w2, w3;
xor (sum,a,b,c);
and (w1,a,b);
and (w2,b,c,);
and (w3,c,a);
or (carry,w1,w2,w3);
endmodule
MULTIPLIER:

module mult(out, a, b);

output [15:0]out;
input [7:0]a;
input [7:0]b;
assign out=a*b;
endmodule

TRUTH TABLE:

--------------------------------------------------------

A B RES

---------------------------------------------------------

00001000 00001001 00001000

----------------------------------------------------------

ARRAY MULTIPLIER: (4 bit)

Program:
module 4bit_mul(y, a, b);
output [8:1]y;
input [4:1]a;
input [4:1]b;

assign y[1] = a[1]&b[1];

wire p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15, p16, p17;

HA HA1(y[2], p1,(a[2]&b[1]),(a[1]&b[2]));
HA HA2(p2, p3, (a[2]&b[2]), a[3]&b[1]);
HA HA3(p4, p5, (a[3]&b[2]), a[4]&b[1]);
FA FA1(y[3], p6, (a[1]&b[3]), p1, p2);
FA FA2(p7, p8, (a[2]&b[3]),p3, p4);
FA FA3(p9, p10, (a[4]&b[2]), (a[3]&b[3], p5);
FA FA4(y[4], p11, (a[1]&b[4]), p6, p7);
FA FA5(p12, p13, (a[2]&b[4]), p8, p9);
FA FA6(p14, p15, (a[4]&b[3]), (a[3]&b[4]), p10);
HA HA4(y[5], p16, p11, p12);
FA FA7(y[6], p17, p13, p14, p16);
FA FA8(y[7], y[8], (a[4]&b[4]), p15, p17);
endmodule

module HA(s, c, a, b);

input a, b;
output s, c;
assign s = a^b;
assign c = a&b;
endmodule

module FA(s, cout, a, b, cin);

input a, b, cin;
output s, cout;
assign s = (a^b^cin);
assign cout = (a&b)|(b&cin)|(cin&a);
endmodule

Result:
Ex. No. 2 Postlab Questions Date:

1. How the carry look ahead adder differ from 4 bit parallel full adder?
2. Draw the circuit of 4bit ripple carry adder.
3. Draw the full adder circuit using half adders.
4. Multiply the number 1101 and 1001
5. What is CMOS Technology?
6. Give the advantages of CMOS IC.
7. What is the relation between addition and multiplication operation.
8. For a particular design of multiplication unit with 6 bit multiplicand and 3 bit multiplier how
many number of adders required?
9. Draw the graph showing the five different operating regions of CMOS inverter.
10. Define Threshold voltage in CMOS.
Ex. No. 3 Prelab Questions Date:

1. What is a module in Verilog and how is it used?

2. List the various levels of abstraction in Verilog HDL.
3. Mention the steps in VLSI design flow.
4. What is Latch Up? How do you avoid Latch Up?
5. Draw the CMOS NAND logic.
6. What is register?
7. What are the types of shift register?
8. Why NMOS technology is preferred more than PMOS technology?
9. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
10. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
 Exp. No.: 3
DESIGN & IMPLEMENTATION OF
Date:
UNIVERSAL SHIFT REGISTER

AIM:

To implement Universal Shift Register using Verilog HDL

APPARATUS REQUIRED:

 PC with Windows XP.

 XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

ALGORITHM:

 New project and type the project name and check the top level source type as HDL
 Enter the device properties and click Next
 Click New Source and Select the Verilog Module and then give the file name
 Give the Input and Output port names and click finish.
 Type the Verilog program and save it
 Double click the synthesize XST and check syntax
 Simulate the waveform by behavioral simulation
 For implementation Select User constraints and give input and output port pin number
 Click Implement design for Translate, map and place & route
 Generate .bit file using programming file
 Implement in FPGA through parallel-JTAG cable
 Check the behavior of design in FPGA by giving inputs

THEORY
A Universal Shift Register is a register which can shift its data in both directions i.e., left and right
directions. In other Words, a universal shift register is a bidirectional shift register. It is combination of
design of bidirectional shift register and a unidirectional shift register with the parallel load provisions. It
can perform parallel to serial operation (first loading parallel input and then shifting). A universal shift
register can also perform serial to parallel operation (first shifting and then retrieving parallel output).
 LOGIC DIAGRAM

PROGRAM:

module universal_shift_register (clr,clk,sel,parin,out);

input clr,clk;
input [1:0]sel;
input [3:0]parin;
output reg[3:0]out;

always @(posedge clk)

begin

if(clr)
out=4'b0000;

else
begin
case(sel)
2'b00: out=out;
2'b01: out={parin[0],parin[3:1]};
2'b10: out={parin[2:0],parin[3]};
2'b11: out=parin;
endcase
end

end
endmodule

RESULT:
Ex. No. 3 Postlab Questions Date:

1. Why PMOS and NMOS are sized equally in a Transmission Gates?

2. What happens when the PMOS and NMOS are interchanged with one another in an inverter?
3. Why are pMOS transistor networks generally used to produce high signals, while nMOS
networks are used to produce low signals?
4. What are the different data types available in Verilog HDL?
5. Write the difference between reg and wire data types.
6. Write the difference between blocking and non-blocking statements with an example for each.
7. In CMOS technology, in digital design, why do we design the size of pmos to be higher than
the nmos.
8. Write about the skewed inverters.
9. What is Noise margin?
10. What is Low noise margin?
Ex. No. 4 Prelab Questions Date:

1. What is High noise margin?

2. Mention the name of the device used in pull up and pull down network.
3. What are the two types of procedural blocks in Verilog?
4. Write the difference between the procedural blocks?
5. What is meant by scaling?
6. What are the types of scaling?
7. What is RTL design in VLSI?
8. By what factor RDS should be scaled, if constant electric field scaling is employed?
9. What is interconnect?
10. List the sources of power dissipation in CMOS circuits.
 Exp. No.: 4
DESIGN & IMPLEMENTATION OF
Date:
MEMORIES

AIM:

To implement Memories using Verilog HDL

APPARATUS REQUIRED:

 PC with Windows XP.

 XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

ALGORITHM:

 New project and type the project name and check the top level source type as HDL
 Enter the device properties and click Next
 Click New Source and Select the Verilog Module and then give the file name
 Give the Input and Output port names and click finish.
 Type the Verilog program and save it
 Double click the synthesize XST and check syntax
 Simulate the waveform by behavioral simulation
 For implementation Select User constraints and give input and output port pin number
 Click Implement design for Translate, map and place & route
 Generate .bit file using programming file
 Implement in FPGA through parallel-JTAG cable
 Check the behavior of design in FPGA by giving inputs

THEORY:

A single port RAM is a that RAM in which only one address can be accessed at a particular time.
The address can be accessed for read operation or write operation at a particular interval of time. Single
port RAM allows only one memory cell to be read or write during each clock cycle. It has one
enable(en) input and one write(we) input. If both are logic ‘1’, data is written into RAM and enable(en)
is logic ‘1’ and write (we) is logic ‘0’, then the data is read from the RAM.
PROGRAM:

module single_port_ram(data_in, ram_address, write_enable, clk, data_out);

input [7:0]data_in;
input [5:0]ram_address;
input write_enable;
input clk;
output [7:0]data_out;

reg [7:0] ram_memory[31:0]; // a 32 byte ( 32*8 bit) RAM

reg [5:0] address_register;

always @(posedge clk)

begin
if (write_enable) // write operation
ram_memory[ram_address] <= data_in;
else
address_register <= ram_address;
end
assign data_out = ram_memory[address_register];
endmodule

RESULT:
Ex. No. 4 Postlab Questions Date:

1. What is the need for clock signal in sequential circuits?

2. What are set up time & hold time constraints? What do they signify?
3. What is standard cells in VLSI?
4. Difference between semi-custom design and full custom design.
5. Define propagation delay??
6. Define RC delay model?
7. What is Elmore’s constant?
8. What happens to delay if you increase load capacitance?
9. What is the difference between RTL and Gate level?
10. Mention what are the two types of procedural blocks in Verilog?
Ex. No. 5 Prelab Questions Date:

1. Define Logical effort.

2. Define Parasitic delay.
3. What is stick diagram?
4. Draw the stick diagram for Y=[(A+B)C]’
5. How the layout diagram differs from stick diagram?
6. Define any two Layout Design rules
7. What is the need for memory element in sequential circuits?
8. What is meant by bubble pushing?
9. Define input ordering delay effect?
10. Differentiate Verilog HDL and VHDL.
Exp. No.: 5 DESIGN & FPGA IMPLEMENTATION OF
Date: FINITE STATE MACHINE
(MOORE/MEALY
MACHINE)

AIM:

To implement finite state machine (Moore/Mealy machine) using Verilog HDL

APPARATUS REQUIRED:

 PC with Windows XP.

 XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

ALGORITHM:

 New project and type the project name and check the top level source type as HDL
 Enter the device properties and click Next
 Click New Source and Select the Verilog Module and then give the file name
 Give the Input and Output port names and click finish.
 Type the Verilog program and save it
 Double click the synthesize XST and check syntax
 Simulate the waveform by behavioral simulation
 For implementation Select User constraints and give input and output port pin number
 Click Implement design for Translate, map and place & route
 Generate .bit file using programming file
 Implement in FPGA through parallel-JTAG cable
 Check the behavior of design in FPGA by giving inputs

MOORE MACHINE:
PROGRAM:
module moore( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @(posedge clk, posedge rst)
begin
if(rst)
state <= 2'b00;
else
begin
case(state)
2'b00:
begin
if(inp)
state <= 2'b01;
else
state <= 2'b10;
end
2'b01:
begin
if(inp)
state <= 2'b11;
else
state <= 2'b10;
end
2'b10:
begin
if(inp)
state <= 2'b01;
else
state <= 2'b11;
end
2'b11:
begin
if(inp)
state <= 2'b01;
else
state <= 2'b10;
end
endcase
end
end
always @(posedge clk, posedge rst)
begin
if(rst)
outp <= 0;
else if(state == 2'b11)
outp <= 1;
else
outp <=0;
end
endmodule
MEALY MACHINE: State diagram

PROGRAM:

module mealy(clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;

always @(posedge clk, posedge rst)

begin
if(rst)
begin
state <= 2'b00;
outp <= 0;
end

else
begin
case(state)
2'b00:
begin
if(inp)
begin
state <= 2'b01;
outp <= 0;
end
else
begin
state <= 2'b10;outp
<= 0;
end
end

2'b01:
begin
if(inp)
begin
 state <= 2'b00;
outp <= 1;
end
else
begin
state <= 2'b10;
outp <= 0;
end
end

2'b10:
begin
if(inp)
begin
state <= 2'b01;
outp <= 0;
end
else
begin
state <= 2'b00;
outp <= 1;
end

end

default:
begin
state <= 2'b00;
outp <= 0;
end
endcase
end
end
endmodule

RESULT:
Ex. No. 5 Postlab Questions Date:

1. State the difference between System Verilog and Verilog in RTL design.
2. What are the drawbacks of Ratioed circuits
3. What is Pseudo-nMOS?
4. Draw the Pseudo-nMOS 2 input NAND gate
5. What is charge sharing in dynamic CMOS logic?
6. What is foot in Dynamic circuits?
7. Define Monotonicity problem.
8. How to avoid monotonicity problem in dynamic CMOS?
9. Compare CPL and CVSL
10. Define Pass transistors.
Ex. No. 6 Prelab Questions Date:

1. What is transmission gate.

2. Using transmission gate draw a 4:1 MUX.
3. Write about the DRC verification process?
4. State the operation performed during precharge and evaluation phase of dynamic circuits.
5. Draw the footed and unfooted dynamic CMOS inverter.
6. Define Keeper circuit.
7. What is meant by bistability?
8. Compare SRAM and DRAM.
9. Draw the MUX based nMOS latch.
10. Draw the MUX based positive level sensitive D latch.
 Exp. No.: 6
DESIGN & FPGA IMPLEMENTATION
Date: OF 3-BIT SYNCHRONOUS UP/DOWN
AND 4-BIT ASYNCHRONOUS
UP/DOWN COUNTER

AIM:

To implement 3-bit Synchronous up/down counter and 4-bit Asynchronous up/down counter
using Verilog HDL

APPARATUS REQUIRED:

PC with Windows XP.

XILINX 9.2i
FPGA-SPARTAN-3 KIT
PARALLEL TO JTAG CABLE
.
ALGORITHM:

 New project and type the project name and check the top level source type as HDL
 Enter the device properties and click Next
 Click New Source and Select the Verilog Module and then give the file name
 Give the Input and Output port names and click finish.
 Type the Verilog program and save it
 Double click the synthesize XST and check syntax
 Simulate the waveform by behavioral simulation
 For implementation Select User constraints and give input and output port pin number
 Click Implement design for Translate, map and place & route
 Generate .bit file using programming file
 Implement in FPGA through parallel-JTAG cable
 Check the behavior of design in FPGA by giving inputs
THEORY:

A 3-bit synchronous down counter is a digital circuit that counts down from a preset value
to zero using three flip-flops to represent the binary count. It operates synchronously, utilizing clock
signals and synchronous logic to ensure precise counting in a downward sequence.

In the asynchronous 4- bit up counter, the flip flops are connected in toggle mode, so when
the when the clock input is connected to first flip flop FF0, then its output after one clock pulse will
become 20. The rising edge of the Q output of each flip flop triggers the clock input of its next flip flop.
3 BIT SYNCHRONOUS UP/DOWN COUNTER

PROGRAM:

module sync_updown_counter(clk, reset, up_down, count);

input clk, reset, up_down;
output [2:0]count;
reg [2:0]count;
always @(posedge clk)
begin
if(reset)
count <= 0;
else if(up_down==1)
begin
if(count==7)
count <= 0;
else
count <= count + 1;
end
else if(up_down==0)
begin
if(count==0)
count <= 7;
else
count <= count - 1;
end
end
endmodule
4 BIT ASYNCHRONOUS UP/DOWN COUNTER

PROGRAM:

module async_updown_counter(clk, reset, up_down, count);

input clk, reset, up_down;
output [3:0]count;
reg [3:0]count;
always @(posedge clk or posedge reset)
begin
if(reset)
count <= 0;
else if(up_down==1)
begin
if(count==15)
count <= 0;
else
count <= count + 1;
end
else if(up_down==0)
begin
if(count==0)
count <= 15;
else
count <= count - 1;
end
end
endmodule

RESULT:
Ex. No. 6 Postlab Questions Date:

1. Define clock skew.

2. Define Clock jitter.
3. Define clock gating.
4. Define Mealy circuit.
5. Define Moore circuit.
6. Differentiate Moore and Mealy circuits.
7. Differentiate Synchronous and Asynchronous sequential circuits.
8. What is C2MOS register.
9. Write the principle of C2 MOS – A clock skew insensitive approach.
10. What is NORA CMOS?
Ex. No. 7 Prelab Questions Date:

1. Define TSPCR.
2. What is Pipelining?
3. Write two examples for Non-bistable circuits.
4. Write any two properties of Schmitt Trigger.
5. How to avoid clock overlapping in dynamic latches?
6. Define data path. List out its components.
7. Summarize about carry propagation delay.
8. Write the equation for critical path delay of 4bit ripple carry adder.
9. Mention the effect of carry propagation delay in circuits.
10. Mention the type of adders used in multiplier circuit.
 Exp. No.: 7
LAYOUT EXTRACTION AND
Date: SIMULATIONOF C-MOS BASIC GATES
AND FLIP FLOPS

AIM:

To draw the layout of CMOS basic gates (Inverter, NAND and NOR) and flip flop.

SOFTWARE USED:
 Microwind
 DSCH

DESCRIPTION:

CMOS INVERTER:

The NMOS transistor and the PMOS transistor form a typical complementary MOS (CMOS)
device. When a low voltage (0 V) is applied at the input, the top transistor (P-type) is
conducting (switch closed) while the bottom transistor behaves like an open circuit.
Therefore, the supply voltage (5 V) appears at the output. Conversely, when a high voltage
(5 V) is applied at the input, the bottom transistor (N-type) is conducting (switch closed)
while the top transistor behaves like an open circuit. Hence, the output voltage is low (0 V).

CMOS NAND and NOR:

NAND and NOR gates are known as universal gates as any function can be
implemented with them.

NAND functionality can be implemented by parallel combination of PMOS and series

combination of NMOS transistor. When any one of the inputs is zero, then the output will be
one and when both the inputs are one the output will be low.

NOR functionality can be implemented by parallel combination of NMOS and series

combination of PMOS transistor. When any one of the inputs is one, then the output will be
one and when both the inputs are zero the output will be low.
ALGORITHM:

 Open the DSCH2

 Drag the components like pmos, nmos, voltage source, ground, and LED from
the symbol library.

 Connect the circuit as in the circuit diagram.

 Save the circuit & run the simulation

 Make verilog file go to Microwind and compile the verilog file saved in DSCH2

 Compile it and obtain the layourt diagram & draw the waveform

CIRCUIT DIAGRAM:
CMOS INVERTER

Verilog code:

module cmosInv( in2,out2)

input in2;
output out2;
pmos #(17) pmos(out2,vdd,in2); // 1.0u 0.12u
nmos #(114) nmos(out2,vss,in2); // 0.48u 0.12u
endmodule
CIRCUIT DIAGRAM:

NAND GATE:

Verilog code:

module cmosNand2( A,B,Nand2);

input A,B;
output Nand2;
nmos #(121) nmos(Nand2,w1,A); // 2.0u 0.25u
pmos #(121) pmos(Nand2,vdd,A); // 2.0u 0.25u
pmos #(121) pmos(Nand2,vdd,B); // 2.0u 0.25u
nmos #(107) nmos(w1,vss,B); // 2.0u 0.25u
endmodule

NOR GATE:

0
12u u
 Verilog code:

module nor2Cmos( B,A,Nor2);

input B,A;
output Nor2;
nmos #(121) nmos(Nor2,vss,A); // 1.0u 0.12upmos
#(121) pmos(Nor2,w4,B); // 2.0u 0.12u pmos
#(107) pmos(w4,vdd,A); // 2.0u 0.12u nmos #(121)
nmos(Nor2,vss,B); // 1.0u 0.12u endmodule

D FLIP FLOP:

RESULT:
Ex. No. 7 Postlab Questions Date:

1. Differentiate carry save adder and carry select adder.

2. Why is barrel shifter very useful in the designing of arithmetic circuits?
3. Interpret a partial product selection table using modified 3 bit booth’s recoding multiplication.
4. What is one time programmable memories?
5. Draw the structure of 6T SRAM cell.
6. Draw the 1bit binary shifter using MOS transistor.
7. State the need of sense amplifier in a memory cell.
8. Draw a single transistor DRAM cell.
9. Write the charge share equation for DRAM.
10. What is the significance of field programmable gate array?
Ex. No. 8 Prelab Questions Date:

1. Which type of device is FPGA?

2. Name the two types of routing in FPGA.
3. Difference between task and function in Verilog.
4. Define controllability and observability.
5. List the common techniques for ad hoc testing.
6. Compare serial and parallel scan in ad hoc testing
7. What are the limitations of IDDQ testing
8. What are the different phases of ASIC design flow?
9. What is the main advantage of ASIC Flow over FPGA-based design?
10. Define wafer.
 Exp. No.: 8
LAYOUT EXTRACTION AND
Date: SIMULATIONOF C-MOS
DIFFERENTIAL AMPLIFIER

AIM:

To design and simulate the CMOS differential amplifier circuit.

SOFTWARE USED

 Microwind
 DSCH

THEORY:

Differential amplifier:

Differential Amplifier amplifies the current with very little voltage gain. It consists of two
FETs connected so that the FET sources are connected together. The common source is
connected to a large voltage source through a large resistor Re, forming the "long tail" of the
name, the long tail providing an approximate constant current source. The higher the
resistance of the current source Re, the lower Ac is, and the better the CMRR. In more
sophisticated designs, a true (active) constant current source may be substituted for the long
tail. The output from a differential amplifier is itself often differential.

ALGORITHM:

 Open the DSCH2

 Drag the components like pmos, nmos, voltage source, ground, and LED from
thesymbol library.

 Connect the circuit as in the circuit diagram.

 Save the circuit & run the simulation

 Make verilog file go to Microwind and compile the verilog file saved in DSCH2

 Compile it and obtain the layourt diagram & draw the waveform
CIRCUIT DIAGRAM:

DIFFERENTIAL AMPLIFIER:

Verilog code:

module diff amp( );

nmos #(17) nmos(w2,vss,w1); // 1.0u 1u

pmos #(10) P2LargeL(w5,w3,w4); // 2.0u 0.12u

pmos #(24) P1LargeL(w4,w6,w4); // 2.0u 0.12u

nmos #(10) N2LargeL(w5,w2,w7); // 1.0u 1u

nmos #(24) N1LargeL(w4,w2,w8); // 1.0u 1u

endmodule

RESULT:
Ex. No. 8 Postlab Questions Date:

1. What is mean by a die?

2. What are the steps involved in manufacturing of IC?
3. What are the processes involved in photo lithography?
4. What is the purpose of masking in fabrication of IC?
5. What are the materials used for masking?
6. What are the types of Photo etching?
7. What is diffusion process?
8. Define the term SoC.
9. What is test bench in Verilog?
10. What is Net list?