Goal

• Build an architecture to support the

following instructions
w Arithmetic: add, sub, addi, slt
w Memory references: lw, sw
w Branches: j, beq
 Process

1) Design basic framework that is

needed by all instructions
2) Build a computer for each operation
individually
3) Add MUXs to choose between
different operations
4) Add control signals to control the
MUXs
 MIPS Steps

• Get an instruction from memory using the

Program Counter (PC)
• Read one or two registers each instruction
w One register: addi, lw
w Two registers: add, sub, slt, sw, beq
• All instructions use ALU after reading regs
• Some instructions also access Memory
• Write result to Register file
 Framework

Get
instruction
from
memory
 Framework

Get Read
instruction from
from register
memory file
 Framework

Get Read Use ALU

instruction from
from register
memory file
 Framework

Get Read Use ALU Access

instruction from memory
from register
memory file
 Framework

Get Read Use ALU Access

instruction from memory
from register
memory file

Write register file

Get Instruction

Where do we store
instructions?
 Get Instruction

Where do we store
instructions?
Memory

Address Data

Instruction
Memory
 Get Instruction

How do we know at
what address to
fetch instruction?

Address Data

Instruction
Memory
 Get Instruction

How do we know at
what address to
fetch instruction?
Program Counter

Program Counter Data

(PC)

Instruction
Memory
 Get Instruction

What do we end up
with?

Program Counter Data

(PC)

Instruction
Memory
 Get Instruction

What do we end up
with?
Instruction

Program Counter Instruction

(PC)

Instruction
Memory
What happens to the
PC each instruction? Get Instruction

Program Counter Instruction

(PC)

Instruction
Memory
What happens to the
PC each instruction? Get Instruction
Increment by 4B

Program Counter Instruction

(PC)

Instruction
Memory
 “Add” Instruction

Get Read Use ALU

instruction from
from register
memory file

Write register file

 “Add” Instruction
Operation rs rt rd shamt funct # meaning
add 3 5 2 0 32 # $2 <- $3 + $5

4
Read Use ALU
from
register
PC op/fun
Read Addr
file
rs
Out Data

Instruction rt
Memory Instrd
imm

Write register file

 “Add” Instruction
Operation rs rt rd shamt funct # meaning
add 3 5 2 0How many32 # $2 <- $3 + $5
registers do we
need to read?
4
Use ALU

PC op/fun
Read Addr
rs
Out Data

Instruction rt
Memory Instrd Register File
imm

Write register file

 “Add” Instruction
Operation rs rt rd shamt funct # meaning
add 3 5 2 0How many32 # $2 <- $3 + $5
registers do we
need to read?
4 2
Use ALU

PC op/fun
Read Addr
rs
Out Data

Instruction rt
Memory Instrd Register File
imm

Write register file

 “Add” Instruction
Operation rs rt rd shamt funct # meaning
What part of
add 3 5 2 0 instruction
32 # $2 <- $3 + $5
tells us the
register
number?
4
Use ALU

PC op/fun
Read Addr
src1 src1data
rs
Out Data

Instruction rt src2 src2data

Memory Instrd Register File
imm

Write register file

 “Add” Instruction
Operation rs rt rd shamt funct # meaning
What part of
add 3 5 2 0 instruction
32 # $2 <- $3 + $5
tells us the
register
number?
4 rs & rt
Use ALU

PC op/fun
Read Addr
src1 src1data
rs
Out Data

Instruction rt src2 src2data

Memory Instrd Register File
imm

Write register file

 “Add” Instruction
Operation rs rt rd shamt funct # meaning
add 3 5 2 0 32 # $2 <- $3 + $5

PC op/fun
Read Addr
src1 src1data
rs
Out Data

Instruction rt src2 src2data

Memory Instrd Register File
imm

Write register file

 “Add” Instruction

Operation rs rt rd shamt funct # meaning

add 3 5 2 0 32 # $2 <- $3 + $5
How do we
know which
4 register to
write?
src1 src1data
PC ReadOutAddr op/fun
Data
rs
src2 src2data
Instruction rt
Register File
Memory Instrd
imm
destdata
 “Add” Instruction

Operation rs rt rd shamt funct # meaning

add 3 5 2 0 32 # $2 <- $3 + $5

How do we
4 know which
register to
write?
op/fun src1 src1data
PC Read Addr rd
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
 “Add” Instruction

Operation rs rt rd shamt funct # meaning

add 3 5 2 0 32 # $2 <- $3 + $5

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
 What happens if instruction reads
and writes same register?

Operation rs rt rd shamt funct # meaning

add 3 5 3 0 32 # $3 <- $3 + $5

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
 What happens if instruction reads
and writes same register?

Operation rs rt rd shamt funct # meaning

add 3 5 3 0 32 # $3 <- $3 + $5
What would happen if we allowed write to occur at any time?
Clock is dependent on longest path (lw)
4 Quick operations may loop twice through machine, getting incorrect result.

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
 Reading/Write Registers

• When does register get written?

w At the end of the clock cycle
w Edge-triggered circuits
 “Addi” Instruction

Operation rs rt imm # meaning

addi $5,$3,6 3 5 6 What # $5 <- $3 + 6
registers do
we read?
4

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
 “Addi” Instruction

Operation rs rt imm # meaning

addi $5,$3,6 3 5 6 What # $5 <- $3 + 6
registers do
we read?
rs
4

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
 “Addi” Instruction

Operation rs rt imm # meaning

addi $5,$3,6 3 5 6 Where do # $5 <- $3 + 6
we get the
second
input?
4

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
 “Addi” Instruction
Operation rs rt imm # meaning
addi $5,$3,6 3 5 6 Where do we # $5 <- $3 + 6
get the
second
input?
4 imm (16 bits)

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

32 bits

16 bits
 Sign Extension

• How do we go from 16-bit number to

32-bit number?
• How about 4-bit to 8-bit.
w 0111 = 7 = 00000111
w 1110 = -2 = 11111110
• Take the top bit and copy it to all the
other bits
 “Addi” Instruction

Operation rs rt imm # meaning

addi $5,$3,6 3 5 6 Sign extend # $5 <- $3 + 6
immediate
value
4

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

16 Sign 32
Ext
 “Addi” Instruction
Operation rs rt imm # meaning
addi $5,$3,6 3 5 6 # $5 <- $3 + 6
How do we
know which
4
register to
write?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

16 Sign 32
Ext
 “Addi” Instruction
Operation rs rt imm # meaning
addi $5,$3,6 3 5 6 # $5 <- $3 + 6

How do we
4 know which
register to
write?
op/fun src1 src1data
PC Read Addr rt
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

16 Sign 32
Ext
 Putting them Together

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

16 Sign 32
Ext
 Putting them Together

Two wires to the

same input
4

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

16 Sign 32
Ext
 Putting them Together

Two wires to the

same input
Add MUXs
4

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

16 Sign 32
Ext
 Putting them Together
What
determines
which to take?

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

16 Sign 32
Ext
 Putting them Together
What
Control determines
Unit ALUOp which to take?
ALUSrc Op/Func code
4 RegDest

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

16 Sign 32
Ext
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
How many source regs?
4 What part of instruction?

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
How many source regs? 1
4 What part of instruction? rs

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Where do we get the second
input?
4

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Where do we get the second
input? Sign extended imm
4

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
What do we do with the ALU
4
output?

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
What do we do with the ALU
4
output? Memory Address

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]

Where do we
4 write the result?

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Load Operation
Operation rs rt imm # meaning
lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]

Where do we
4 write the result?
rt
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Store Operation
Operation rs rt imm # meaning
sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Store Operation
Operation rs rt imm # meaning
sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Address calculation
4
identical to load word

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Store Operation
Operation rs rt imm # meaning
sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5

Is $5 read or
4 written?
Which register?
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Store Operation
Operation rs rt imm # meaning
sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5

Is $5 read or
4 written? read
Which register?
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Store Operation
Operation rs rt imm # meaning
sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5

Is $5 read or
4 written? read
Which register? rt
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Store Operation
Operation rs rt imm # meaning
sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5

What do we do with
4 the value?

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Store Operation
Operation rs rt imm # meaning
sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5

What do we do with
4 the value?
In Data for memory
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Store Operation
Operation rs rt imm # meaning
sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5

What do we do
4 with OutData?
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Store Operation
Operation rs rt imm # meaning
sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5

What do we do
4 with OutData?
Nothing.
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Putting them together
Control
Unit

ALUOp
4

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Putting them together
What do we NOT
want it to do for a
Control store?
Unit

ALUOp
4

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Putting them together
What do we NOT
want it to do for a
store? Write to
Control destreg
Unit

ALUOp
4 RegWrite

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Putting them together
Do we want it to
read or write?

Control
Unit

ALUOp
4 RegWrite

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Do we want it to

Putting them together read or write?

Depends on
opcode
Control MemWr
Unit
MemRd
ALUOp
4 RegWrite

Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

What operation?
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

Zero?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

What operation?
Subtraction,
compared with 0
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

Zero?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
How do we go
anywhere?
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

Zero?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
How do we go
anywhere?
Change the PC
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

Zero?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
Where do we want
to go?
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

Zero?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
Where do we want
16 Sign 32 to go? Advance
Ext imm instructions
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

Zero?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
Where do we want
16 Sign 32 to go? Advance
But the PC is in Ext imm instructions
bytes.
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
Where do we want to
go? Advance imm
4 instructions
<<
2 Zero?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata

16 Sign 32
Ext

But the PC is in bytes.

PC = (PC + 4)+ Imm<<2
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

4
<<
2 Zero?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
How do we use our
16 32 Zero bit?
Sign
Ext
 “beq” Instruction
Operation rs rt imm # meaning
beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp

4
<<
2 Zero?
op/fun src1 src1data
PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata
How do we use our
16 32 Zero bit?
Sign
Ext Choose between
PC+4 and PC+4+
(Imm<<2)
 “j” Instruction
Operation Target address # meaning
j loop 0x0174837 # goto loop

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata Where do we go?
 “j” Instruction
Operation Target address # meaning
j loop 0x0174837 # goto loop

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata Where do we go?
To this absolute
address
 “j” Instruction
Operation Target address # meaning
j loop 0x0174837 # goto loop

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata Where do we go?
But this is only To this absolute
______ bits, when
the PC is _____ address
bits.
 “j” Instruction
Operation Target address # meaning
j loop 0x0174837 # goto loop

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata Where do we go?
To this absolute
But this is only 26 bits,
when the PC is 32 bits. address
 “j” Instruction
Operation Target address # meaning
j loop 0x0174837 # goto loop

op/fun src1 src1data

PC Read Addr
rs
Out Data

src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm
destdata Where do we go?
But this is only 26 bits, To this absolute
when the PC is 32 bits. address
Shift left, Concatenate
PC’s upper bits
 “j” Instruction
Operation Target address # meaning
j loop 0x0174837 # goto loop

4 bits
4
28 bits

op/fun << src1 src1data

PC Read Addr
rs
Out Data
2
src2 src2data
Instruction rt
Register File
Memory Instrd
destreg
imm 26 bits
destdata
But this is only 26 bits,
when the PC is 32 bits.
Shift left, Concatenate
current PC’s upper
bits
 The Whole Shebang

4 << <<
2 2
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Control Unit

• Set of control line values cause appropriate

actions to be taken at each step
• Finite state machine determines what needs
to be done at each step
w Fetch
w Decode
w Execute
w Memory ACTIONS
w Writeback DEPEND ON
OPCODE
 Single Cycle Latency

4 << <<
2 2
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
Time Diagram
 Cycle Time

• Not all instructions must go through

all steps
w add doesn’t need to go to memory
• Single long clock cycle makes add take
as long as load
• Can we change this?
w Break single instruction execution into
small execution steps
 Five Cycle Implementation

4 << <<
2 2
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext
 Five Cycle Implementation

4 << <<
2 2
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

FETCH 16 Sign 32
Ext
 Five Cycle Implementation

4 << <<
2 2
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext

DECODE
 Five Cycle Implementation

4 << <<
2 2
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext

EXECUTE
 Five Cycle Implementation

4 << <<
2 2
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext MEMORY
 Five Cycle Implementation

4 << <<
2 2
Addr
op/fun src1 src1data
PC Read Addr Out Data
rs
Out Data

src2 src2data
Instruction rt Data Memory
Register File
Memory Instrd
destreg
imm
destdata In Data

16 Sign 32
Ext

WRITEBACK
 How Many Cycles For:

• add
• sw
• lw
• blt
• j