';

I
_ a;Dtet
!

t0

Puipheral lntwfacing

T[," iOPBOGRAMMING
;''-= k-now
that binary information received from an external device is usually stored
rru-:: r: '-"':or later processing.
in
Information transferred from the central computer inio u,
,"b' :'= ::iginates in the memory unit. The CPU merely "*tu"rut
executes the I/O instructions and. may
rlirr:::: ie data temporarily, but the ultimate source or
destination is the memory unit. Data
r':;:';.:: between the central computer and I/O devices may be handled
in a varie"ty of modes.
: : ' -odes use the CPU as an intermed.iate path; others transfer the data directly to an from
ri: I - :ri:ror/ unit. Data transfer to
and from peripherals may be handled in one of three possible
: :.:.
- Programmed I/O
- Interrupt-initiated VO
l. Direct memory access (DMA)
Programmed UO Interrupt DMA IOp
Programmed I/O operations are theresult of I/O instructions
* written in the computer
'-:am' Each data item transfer is initiated by an instruction in the program. Usually, the
:-'----'fer is to and from a CPU register and peripheral.
other instructions are needed to transf'er
"r; jata to and from CPU and memory. Transferring data under prograrn control requires
:--'tant monitoring of the peripheral by the CPU. Once
a data transfer is initiated, the CpU is
-'-':ired to monitor the interface to see
when a transfer can again be made. It is up to the
-
' :rammed instructions executed in the CPU to keep close tabs on everything
that is taking
; .re in the interface unit and the I/O device.

10.3
 PERIPHERAL
10.4

IntheprogTammedliomethod,theCPUstaysinaprogramloopuntiltheVo,
indicates that it is ready for data transfer. This is a time-consuming process since it keep.
an interrupt facility and special comm
fro"".ro. busy needlessiy. It can be avoided by using signal when the data are available
io inform the interface io issue an interrupt' request
the device. In the meantime the cPU pro""ud to execute another prog:ram' The inte-:
"u.,
meanwhilekeepsmonitoringthedevice'Whentheinterfacedetermin"t,:11:11i^1.11':!.
to the computer' Upon detecting
ready for data transfer, it geierates an interrupt request
signal, the CPU momentariiy stops the task it is processing'
btul-"1:=-
external
utrLgl llal interrupt
urvvr r sl/v vtb^'$^,
returns to the task it was ongl
service program to process the I/O transfer, and then
performing.
peripheral' In direct
Transfer of data under programmed uo is between cPU and
access (DMA), the interface transfers data into and
out of the memory unit through the
bus. The cPU initiates the transfer by supplying the
interface with the starting address
then proceeds to execute other tasks' \\
the number ofwords needed to be transferred and
the memory bus' when
the transfer is made, the DMA requests memory cycles through
request is granted by the memorv controller, the DMA transfers,th:,11i? yT:Y]lX T::
memory Uo tran:
irr" Cpu ir"."ly deiays its memory access operation to allow the direct
I/o-memory transfers
since peripheral speed is usually slower than processor speed,
infrequent compared to processor access to memory'
Many computers combine the interface logic with the'":"i""f-u-i1:
t11iT:t:ff
pro""rro, (IoP). The IoP can handle many perip)
access into one unit and call it an Vo
the computer is divided into
through a DMA and interrupt facility. In such a system,
,"purlt" modules: the memory unit, the CPU, and the IOP'
Example of Programmed l/O
access to rnemorl-'
In the programmed I/o method, the I/o device does not have direct
of severai instructions by t;
transfer from an I/O device to memory requires the execution
ffiilffi;;f."I"r", instruction to transfer the data from the device to the CPU and
store instruction to transfer the data from the cPU to memory'
other isntructions may'
and to count the numbers of
needed to verify that the data are available from the device
transferred.
interface into the cPU
An example of data transfer from an vo device through an
one at a time as they are availab
shown in Fig. 10.1(o). The device transfers bytes of data
I/O bus and enables its data v
When a byte of data is available, the device flu."t it is the
enables the data accepted I
line. The interface accepts the byte into its iata register and
The interface sets u .u., ,ro* disable the data valid line, but
it will not transfer another
until the data accepted line is disabled by the interface'
A program is written for the computer to check the flag in the
status register to dete
is by reading the
ifa byte has been piaced in the dataregister by the VO device' This done
;"#;ffi " 6i,tl""ster and checking the value of the then flag bit. If the flag is equal to 1'
cleared to 0 by either the c
cPU reads the data from the data register. The flag bit is . r n - -- rL^ 11^-:^is clear
designed' Once the flag ^l^^.
or the interface, depending on how the interface circuits are
then transfer the next d
the interface disables thJdata accepted line and the device can
byte.
 PE RIPH EBAL INTER FACI NG
10.5

Data bus Interface VO bus

Data legister
Address bus
Data vald
CPU I/C)
VO read device
Status Data accepted
VO wriie regfister r'

F = Flag bit
Fig. 10.1(a) Data transfer f rom l/O device to Cpt-J.

lnterrupt-lnitiated l/O
An alternative to the CPU constantly monitoring the flag is to let the interface inform the
computer when it is ready to transfer data. This mode of transfer uses the interrupt facility.
While the CPU is running a program, it does not check the flag. However, when the flag is set,
the computer is momentarily interrupted from proceeding with the current program and is
l: tr]emo{, informed of the fact that the flag has been set. The CPU deviates from what it is doing to take
€riphera-: care of the input or output transfer. After the transfer is completed, the computer returns to
into thre= the previous program to continue what i{ was doing before the interrupt.
Vectored Interrupt: The CPU responds to the interrupt signal by storing the return
address from the progrtam counter into a memory stack and then control branches to a service
routine that processes the required I/O transfer. The way that the processor chooses the branch
nemory. A address of the service routine varies from one unit to another. In principle, there are two
ons by the methods for accomplishing this. One is called uectored, intercupt and the other, nonuectored,
IPU and a interrupt. In a nonvectored interrupt, the branch address is assigned to a fixed location in
ns may be memory. In a vectored interrupt, the source that interrupts supplies the branch information to
rs of words the computer. This information is called the interrupt uector.In some computers the interrupt
vector is the frrst address of the I/O service routine. In other computers the interrupt vector is
an address that points to a location in memory r,vhere the beginning address of the I/O service
he CPU is
available. routine is stored.
data valid
epted line. 10.1.1 lntroduction to DMA controller (SZS7 and 8237)
iother byte Direct memory access is an IIO technique commonly used for high-speed data tfansfer. In
microprocessor controlled data transfer, the speed of peripheral is less than or equal to the
determine speed ofmicroprocessor. Ifthe speed ofperipheral is greater than the speed ofmicrqprocessor,
J the status then the microprocessor is disconnected and DMA controller is used to transfer data. The DI\{A
al to 1, the controlled data transfer does not require software hence it is faster than microprocessor
:r the CPU controlled data transfer. This tcchnique used on any system that requires a high speed data
i is cleared, transfer rate. e.9,, C.R.T. systern, floppy disk drive system, hard disc derive system, High speed
r next data ADC etc.
In microprocessor based system data transfer can i.e., controlled by either softu,a:-e or
hardware. It uses program instructions to transfer data from I/O device to memorv or from
 PERIPHERAL INTERFA0ING
10.6
perform following
memory and vo device. To transfer data by this method microprocessor
operation.
1. Fetch the instruction form memory'
2. Decode the instruction.
3. Execute the instruction'
To perform these operations microprocessor requires consid'erable
time' so this method
such this data transfer from magnetic
of data transfer is not suitable for large data transfeis
disk or optical disk to memory. Above technique is known as
software controlled data
transfer,
External device gnerates
In other technique external device is used to control d.ata transfer.
and a11ows peripheral device to
address and control signats requited to control data transfer
direct memory access (DMA)
directly access the meriory. Hence this technique is referred to as
as DMA Controller Fig' 10' 1(b )'
and externai device which controls the data transfer refred to

a-, a*
MEMR, MEMW
HOLD

Fig. 10,1(b)

10.1.2 DMA 0perates in two Operating Cycle

(1) DMA Idle Cycle. when the system is turned on, the switches are on the X position'
memory and peripherals'
so the buses are connlcted from the microprocessor to the system
of data from the disk'
Microprocessor then executes the program until it needs to read a block
of commands to the disk
To read a block of data from the disk microprocessor sends a series
the disk' When disk
controller device felling it to search and read to desired block of data from
request DRQ signal to
controller is ready to transfer first b;'te of data from disk, it sends DMA
signal by floceting
the DMA controller. Then DMA controller sends a hold request this HOLD
controller' when the
its buses and sending out a HLDA (hold acknowledge) signal to the DMA
switch position
DMA controller receives the I{LDA signal, it sends a control signal to change
forrn X to Y.
(2) DMA Active Cycle. When DMA controller gets control of the buses, it sends the
rnemory address where the Ist byte of data from the disk is to be written'
It also sends a DMA
it get ready for data transfer'
acknowle6ge, DACK signal to thl disk controller device telling
to
 6' ri ;- ::;, INTERFACING 10.7

ffi::.i ,trncaseofDMAwriteoperation),itassertsboththe IOR and MEMW signalsonthe

.nr the IOR signal enables the disk controller to output the bl'te of data
"1 - . - : us. Asserting
y. :- -.:,: disk on the data bus and asserting the tttEiltW signals enables the addressed memory
r, . .::: data from the data bus. In this technique data is transferred directly form the disk
11 :
-- -er to the memory location without passing through the CPU or the DMA controller.
--"1en
the data transfer is complete the DMA controller unasserts the HOLD request
,i -1 :- i -, the microprocessor and release the bus by changing switch form Y to X. After getting
1: -.:rol of ali buses the microprocessor executes the remaining program.
-1 ' DMA Transfer Modes
3
The DMA controller functions as a bus master and bus sleve. It performs only data
;*.,: .:=r operations. It does not process data. DMA controlled input output is further divided
: :'i following categeries :
- Burst or Block transfer DMA.
- Cycle steal or single byte transfer DMA.
r Transparent or Hidden DMA.
lne 8257 offers three different modes of operation:
1) DMA. Read. \{hich causes data to be transferred form a memory to peripheral.
Z) DMA l4rrite. This causes data to be transferred from a peripheral to memory.
B) Dl\{-A. Verify, Which does not actuaily involve the transfer of data. When an
r
- is i1 $1\{A verify mode no memory or I/O read/write control signal will be
- I channel
*,-.:dr€d. Thus pre.ienting the transfer of data the 8257 however, will gain control of the
' ,-.:n bit.
Ihe 825? i,;:g2nluurton:
The 825? organisation is divided in two sections:
1) Pin description Le. external organisation.,
I 2) Block diagram i.e. internal organization.

": 2 BURST OR BLOCK TRANSFER DMA

It is the faster DMA mode. In this mode, two or more data bytes are transferred
: -:rnuously. The microprocessor is disconnected from the system bus during DMA transfer
, . the micyoprocessor iannot executed is own program during this transfer' N number of
where N is number of
- l.'\ cycles are added into the machine cycles of the microprocessor
: --.s to be transferred, as shown in Fig. 10,2, her"" the instruction execution speed of the
-_-rroprocessor is reduced.
(lnstruction Cycle)

M1 DMA DMA DMA M2

cycle 1 cycle 2 cycle N
Fig.10.2.
The sequence of events that take place is shown by flowchart Fig. 10.2' In this mode, the
IIJIA controller sends 'HOLD' signal to the microprocessor and waits for HLDA signal. After
::ceiving HLDA signal, the DMA controller gains control of the system bus and executes a
10.8 PERIPHERAL

DMA cycle to transfer one byte. After transferring one byte it increments address register
decrements byte count register and transfer next byte. In this way, it transfers all data b;
between memory and input/output devices. After transferring all data bytes, the DMA contr,-,
disables 'HOLD' signal and enters into slave mode.

Enable DMA channel

Send "Hold" signal

to microprocessor

Transfer a byte trom

memory to l/O or l/O to

Decrement count register

Disable hold signal and enter

into slave mode

Flowchart: Burst Mode DMA

10.2.1 Gycle Steal or Single Byte Transfer DMA

In cycle steal transfcr only one byte of data is transferred at a time. After transferring one
byte, the DMA controller disables HOLD signal and reactivates this signal only when the nex:
byte actually needs to be transferred i.e., the DMA controller gives control of the bus back tr
the microprocessor in between successive byte transfer. This type of DNIA is slower than burs'i
 P ERI PH ERAL INT ER FACING
10.9

DliA. In this mode only one DMA cycle is added between two machine cycles ofof the
the
microprocessor as shown in Fig. 10.3, hence the instruction execution speed
microprocessor is reduced slightly.
(lnslructlon CYcles)

*
Ml Mz M3 Mp
DMA
DMA DMA DMA
cycle "1 cycle 2 cycle 3 Fi9.10.3.
cycle N

The sequence of events that take place is shown by flowchart of Fig. 10.4.

lnitiate DMA controller

Check HLDA input

Transler a byte from

memory to l/O or l/O lo memorY

Disable hold signal &

enter into slave mode

lncrement address register

Decrement count register

ransferring one
; \.,'hen the next
the bus back to
lr,,'er than burst Fig. 10.4. Flowchaft for cycle steel DMA.
10.10 PERIPH ERAI- INTERFAC', :

In this mocie the DMA controller sends 'HOLD' signal to the microprocessor and waits :-:
HLDA signal. After receiving HLDA signal, ihe DMA controller gains control of the system b.-
and execuies only one DMA cycle. After transferring one byte, it disables 'HOLD' signal a::
enters into slave mode. The microprocessor then gains control of the sysiem bus and execur.:
next machine cycle. If the count is not zero and next data is available then the DMA controil=:
sends 'HOLD' signal to the microprocessor and transfers next byte of data block.

10.2.2 Transparent or Hidden DMA Transfer

The microprocessor executes some states during which it floats the address and da:;
busses. e.9.,T4, T5 and T6 of 8085 opcode fetch cycle. During these states, the microprocess.:
is isolated form the system bus. The DMA controller transfers data between memory a,n:
inpui/output devices during these states. This operation is transparent to microprocessor. Th=
8085 microprocessor executes idle machine cycle for some instructions (DAD Rp). During th:-.
cycle, the DMA controller can transfer data. This is the slowest DMA transfer. In this mode.
the instruction execution speed of microprocessor is not reduced. But, the transparent DlLi
requires logic the states when the microprocessor is floating the buses.
The DMA controller contains four types ofregisters viz. address, count, control and statu=
register. The address regiaster is used to hold the starting address of rnemnry. The coun:
register indicates number ofbytes to be transferred. Control register is used to set operating
modes of the DMA controller and status register provides states of DX{A cycle.

10.3 PROGRAMMABTE DMA CONTROLTER 8257

General Features :
1. It is a 4 channel DMA (Direct memory access), Controller i.e., 4 peripheral input
output devices can be interfaced to 8257 . Each channel is individually programmable.
2. It is compatible with Intel microprocessors.
3. Each channel of 8257 provides a 16 bit address register and a 14 bit counter, hence
each channel can transfer 16 K bytes without microprocessors intervention.
4. It provides on chip priority resolver that resolves priority of channel in fixed or rotating
priority mode.
5. It provides on chip channel inhibit logic.
6. It generates a TC signal to indicate the peripheral that the prograrnmed numbers of
data bytes have been transferred.
7. It generates a MARK signal to indicate the peripheral that 128 data bytes have becn
transferred.
8. It requires single phase TTL clock. (Qr).
9. The maximum frequency is 3 NIHz and rninimum frequency is 250 kHz.
10. It can be used in block and cycle steal transfers.
11. In response to peripheral DMA request, the 8257 activates HOLD input of the CPU,
which then relinquishes hold on the buses. It gains control of the systern bus and
resolr'es the propriety of channel, and executes appropriate DMA cycle {br highest
propriety requesting channel.
IERAL INTERFACINC
::]|PHERAL INTERFACING
tl.il
i l anci waits fo: 72. I't executes three DMA cycies:
::he system br,--
li D' signal ani U) DN,IA read,
(ii) DN{A w.rite,
-:. rtod executes
DJI-{ controller (rrl) DMA verify.
i:,. 13. It can bc operated in auto loacl mocle.
74' rt provides AEN signal that can be used to isolate
system bus.
cpu arid +thcr.devices from thc
::'tss and data 15' The external device can terminate DNIA operation.
:licroprocessor lionnr.ily the D1,IA controller
operates in two modes viz.: (il slave mocle,
:_ lnemory and
ilj) master niarle.
- ::rrCeSSOr. ThC : In rnicrocomputer,
- 'rcroprocessor
the system bus is controlleci by onlv one bus rnaster
and DNIA controller canrot control the systein ai a time, 1.e.,
l: During this bus simultarr"or.io
' ^r this mode, 10.3.1 Comparison between Slave and Master
Mode
:,:i-rarent DMA
Slaue Mode
(Nornt.al ntode of the systent) Master lllode
::,,t1 andstatus (DMAmode of tIrc qtstent)
.:". . The count 1. In this mode microporcessor functions 1. In this mode the DNIA controller functions as a
, .r.t operating as a bus master and DMA controller
bus master but the microprocessor is disconnected
iunctions as a bus slave Le., the system
from the system bus 1.e., the system bus is controlled
bus is controlled by microprocessor.
by DMA controller.
2. Tire data is transferred throgh micro_ 2. The data is not transferred through mict oprocessor
processor, irence has to perform and
as well as DMA controller 1.e., the data is transferred
least two operations to transfer. one
between I/O device and memory directly. Hence
:11-reral input byte between I/O device and a memory.
the DMA controller performs only one ope"ration
As a result transfer rate is reduced. to
r. lrrammable. transfer one byte between I/O device anju *"rrory.
As a result the transfer rate is increased.
, ,iilter, hence The microprocessor executes the 3. The DMA controiler executes the following
following:
:-:t !n. DMA cycle :
Machine cycles (l) DMA read,
:.:l or lotating (i ) Opcodc fetch, rij)
Operand Fetch, (ll) DMAwrite,
(rli) Memory read, 0u) Nlemory write, )

(lll) DMAverify.
(u) I/O read, (ui\ t/O
write, rui I ) Interrupt
r Lumbers of acknowledge, (ulil) Jdle.

4. The microprocessor has to execute

:-'s have been
at The D1VIA controller execute only one DMA cycle
Ieast 6 machine cycles to transfer one
to transfer one b;te between I/O device andmemorv.
byte between I/O devices and memory.
'Ihe microprocessor, DMA controiler,
The DMA controller, memory and DMA I/O
mernory, DMA and non-DMA I/O devices devices
are connected to the system bus.
are connected to the system bus.

,,i'the CPU, The microprocessor executes T states

6. The DMA controller executes S states where,
.:m bus and where,
:br liighest rn_
CPU clock frequency DN{A clock frequency
 mfl liririrlliriililhs-.:F{
PERIP H ER A L INT EB FAC I'" 3
1Ai2

Slaue Mode MasterMode

(Nonnal mode of the sYsten) (DMAmode of the system)

7. The rnj:croplocessor performs arithmetii, The DMA controller performs oniy data transfe:
logical data transfer and decision operation, hence data cannot be processed.
making opelations, hence data can be
processed.
8. A11 address and control signals are All address and controi signals are generated
generated by microProcessor. DN'IA controller.

9. Data lines of8257 are connected to the Data lines of 8257 are connected to the higher
systern data lines' system address lines.
10. The intialization of DMA controller, The DMA controller cannot intialize devices.
DMA and non-DMA I/O devices is done
by microprocessor.
11. TC, AEN, ADSTB, MARK etc. signals TC, AEN, ADSTB, MAIIK, etc. signals are
cannot be activated. activated.
12. The microprocessor provides instructio The DMA controller does not provide
set. set.

10.4 8257 PIN CESCBIPTIoN

The pin diagram of 8257 is as shown in Fig. 10.5.
I Input
=
O = Output
I/O = InpuVOutput

Pin Direction
Dr-Do vo Databus (8 bits bidirectional)
IOR ao I/O read bidirectional

IOW vo Write bidirectional

MEMR o Memory read
NIEMW o Memory write
Ao-A, vo Address bus bidirectional
An-A, o Address bus : r'Tlli

CLK I Clockinput
Reset I Reset input
Rcady I Readyinput
HRQ o HOLD request (to 8085)
I_ILDA I HoId acknowiedge (From 8085)
AEN o Address enable
(contd...)
 :: 2 IP H ERAL INTER FACING 10.13

ADSTB o Address strobe

TC o Terminal count
MARK o Modulo 128 mark
DRQ0 - DRQs I DMA request input
DACK0-DACrq o MA acknowledge output
CS I Chip select
vcc I +5 volts input
v.. I 0 volts ground reference

+->ffi 140 A7--|

+>tow -39
2
Ao---->
<-MEMR 3 As------->
3B
<-MEMW 437 A+------->
<-MARK 536 A6----->
I
L

I
I
-_}READY 635 A3<+
734 A2<-.-..-r.
-}HLDA
<-ADSTB 833 A1€
<-AEN 932 46€
<-HRO .10 8257 31 VCC<-
-----|cE 11 30 DO+
12 29 D1 e
->CLK
-----|Reset 13 28 D2e
+-D7ffi2 14 27 D3e
+-DAeks '15 26 Da€
--_)DHe3 16 25 onCK-o->
*+DRQ2 17 24 6lffir+
18 23 Dse
->DRQ1
---+DRe6 19 22 D6e
*\/-^'5t 20 21 D76
Fi9.10.5.

Symbol Description
Do'Dr: These are bidirectional tristate, buffered, multiplexes data (Do -
Dr)/address (As - A15) lines. In salve mode, these line function as
bi-directional data lines. In this mode, data lines are used to transfer
information (Address, count value, corltrol world and status word)
between microprocessor and 8257's registers. In master mode,
these lines function as address output lines (A. - Aru). 8257 places
tntd...) co ttt d
10.14 P E R I P H ER A L I NT E B FAC I,\..

higher byte of memory address on rhese lines. These lines shou__

be connected to higher address lines of system address bus '-
master mode.
ron , It is an active low, tristate, buffered, bidirectional control line. l:
slave mode, f'unctions as an input line. In this mode, IOR sign.
is generated by microprocessor to read contents of8257 register=
In master mode, it f'unctions as an output line. In tli is ;uode iOF.
signal is generated by 8257 during DMA rvrite cycle.
fOW t It is an active low tristate, buffered, bidirectionai control line. I*
slave mode functions as an input line. In this mode, IOW sign;-
is generated by microprocessor to write data in to 8257 register=
In mastcr rnode, it functions as an output line. In this mode IOW
is generated by 8257 during DN{A read cycle.
CLK: It is a clock input line. It is connected to single phase, SAVo dut;;
cycle, external TTL clock generator. This signal ignored in slave
mode.
Reset: It is a reset input line. It is connected to RESET OUT pin of B08r
microprocessor. This signal clears mode set register and status
register, and forces 8257 into slave mode.
Ao-Ar: These are tristate, buffered bidirectional address lines. In the slave
mode, these lines are used as address input and are internalll-
decoded to access one of the registers. In master mode, these lines
function as address outpu! lines. The 8257 places Ao - A, bits of
memory address on these lines.
CSt It is an active low, chip select input line. In salve mode, this signai
is generated by address decoder to select the 8257 chip. This signal
is ignored in master mode.
An - Ar: These are tristate buffered, address output lines. These lines are
tristated in salve output mode. In the master mode, the 8257 places
A4 - A7 bits of memory address on these lines.
Ready: It is an asynchronous input line. This signal is generated by slou,
devices to delay DMA cycle in master mode. The 8257 samples its
ready input during S.r. When it find READY low, it adds a wait
state between S, and So. In slave mode, the 8257 ignores this signal.
HRQ: It is a hold request output line. It is connected to the HOLD input
of the microprocessor.
IILDA: It is a HOLD acknow-ledge input line. It is connected to the HLDA
output of the microprocessor. In response to this signal, the 8257
gains control ofthe system bus.
MEMR : It is an active low, tristate buffered control, output line. It is
tristated in slave mode. In master mode, this signal is activated
during DMA read cycle.
(contcl...)
 , ER IPH ERAL INTEB FACING 10.15

MEMW : It is an active low, trisrtaie, buffered control, output line. It ir;

tristated in siave mode. In master mode, this signal is activated
during Dl{A write cycle.
,\EN (Address It is a controi output line. This signal goes 1ow in slave mode and
enable): high in master mode. It is used to :
1. Isolate CPU address, data and control iines from the system
address, data and control lines respectively.
2. Isolate non-DMA I/O devices from the system bus.
3. Discori-nEct data lines of 8257 from the systerrr data bus
and connect these lies to the high order system address lines
(A8_A15).
4. Isolate DMA input/output devices from the system address
bus (because the 8257 does not generate inpuUoutput address)
ADSTB It is a control output line. It is similar to ALE of an 8085
(Address strobe) : microprocessor. This pulse is activated in rnaster mode oniy.
It is used to latch higher byLe of memory acldress (which is placed
on data lines).
TC It is a status output line. It is activated in master
(Terminal count) : mode only. The high level on'this line indicates the selected
peripheral that the present DMA cycle is the last c;ucle for block
transfer. This signal is activated when the contents of TC register
ofthe selected channel are equal ta zera. It is also used to interrupt
the rnicroprocessor and to disable the requesting input/output
device.
MARK: It is a modulo 128 MARK output line. It is activated in master
mode only. It transferring every 128 bytes of data
goes high after
block. It the length ofblock is iess than 128 then this signal is not
activated.
oRQo - pRQs These are synchronous DNIA request input lines. These signals
. - t-^
i:11: (DMA request) : are generated, by peripherals. In fixed propriety mode, DRQO has
., :it
highest priority while DRQS has lowest priority.
:gral.
DACK0 - DACKs These are active low DMA acknowledge output lines. The low
---JUL
(DMA ackuowledge) : level this line informs the peripheral connected to that channel
that, it has been selected for a DMA cycle. This pulse is actuated
:- DA during DMA cycle, i.e., this signal can be used to count the number
of DMA cycles, it is also used as a chip select input for a DMA
input/output device in master mode.
- lc
'at ed

:::...1
 PER I PH ER AL INT EB FACIN G
10.16

10.5 8257 BLOCK DIAGRAM

The block diagram of 8257 is as shown in Fig. 10.6. It contains following blocks :

INTERNAL BUS

DRQo
Ds-Dz
orcro

ron.
iOW. DRQl
CLK
HE SET -) 6;6r"1
Ao #
A1
s
Ar s
A3 +

A4
A5
4.,
A7
READY DRQ3
HRO
HLDA, DACR3
Llelvr n
ME[,1IV
AEI\
ADSTB
TC
IIAFK

Fig. 10.6. 8257 Function block diagram.

(1) Data bus buffer
(2) Read/write control logic
(3) Control logic block
(4) Priority resolver
(5) DMA channels.
(1) Data Bus Buffer. It contains tristate, bidirectional 8 bit buffer. In slave mode, it
transfers data between microprocessor and internal bus. The direction of data bus buffer is set
by read/write control logic. In master mode, it outputs A, - Aru bits of memory address on data
lines. In this mode the direction of data bus buffer is fixed.
(2) Read/Write Control Logic. In slave mode; it accepts address bits and controls signals
frorn the microprocessor. It master mode, it generated address bits and control signals. It
controls all internal read/write operations. It contains F/L flip-flop
(3) Control Logic Block. It contains control logic, mode set register and status
register. Control logic control the sequence of DMA operations during all DMA cycles in master
mode. It generates address and control signals. It increments 16 bit address and decrements 14
bit count register. It activates a HRQ sigaal on channel DMA request. It is disabled in slave
mode.
 ). BIP H ERAL INT ER FAC I NG 10.17

(o) Mode Set Register. It is a utrite only register. It is used to set oper(tting nodes of
-;257. This register must be programmed ai'ter initialization of required DMA channeis.
The
:ddress of this register is (As Az Ar Ao = 1000). The format of mode set register is shown in
: ig. 10.7.

AL TCS EW RP ENs ENz ENr ENo

'i
vl
D ioJd
= Auto io rnode I
'1
= Enable DlvlA CH-O
(

0 * Ho'taiin inoflty
''l:lnJ Dll,'1A Ch-0
0 = Disable Dl"1A
I

I
1; afler
1 = Stop a1 TC # 1 = Enablc Dl'lA
Dl'']A CH-l
;a5le channel aiter TC)
(DisaSl Disaolc DL4A dH'1
0 = Disatlc
3nnel is enabled after TC
0 = Chann
ended write mode
1 = Extend
rmal
0 = Norma mode {- 1 = Enable DiUA
Dir{A CH-2
D[4A CH-2
0 = Disable Dlr4A

:ating pri1]rlty
1 = Rotat
:d priority 1 = Enable DMA
DMA CH-3
0 = Fixed
0 = Disable Dl"/A CH-3

Fig. 10.7. Mode set register.

(b) Status Register. It is a reed. only register. It prouides the status of DMA charunels.
The format of status register is as show-n in Fig. 10.8. The TC status bits are set when the TC
signal is activated for that channel TC status bits remains set until the status register is ready
rrr the 82b7 is reset. Update flag is not affected by a status read operation. The UP bit is set
during update cycle. It is clearecl automatically after completion of update cyc1e. This flag is set
in auto load node only. The address of status reg:ister is (A, A, Ar Ao = 1000).
D7 D6 D5 D,1 D3 D" D1 D6

0 0 0 UP rc: I rc, TCr TCo

1 =TC activated CH-0

0= =TTC nct activated CH-O
1l=l= TC activateC CH-l
n
0 -T= TC not activaled CH-1
1l=l= TC activated CH-2
Update Fiag
0=T
0 = TC nol activated CH-2

1 = 8?57 exer;LttirtQ
it cvcie
I

le. urrdate I

-: .\cL
O=A'2s2"ro.r,.,, 1l , 1t''rC
='fC activaled ft)r CH-3
DlvlA cycle 0=TC not activated for CH-3
data
F!9. 10.8. Status register.
nals (c) F/L Flip-Flop (First/Last FliplF'lop). Thc rvord leng$h of 8257 is 8 bits, hence it
.-q. It can accept or gcnerate B bit data simultaneously. But the address and count registers are 16
bit. The microprocessor cannot access a 16 bit register simultaneously. A0 - A, address lines
atus are used to distinguish between 16 bit registers, but they are not used to distinguish betu'een
IStEI lower and higher by'tes of the 16 bit registers. The 8257 provides on clip F/1, flip-flop to distinguish
IS 14 signal. It also gets reset rvhenever the rnode set register is loaded. Hence the initialization
ilave prograrn can begin w,ith loading a "durnmy" (00H0 in mode set reg"ister. To access lorver blte of
a 16 bit register, the F/L flip-flop shoulci be reset and for higher byte of a 16 bit register the F/
 10.18 PERI PH ERAL INTER FAC I :,.

L fiip-flop should be set. This flip-flop is togglecl af'ter each CH register access. The interrup:
must be disatrled before accessing 16 bit register.
The selection of registers is shown in tabie below :

A$ A2 A1 Ao FIL Register
0 0 0 0 0 LSB CH-0 Address register
0 0 0 0 1 MSB CH-0 Address register
0 0 0 1 0 LSB CH-O Terminal count register
0 0 0 1 1 X,[SB CH-O Termina] count register

0 0 1 0 0 LSB CH-1 Address register

ft 0 1 0 1 MSB CH-1 Address register
0 0 1 1 0 LSB CH-1 'Ierminal count register
0 1 1 1 MSB CH-1 Terminal count register

t) 1 0 0 0 LSB CH-2 Address register

0 1 0 0 1 MSB CH-2 Address r"egister ri:
0 1 0 1 0 LSB CH-2 Terrninal count register
n 0
1 1 1 MSB CH-2 Terr::inai count register

0 1 1 0 0 LSB CH-S Address register

0 1 1 0 0 MSB CH-8 Address register
0 1 1 1
0 LSB CH-S Terminal count register
0 I
1 1 1 XlSts CH-S Terminal count rcgister
1 0 0 0 0 Mode set register (write only)
l 0 0 0 0 Status register (read only)

i4) Priority Resolver. It contains priority resoiving logic circuit the resolves the priority
af each cirannel. It can be initialized either in rotating or fixecl priority rnode.
{5i DMA Channel. 8257 provides four separate channels. Each channel contains two 16
l:it regJistcr viz. (1) 16 bit address register (2) 16 bit count register.
(a) 16 Bit Address Register. It is a 16 bit register. It is used to hold the starting
address of rnemory. This register is incremented after each DMA cycle. If the adclress register
is read in the middle of a DMA operation, it provides the adclress of next memorv location. The
format of address register is as shown in Fig. 10.9.

Ais At+ Ar: Ara Arr Ato A9 A8 /\l ,A^

'lJ A5 A. A3 A2 A1 Ao

l{-*.-"_--_'- FiL = 1------4l{-.-"_ FiL = 0 --'-+

Fig. 10.9. Address Register
(b)
16 Bit TC Register. It is divided into two frelds. 14 bit counts an cycle control bits.
TC6 - TC13 bits indicate number of bytes to be transferred minus 1 and this value should
-
be N 1. The actual 14 bit count value is decremented after each DMA cycle RD and WR
bits
 P ERIPH ERAL INT ER FAC ING 10.19

rndicate type of DMA cycle or direction of data transfer. The format of TC register is as Sho\!rr
in Fig. 10.10.
i<- ril = 0 _._ !i
TCr2ircrl lTCloi rce
Binary code o{ N-1 where N is number of bytes to be transferred

RD WR DMA cycle {l,O mappedr,Ol DlvlA cycle (memory mappeci llOl

0 0 Dir,4A veriiy cycle DMA verify cycle

0 1 DMA write cvcle DMA read cycle

1 0 DfvlA read cycle Dl",lA wr,te cycle

1 1 lllegal lllegal

Fig. 10.10. TC Register.

10.6 OPERATING MODES OF 8257

The 8257 priority mode :
(1) Rotating Priority Mode. if the RP bit of mode set register is set then lb.e 8257
operates in rotating priority mode. After each DMA cycle, the priority of each channel changes.
Hence, all channels will get equal opportunitv if they are enabled changes.
Initially CH-0 gains highest priority while CH-3 gains lowest priority. The channel which
has just been serviced will get the lowest priority after the DMA cycle and other channels move
up to the next higher priority levels. The rotating pattern of channels is as shorvn in Fig. 10.11.

Fig.10.11.
(2) Fixed Priority Mode. If the RP bit of mode set register is reset then 8257 operates
in fixed priority mode. In fixed priority mode, channel 0 has highest priority and channel 3 has
lowest priority. The propriety is resolved during 54 of each DMA cycle.
(3) Extend Write Mode. If the EW bit of rnode set register is set then 8257 generates
advanced or extencled writc control signais (IOW and MEMW), 1.e., MEMW or IOW will go low
one clock cycle earlier as shown in Fig. 10.12. This mode is used to interface slower device to
systen\. If the memory devices or VC) device connected is slightly slower, then for synchronization
it used READY signal. In this method the write signal is delayed by adding rvait states into a
DMA cycle. This reduces tire speed of transfer'. But in extended write mode, the writ signal is
- lits. extended earlier r,vithout adding states, 1.e., the set up time of write input signal of an input/
output device or rnemory is increased in extended lvrite mode rvithout reducing the speed of
.-ould
transfer. Thus sigaal allou, more time to external logic for deciding if additional rvait states are
?, bits
needed. Microcomputer systems may use lnelnory and input/output devices of difl'erent speeds.
10.20 PERIPHERAL INTERFA: ,:
.lf,] :

Ii'the wait state generator is common fbr aii devices, then it wili introduce wait states --:
DMA cycles of the speed cornpatible devices, because the wait generator decides whether to a: :
rvait state or not, at the falling edge of IOW or NItrMW signal. Hence, extended write mode r- _'..
be used for speed compatibie devices if the wit state generator is common. If the wait s:.:.,
generator is uot used, then extended write morie can be used to access slorn, devices, but :: :
speed of the slow device should be less than, {'s =? where, fs is the speed of cornpatible der':-.
Normal

low

Exterided
low
Fig.10.12.
(4) TC STOP Mode. If the TC stop bit mode set register is set, then 8257 disables t:-.
channel whose TC is reached. In this case, channel is disabled by 8257 itself. If the TC stop t-.
of mode set register is reset, then the corresponding channel must be disabled by t::
rnicrocomputer systern through software. The channel should not be left enabled after termin;
count, in any case. The TC stop bit option should be common for all channels.
(5) Auto Load Mode. If AL bit of mode set register is then the 8257 operates in autoloa:
mode. In this mode the data is transferred by channel 2 only, i.e., other channels are not use:
for data transfer. If the AL bit is set, then the 8257 can be used for repeat block or blocr
chaining operations.
(i) Repeat Bloch Operatiort. If the AL bit is set, the paramcters (memory address an:
terminal count) of CH-2 and TC are cluplicated into CH-3 register it CI{-2 is programmed. I-
this mode, ENS and TC bits are irrelevant. The new parameters are not written into the CH-:
registers. The CH-2 transfers first DMA block between memory and input/output device. After
transferring first DMA block, the 8257 executes an between memory and input/output device
After transferring first DMA block, tbe 8257 executes an 'update cycle'. During this cycle ir
transfers contents ofCII-3 register into CH-2 register and sets update flag in statue register.
After completion of an update cycle, CH-2 transfers two or more,
(ii) Bloclt Clruining Operatiort. In this operation CH-2 transfers two or more different
data blocks. CH-3 must be loaded with different parameters a{'ter initialization of CH-2 registers.
In tiris mode both the channels have to be enabled. The TC stop bit is irrelevant. The autoloaci
timing diagram is shown Fig. 10.13.
Blockt Block2 Block3
Parameter Parameler CH2 update Parameter CH2 update
occurs here occlrrs here
liO Wrile

nro.X3 Oft,4n

Update
flag

Fig. 10.13. Autcload timing.

 PERIPH ER A L INTER FAC I NG 10.21

Initially CH-2 and CH-S register are lnitialized with Btock 1 and Block 2 pararneters
respectively. Thel, CH-2 transfers data block, between memory and inpuUoutput device.
During
last DNIA cycle it activates TC signal and sets the update flag. The 8257 executes an update
cycle. During this cycle it transfers contents of CH-3 registers into CH-2 registers.
But CH-2
,Lgirt"r, are updated at the end of update cyc1e. To terminate the update cycle, at ieast one
DMA cycle must be executecl. This DMA cycle will be the first DMA cycle of next data block.
The update flag is cleared at the end of frrst DMA cycle of next data block. The microprocessor
w.rites new parameters (block parameter) into CH-3 registers.
(Note that the DRQ2 signal
should be disabled during initialization of CH-3 registers). The CH-2 then transfers second byte
of noxt data block. In this way, CH-2 transfers tow or more data blocks' The TC signal can be
used to interrupt the nicroprocessor.

10.7 8237 HIGH PERFOBMANCE PROGRAMMABTE DMA CONTROLLER

Before starting of 8237 take overview of 8257'
Note:
General Features
(1) Multimode DMA Controller : It provides various modes of DMA.
(2) Four Independent DMA Channels : It provides on chip ftrur independent DMA
channels. The number of channels can be increased by cascading DMA controller chips. Each
channel can transfer 6 bYtes.
(B) Independent Auto Initialization of all Channels : Each channel can be used in
3:S anc
c-ed, hr auto initiali zationmode. In 8257 only channel 2 can be used in autoload mode'
:e CH-3 (4) Memory to Memory Transf'er : It can transfer data between trvo mernory blocks in
e. After DMA mode.
ievice. (b)Memory Block Initialization : In rnemory to rnemory transfer a single rn'ord can bc
.-1-cie it written into all location of memory block'
'egtster.
(6) Address Increment or Decrement: The address of memory is either Incremented
Lltferent
or Decremented after each DMA cycle depending upon the mode'
i 3.1SteIS. (7) The clock frequency is 3 MHz (8237) or 5 MHz (8237-2)'
rutoload (8) High Performance : The data transfer rate is very high, e.g., 1.6 M bytes/second for
8237-2 of 5 MFI;r. The minimum length of DMA cycle is 25'
(g) Direcgy Dxpandable to Any Number of Channels : It doesn't require any additional
chip for cascading. There is no iimitations on cascading'
(10) End of Process for Terminating Transfer : It provides EOP line that is used to
terminate DMA operation. This signal is generated by external hardware.
(11) Software DMA: The DMA can be requested by setting an appropriate bit of request
register.
(12) Independent control for DREQ and DACK signal. DREQ and DACK signal can be
initialized wither of active high or active low.
(18) Compressed Timing : It provides compressed timings to improve throughput of'
the system. It can colnpress the transfer time to two cycles (2S)'