Introduction to Xilinx Vivado

To study the Xilinx tool

Equipment Required:
Xilinx Vivado 2018.1 software tool
Personal computer
Procedure:
1. To Create a Project: Open Xilinx Vivado 2018.1 software and create new project from the file
menu, select RTL Project, then at default Xilinx part or board, select family as Artix-7, Package as
csg324, speed as -1, and then select a board with name xc7a100tcsg324-1(last specified board in the
list).
2. To create a source file: Select add sources under Sources menu, then select Add or create design
sources, then select create file, provide file type(Verilog/VHDL) and file name as exp1a, then click
on finish. At define module window assign port names as per the considerations in the code. Source
file with file name exp1a will be created. Open that file and write the remaining code in editor &
save it.
3. Simulation: Select Run Simulation and then Behavioural Simulation. At simulation waveform
window to simulate the code right click on variable names such as a variable and then select Force
clock write the Leading and trailing edge values as 0 & 1 respectively, and fix the period as 50ns or
any. Then do force clock/force value for all variables. Then run the code and verify the input and
output logic through the simulation waveforms. 4. Save the code and check the syntax in the
synthesize-xst menu until no errors are found.
5. RTL Analysis: Set the Open elaborated design under RTL analysis. At the bottom of the window
do the scalar ports selection that is Input/ Output ports pins w.r.t Artix7 board I/O pin names and
give LVCMOS33 at I/O Std for all selected pins. Then save the constraints by providing the file
name as gates or any. Then view the .xdc file by selecting Sources --> Constraints-->gates.xdc.
6. Synthesis: Set Run synthesis --> Launch Runs on local host--> Wait --> Open Synthesized
Design. View RTL Schematic and Synthesized reports.
7. Implementation: Set Run Implementation --> Launch Runs on local host--> Wait --> Open
implemented Design. View RTL Schematic and implementation reports.
8. Generate Bit stream: Select Generate Bit stream under Program and Debug option, after
successful completion of it, select open hardware manager --> open target --> Auto connect -->
Program Device and then verify the output in the FPGA Artix7 Kit

Vivado Design Suite User Guide: https://docs.xilinx.com/r/2021.1-English/ug893-

vivado- ide/Introduction
Creating a New Project
Creating a New
Project
• Launch Xilinx Vivado 2019.1 and click on Create Project in Quick Start tab (or click on File -
> Project -> New). Set your project name and location, then click on Next.
• You can also open an existing project by clicking on Open Project in Quick Start tab
(or click on File -> Project -> Open), then browsing and selecting project_name.xpr
file.
Creating a New
Project
• Select project type as RTL Project and click on Next. In the next step, you can either add
design sources/constraint files by clicking on Create File button or you can skip this step
by clicking on Next (you can create files after you created the project).
Creating a New
Project
• You should select an FPGA device or Board for your project. In order to select PYNQ-
Z2 board, switch to Boards tab and select pynq-z2. Then click on Next and Finish.
Vivado Interface
Vivado Interface
Vivado Interface

Project Settings

Summary of project
Runs Behavioral
and results
Simulation

Shows design andsimulation

files with project hierarchy
Compiles RTL code
and loads RTL netlist

Implementation
run and settings
Messages tab shows useful information
(warnings, errors) about your design.
Vivado Interface
• From Settings under PROJECT MANAGER tab, you can change the settings of your
project (e.g., Board or FPGA).
Vivado Interface
• From Settings under PROJECT MANAGER tab, you can change the settings of
your project (e.g., Board or FPGA).
• For example, you can change the font type and size of the text editor.
Vivado Interface
• Language Templates under PROJECT MANAGER tab shows useful Verilog and
Xilinx IP constructions.
Vivado Interface
• See Vivado IDE Viewing Enviroment chapter of Vivado Design Suite User Guide[1].

[1] https://docs.xilinx.com/r/2021.1-English/ug893-vivado-ide/Vivado-IDE-Viewing-Environment
Adding/Creating Design and Simulation Files
Create a Design
Source
• For your design, you should add a design source (*.v file). Click on Add Sources in Flow
Navigator Window or "+" button on Sources window or File -> Add Sources on menu
bar, select Add or create design resources and then click on Next.
Create a Design
Source
• Click on Create File button, name your source file (e.g., design1.v) and click on Next.
• If you want to add an existing file to your project, click on Add Files and select the
files that you want to add to the project.
Create a Design
Source
• Set your module name (it is set as source file name per default) and click on OK. Then,
you will see your source file under Design Sources tab on Sources window.
Create a Design
Source
• Open design1.v and write the following (or any other) Verilog code as an example and
save it.
`timescale 1ns / 1ps

module design1(
input clk,
input [7:0] a,b,
input [15:0] c,
output[16:0] d
);

reg [15:0] m;
reg [16:0] d;

always @(posedge clk) begin

m <= a*b;
end

always @(posedge clk) begin

d <= m + c;
end

endmodule
Create a Simulation
Source
• In order to test your design, you should add a simulation source. Click on Add Sources in
Flow Navigator Window, select Add or create simulation resources and then click on
Next.
• Click on Create File button, name your simulation file (e.g., design1_tb.v) and click on
Next.
• Set your module name (it is set as simulation file name per default) and click on OK.
Then, you will see your simulation file under Simulation Sources tab on Sources window.
Create a Simulation
Source
• Open design1_tb.v and write the following example Verilog testbench code and save it.

‘ timescale 1ns / 1ps

module design1_tb();

reg [7:0] a,b;

reg [15:0] c;
wire [16:0] d;

design1 dut (a,b,c,d);

initial begin
a=0; b=0; c=0;
#10;
a=10; b=40; c=25;
#10;
a=53; b=19; c=100;
end

endmodule
Design Elaboration
• Design Elaboration and RTL Analysis
• It compiles RTL code and loads RTL netlist
• You can check RTL structure, syntax, and logic definitions
• You can view the schematic of your design
Running Behavioral Simulation
Behavioral Simulation
• Before running simulation, first make sure that your simulation source (testbench) is
selected as top simulation module (its module name should be in boldcase letters)
under Simulation Sources tab on Sources window.
• If it is not, right click on its name and click on Set as Top.
• Then, click on Run Simulation in Flow Navigator Window and click Run
Behavioral Simulation.
Behavioral Simulation
• If there is no error in your design and testbench files, you will see the following
simulation screen.

Save waveform configuration

Zoom in to area where cursor is

Zoom out from area where cursor is

Fit whole run into waveform

Go to time=0

Go to the last time

Behavioral Simulation
• You can change radix of the signals in the
waveform window. For example, right click on
signal name and then select Radix -> Unsigned
decimal to change representation of this
signal from hexadecimal to unsigned decimal.

• Similarly, you can change the color of the signal.

For example, right click on signal name and then
select Signal Color -> Yellow to change the color
of this signal from lime to yellow.
Behavioral Simulation
• Change radix of the signals to the unsigned decimal. Then, zoom in to the beginning of
the simulation. Now you can observe output d.
Behavioral Simulation
• In the toolbar on the top, you will see some shortcut buttons for simulation.

Restart the simulation. Use this to restart the simulation with current state of the
design. Run All. Use this to run simulation until it reaches a stop/finish command in
testbench .

Run for specified time. Use this to run simulation for specified time.
Time and unit. Use this to specify run time and unit for the command above.

Relaunch the simulation. Use this to relaunch the simulation for elaborating
the changes you made in your design.
Behavioral Simulation
• In the Scope window, you can see the design hierarchy. When you select a scope in
the Scope window, all HDL objects visible from that scope appear in the Objects window.
Behavioral Simulation
• When you start simulation, you will see signals defined in testbench on the waveform.
In order to observe internal signals (for debugging), click on the module you want to
investigate on Scope window. Then right click on the signal you want to observe in the
Objects window and click on Add to wave window.
Synthesis/Implementation
Constraint File
• Constraint file
• Timing: For setting clock frequency of your design
• Placement: For floorplanning
• I/O: Assigning your design inputs/outputs to FPGA pins
• Other user-defined constraints (i.e., false paths)

• For adding the constraint file, click on Add Sources in Flow Navigator Window, select Add
or create constraints and then click on Next.
• Click on Create File button, name your simulation file (e.g., const.xdc) and click on Next.
• Then, you will see your source file under Design Sources tab on Sources window.
Constraint File
• We will only use timing constraint for clock frequency/period [1]

create_clock -name clk -period PERIOD [get_ports PORT_NAME]

[1] https://docs.xilinx.com/r/2021.2-English/ug835-vivado-tcl-commands/create_clock
Synthesis
• Synthesis translates RTL code to a netlist which defines the circuit[1]
• You can change synthesis strategy (i.e., area optimized or performance
optimized) from synthesis settings (right click on SYNTHESIS -> Synthesis Settings)
• For starting synthesis, click on Run Synthesis.

[1] https://docs.xilinx.com/v/u/2021.1-English/ug901-vivado-synthesis
Synthesis
• After synthesis is finished, you can directly start implementation, open the
synthesized
design
• Youorcan
viewsee
synthesis reports.
synthesis report summary in Project
Summary.
Synthesis
• After synthesis is finished, you can directly start implementation, open the
synthesized
design
• Youorcan
viewsee
synthesis reports.
synthesis report summary in Project
Summary.
• For detailed report/results, open the synthesized design.
Implementation
• Implementation takes the netlist with user constraint and maps it to actual
FPGA components[1].
• Similar to Synthesis, you can change implementation strategy
• For starting implementation, click on Run Implementation.

• After implementation is finished, you can start bitstream generation, open

the implemented design or view implementation report.
• You can see implementation report(area and timing) in Project Summary.

[1] https://docs.xilinx.com/r/2021.1-English/ug904-vivado-implementation/Revision-History
Implementation
• For detailed report/results and the placed & routed design, open the implemented design.
Placed design

For detailed
timing report

For detailed
utilization report

Timing summary
Implementation
• For detailed report/results and the placed & routed design, open the implemented design.
• Placed design
Implementation
• For detailed report/results and the placed & routed design, open the implemented
• Detailed timing result (showing critical paths in your design).
design.
• Worst Negative Slack (WNS): If it is negative, then it means your design could not
meet the timing requirement (given in your constraint file) and your design has failing
paths.
• Click on WNS value to see critical paths.
Implementation
• For detailed report/results and the placed & routed design, open the implemented
design.
• Detailed timing result (showing critical paths in your design).
Implementation
• For detailed report/results and the placed & routed design, open the implemented
design.
• Detailed area (utilization) result.
information such as the main messages, warnings, errors.