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MODULE 3(b)
DATA TYPES

2.1 Built in Data types

SystemVerilog introduces several built-in data types that enhance the capabilities of Verilog. These
data types are designed to improve performance, reduce memory usage, and provide more flexibility in
modeling and verification. The built-in data types in SystemVerilog:

1. Logic Type: A 4-state data type (0,1,X,Z) that can be used in place of reg and wire.

 Usage: Can be driven by continuous assignments, gates, and modules, in addition to being used as
a variable.
 Example:

logic [7:0] data;

2. Bit Type: A 2-state data type that can only hold 0 or 1.

 Usage: Useful for modeling hardware where X and Z states are not needed.
 Example:

bit [3:0] nibble;

3. Byte, Shortint, Int, Longint: Signed 2-state data types of different sizes.

byte: 8 bits
shortint: 16 bits
int: 32 bits
longint: 64 bits

 Usage: Useful for arithmetic operations and when specific bit-widths are required.
 Example:

byte b;
shortint si;
int i;
longint li;

4. Integer: A 32-bit signed 4-state data type.

 Usage: Similar to int, but can hold X and Z states.

 Example:

integer count;

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5. Time: A 64-bit unsigned 4-state data type.

 Usage: Used for storing simulation time values.

 Example:

time t;

6. Real and Shortreal: Floating-point data types.

 real: Double-precision (64 bits)

 shortreal: Single-precision (32 bits)
 Usage: Useful for modeling analog values and performing floating-point arithmetic.
 Example:

real r;
shortreal sr;

7. String: A variable-length sequence of characters.

 Usage: Useful for handling text and messages.

 Example:

string name;

8. Chandle: A handle to a C object.

 Usage: Used for interfacing with C code through the Direct Programming Interface (DPI).
 Example:

chandle c_obj;

9. Event: A synchronization primitive.

 Usage: Used for synchronizing between different processes.

 Example:

event e;

10. Void: Represents the absence of a value.

 Usage: Used as a return type for functions that do not return a value.
 Example:

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function void display();

// Function body
endfunction

SystemVerilog's built-in data types provide a rich set of tools for modeling and verification. They allow
for more precise and efficient representation of hardware and enable advanced verification techniques.
By understanding and utilizing these data types, one can create more robust and flexible testbenches
and models.

2.2 Fixed and Dynamic Arrays

In SystemVerilog, arrays can be either fixed-size or dynamic, each serving different purposes and
offering various features.

Fixed-Size Arrays: Fixed-size arrays have a predetermined size that is set at compile time. The size
cannot be changed during simulation.

Declaration: A fixed-size array is declared by specifying the size in square brackets.

int fixed_array[10]; // An array of 10 integers

Initialization: A fixed-size array is initialized at the time of declaration.

int fixed_array[5] = '{1, 2, 3, 4, 5}; // Initializing with values

Usage:

 Fixed-size arrays are useful when the number of elements is known and constant.
 They are efficient in terms of memory usage since the size is fixed and allocated at compile time.

Example:

int fixed_array[4] = '{0, 1, 2, 3};

for (int i = 0; i < 4; i++) begin
$display("fixed_array[%0d] = %0d", i, fixed_array[i]);
end

Dynamic Arrays: Dynamic arrays do not have a fixed size at compile time. Their size can be changed
during simulation.

Declaration: A dynamic array is declared with empty square brackets.

int dynamic_array[]; // A dynamic array of integers

Allocation: Memory is allocated for a dynamic array using the new[] constructor.

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dynamic_array = new[10]; // Allocating 10 elements

Resizing: Dynamic arrays can be resized during simulation.

dynamic_array = new[20]; // Resizing to 20 elements

Usage:

 Dynamic arrays are useful when the number of elements can vary during simulation.
 They provide flexibility but can be less efficient in terms of memory usage compared to fixed-size
arrays.

Example:

int dynamic_array[];
dynamic_array = new[5]; // Allocating 5 elements
for (int i = 0; i < 5; i++) begin
dynamic_array[i] = i * 2;
end
for (int i = 0; i < 5; i++) begin
$display("dynamic_array[%0d] = %0d", i, dynamic_array[i]);
end

Difference between Fixed-Size and Dynamic Arrays:

1. Size:

Fixed-size arrays have a constant size determined at compile time.

Dynamic arrays can change size during simulation.
2. Memory Allocation:

 Fixed-size arrays allocate memory at compile time.

 Dynamic arrays allocate memory at runtime, which can be resized as needed.
3. Flexibility:

 Fixed-size arrays are less flexible but more efficient in terms of memory usage.
 Dynamic arrays offer greater flexibility but may have overhead due to dynamic memory
management.

Choosing Between Fixed-Size and Dynamic Arrays

 Use fixed-size arrays when the number of elements is known and constant throughout the
simulation.
 Use dynamic arrays when the number of elements can vary, providing the flexibility to allocate
and resize as needed during simulation.

By understanding the characteristics and use cases of fixed-size and dynamic arrays, one can choose
the appropriate type for specific needs in SystemVerilog.

2.3 Queues

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In SystemVerilog, a queue is a dynamic array that allows elements to be added or removed from either
end efficiently. Queues are particularly useful for modeling FIFO (First In, First Out) structures and
other dynamic data structures where the size can change during simulation.

 Queue Declaration: A queue is declared using the [$] syntax.

int queue[$]; // A queue of integers

 Queue Initialization: A queue is initialized using an array literal.

int queue[$] = '{1, 2, 3, 4, 5}; // Initializing with values

Methods and Operations

Queues come with several built-in methods that make them versatile and easy to use:

1. Insert and Delete Methods:

 push_back: Adds an element to the end of the queue.

queue.push_back(6); // Adds 6 to the end

 push_front: Adds an element to the front of the queue.

queue.push_front(0); // Adds 0 to the front

 pop_back: Removes and returns the last element of the queue.

int last = queue.pop_back(); // Removes and returns the last element

 pop_front: Removes and returns the first element of the queue.

int first = queue.pop_front(); // Removes and returns the first element

2. Access Methods:

 Indexing: Access elements using an index.

int second = queue[1]; // Accesses the second element

 size: Returns the number of elements in the queue.

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int size = queue.size(); // Gets the size of the queue

3. Iteration:

 foreach: Iterates over each element in the queue.

foreach (queue[i]) begin

$display("queue[%0d] = %0d", i, queue[i]);
end

Example

module queue_example;
int queue[$] = '{1, 2, 3, 4, 5}; // Initializing a queue

initial begin
// Display initial queue
$display("Initial queue:");
foreach (queue[i]) begin
$display("queue[%0d] = %0d", i, queue[i]);
end

// Push elements to the queue

queue.push_back(6);
queue.push_front(0);

// Display queue after push operations

$display("Queue after push operations:");
foreach (queue[i]) begin
$display("queue[%0d] = %0d", i, queue[i]);
end

// Pop elements from the queue

int last = queue.pop_back();
int first = queue.pop_front();

// Display queue after pop operations

$display("Queue after pop operations:");
foreach (queue[i]) begin
$display("queue[%0d] = %0d", i, queue[i]);
end

// Display popped elements

$display("Popped elements: first = %0d, last = %0d", first, last);
end
endmodule

 Dynamic Size: Queues can grow and shrink dynamically during simulation.
 Efficient Operations: Adding and removing elements from either end of the queue is efficient.
 Versatile: Queues are useful for modeling FIFOs, buffers, and other dynamic data structures.

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By understanding and utilizing queues in SystemVerilog, one can create more flexible and efficient
testbenches and models.

2.4 Associative Arrays

Associative arrays in SystemVerilog are a powerful feature that allows to create arrays with non-
contiguous or non-integer indices. They are particularly useful for modeling sparse memories or lookup
tables where the index values are not sequential or are widely spaced.

 Associative Array Declaration: An associative array is declared using the [*] syntax, where the
index type is specified inside the square brackets.

int assoc_array[string]; // Associative array with string indices

 Associative Array Initialization: You can initialize an associative array using an array literal with
index-value pairs.

int assoc_array[string] = '{"one": 1, "two": 2, "three": 3}; // Initializing with values

Methods and Operations

Associative arrays come with several built-in methods that make them versatile and easy to use:

1. Insert and Delete Methods:

 exists: Checks if an element with a specified index exists in the array.

if (assoc_array.exists("one")) begin
$display("Element 'one' exists");
end

 delete: Removes an element with a specified index from the array.

assoc_array.delete("two"); // Removes the element with index "two"

2. Access Methods:

 Indexing: Access elements using an index.

int value = assoc_array["three"]; // Accesses the element with index "three"

 size: Returns the number of elements in the array.

int size = assoc_array.size(); // Gets the size of the array

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3. Iteration:

 foreach: Iterates over each element in the associative array.

foreach (assoc_array[i]) begin

$display("assoc_array[%s] = %0d", i, assoc_array[i]);
end

4. First and Next Methods:

 first: Returns the first index in the associative array.

string first_index;
if (assoc_array.first(first_index)) begin
$display("First index: %s", first_index);
end

 next: Returns the next index in the associative array.

string next_index;
if (assoc_array.first(next_index)) begin
do begin
$display("Index: %s, Value: %0d", next_index, assoc_array[next_index]);
end while (assoc_array.next(next_index));
end

Example

module associative_array_example;
int assoc_array[string]; // Declaring an associative array

initial begin
// Initializing the associative array
assoc_array["one"] = 1;
assoc_array["two"] = 2;
assoc_array["three"] = 3;

// Display initial associative array

$display("Initial associative array:");
foreach (assoc_array[i]) begin
$display("assoc_array[%s] = %0d", i, assoc_array[i]);
end

// Check if an element exists

if (assoc_array.exists("two")) begin
$display("Element 'two' exists");
end

// Delete an element

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assoc_array.delete("two");

// Display associative array after deletion

$display("Associative array after deletion:");
foreach (assoc_array[i]) begin
$display("assoc_array[%s] = %0d", i, assoc_array[i]);
end

// Get the size of the associative array

int size = assoc_array.size();
$display("Size of associative array: %0d", size);

// Iterate using first and next methods

string index;
if (assoc_array.first(index)) begin
do begin
$display("Index: %s, Value: %0d", index, assoc_array[index]);
end while (assoc_array.next(index));
end
end
endmodule

 Sparse Indexing: Associative arrays are ideal for sparse indexing where the indices are not
contiguous or are widely spaced.
 Dynamic Size: The size of an associative array can change dynamically during simulation.
 Efficient Access: Associative arrays provide efficient access to elements using non-integer indices.
 Versatile: They are useful for modeling lookup tables, sparse memories, and other data structures
with non-sequential indices.

By understanding and utilizing associative arrays in SystemVerilog, one can create more flexible and
efficient testbenches and models.

2.5 Linked Lists

Linked lists are a fundamental data structure used to store a collection of elements. Unlike arrays, linked
lists do not require contiguous memory allocation, making them flexible and efficient for certain
operations. A linked list consists of nodes, where each node contains data and a reference (or link) to
the next node in the sequence. The primary types of linked lists are:

1. Singly Linked List: Each node points to the next node.

2. Doubly Linked List: Each node points to both the next and the previous node.
3. Circular Linked List: The last node points back to the first node, forming a circle.

In SystemVerilog, a node can be defined using a class.

class Node;
int data;
Node next;

// Constructor
function new(int data);
this.data = data;
this.next = null;

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endfunction
endclass

Singly Linked List Operations

Insertion
1. At the Beginning:

function void insert_at_beginning(ref Node head, int data);

Node new_node = new(data);
new_node.next = head;
head = new_node;
endfunction

2. At the End:

function void insert_at_end(ref Node head, int data);

Node new_node = new(data);
if (head == null) begin
head = new_node;
end else begin
Node temp = head;
while (temp.next != null) begin
temp = temp.next;
end
temp.next = new_node;
end
endfunction

Deletion
1. From the Beginning:

function void delete_from_beginning(ref Node head);

if (head != null) begin
head = head.next;
end
endfunction

2. From the End:

function void delete_from_end(ref Node head);

if (head != null) begin
if (head.next == null) begin
head = null;
end else begin
Node temp = head;
while (temp.next.next != null) begin
temp = temp.next;
end
temp.next = null;

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end
end
endfunction

Traversal

To traverse a linked list, one can use a simple loop:

function void traverse(Node head);

Node temp = head;
while (temp != null) begin
$display("Data: %0d", temp.data);
temp = temp.next;
end
endfunction

Example

Here is an example module that demonstrates the creation and manipulation of a singly linked list:

module linked_list_example;
Node head;

initial begin
// Insert elements
insert_at_beginning(head, 10);
insert_at_beginning(head, 20);
insert_at_end(head, 30);

// Traverse and display the list

$display("Linked List:");
traverse(head);

// Delete elements
delete_from_beginning(head);
delete_from_end(head);

// Traverse and display the list again

$display("Linked List after deletions:");
traverse(head);
end
endmodule

 Dynamic Memory Allocation: Linked lists use dynamic memory allocation, allowing for efficient
insertion and deletion operations.
 Flexibility: Linked lists can grow and shrink in size dynamically, unlike arrays with fixed sizes.
 Traversal: Traversing a linked list involves following the links from one node to the next.

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By understanding and utilizing linked lists in SystemVerilog, one can create more flexible and efficient
data structures for testbenches and models.

2.6 Array Methods

Array methods in SystemVerilog provide powerful tools for manipulating arrays. These methods can
be applied to any unpacked array types, including fixed-size, dynamic, queue, and associative arrays.
Here are the key array methods, along with detailed explanations and examples:

2.6.1. Reduction Methods

Reduction methods perform operations that reduce an array to a single value. Common reduction
methods include sum, product, and logical operations like and, or, and xor.

 Example: Sum of an Array

int array[5] = '{1, 2, 3, 4, 5};

int total = array.sum();
$display("Sum of array: %0d", total); // Output: Sum of array: 15

 Example: Logical AND of an Array

bit [3:0] bits = 4'b1101;

bit result = bits.and();
$display("Logical AND of bits: %b", result); // Output: Logical AND of bits: 0

2.6.2. Locator Methods

Locator methods help find specific elements within an array. These methods include min, max, unique,
find, find_index, and more.

 Example: Finding the Minimum Value

int array[5] = '{10, 20, 5, 30, 15};

int min_value = array.min();
$display("Minimum value: %0d", min_value); // Output: Minimum value: 5

 Example: Finding Unique Values

int array[5] = '{1, 2, 2, 3, 3};

int unique_values[] = array.unique();
foreach (unique_values[i]) begin
$display("Unique value: %0d", unique_values[i]);
end
// Output: Unique value: 1
// Unique value: 2
// Unique value: 3

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 Example: Finding an Element

int array[5] = '{10, 20, 30, 40, 50};

int index = array.find_index(x) with (x == 30);
$display("Index of 30: %0d", index); // Output: Index of 30: 2

2.6.3. Sorting and Ordering Methods

These methods allow you to sort the elements of an array, reverse their order, or shuffle them randomly.

 Example: Sorting an Array

int array[5] = '{30, 10, 50, 20, 40};

array.sort();
foreach (array[i]) begin
$display("Sorted array[%0d]: %0d", i, array[i]);
end
// Output: Sorted array[0]: 10
// Sorted array[1]: 20
// Sorted array[2]: 30
// Sorted array[3]: 40
// Sorted array[4]: 50

 Example: Reversing an Array

int array[5] = '{10, 20, 30, 40, 50};

array.reverse();
foreach (array[i]) begin
$display("Reversed array[%0d]: %0d", i, array[i]);
end
// Output: Reversed array[0]: 50
// Reversed array[1]: 40
// Reversed array[2]: 30
// Reversed array[3]: 20
// Reversed array[4]: 10

 Example: Shuffling an Array

int array[5] = '{10, 20, 30, 40, 50};

array.shuffle();
foreach (array[i]) begin
$display("Shuffled array[%0d]: %0d", i, array[i]);
end
// Output: Shuffled array[0]: 30
// Shuffled array[1]: 10
// Shuffled array[2]: 50
// Shuffled array[3]: 20

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// Shuffled array[4]: 40

These array methods make it easier to manipulate and analyze arrays in SystemVerilog, enhancing the
efficiency and readability of your testbench code.

2.7 Choosing a Storage Type

When selecting a storage type in SystemVerilog, consider the following factors:

2.7.1 Flexibility

 Fixed-Size Arrays: Use these if the array size is known at compile time.
 Dynamic Arrays: Suitable when the array size is determined at runtime.
 Associative Arrays: Ideal for non-standard indices or sparse data.
 Queues: Best for data that grows and shrinks frequently during simulation.

2.7.2 Memory Usage

 2-State Elements: Use these to reduce memory usage.

 Packed Arrays: Help conserve memory by storing data contiguously.
 Dynamic Arrays and Queues: Efficient for arrays with up to a million elements.
 Associative Arrays: Use more memory due to pointer overhead but are efficient for sparse data.

2.7.3 Speed

 Fixed-Size and Dynamic Arrays: Provide constant-time access to elements.

 Queues: Efficient for adding/removing elements at the ends but slower for middle operations.
 Associative Arrays: Slower due to search operations but useful for large, sparse datasets.

2.7.4 Data Access

 Sorting: Fixed-size, dynamic arrays, and queues can be sorted.

 Associative Arrays: Cannot be sorted but are useful for unique, non-contiguous values.

2.7.5 Choosing the Best Data Structure

 Network Packets: Use fixed-size or dynamic arrays.

 Scoreboards: Use queues for dynamic size and associative arrays for large datasets.
 Large Memories: Use associative arrays for sparse memories.
 Command Names/Opcodes: Use associative arrays with string indices.

2.8 User-Defined Types with typedef

Creating New Types
SystemVerilog allows you to create new types using the typedef statement. This is useful for creating
more readable and maintainable code.
Example:
typedef logic [31:0] uint_t;
uint_t my_var;

Defining Array Types: You can define new array types using typedef.
Example:

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typedef logic [7:0] byte_array_t[5];

byte_array_t my_array = '{8'h01, 8'h23, 8'h45, 8'h67, 8'h89};

Associative Arrays: Associative arrays can be declared with a user-defined index type.
Example:
typedef int unsigned addr_t;
typedef logic [31:0] mem_t[addr_t];
mem_t memory;

Creating User-Defined Structures

Structures: SystemVerilog allows you to create structures using the struct statement, similar to C.
Example:
typedef struct {
logic [7:0] red;
logic [7:0] green;
logic [7:0] blue;
} pixel_t;
pixel_t pixel;

Initializing Structures: Structures can be initialized using an array literal.

Example:
pixel_t pixel = '{8'hFF, 8'h00, 8'h00}; // Red color

Packed Structures: Packed structures are stored as contiguous bits without any padding.
Example:
typedef struct packed { logic [7:0] red; logic [7:0] green; logic [7:0] blue; }
packed_pixel_t;
packed_pixel_t packed_pixel;

Unions: Unions allow multiple views of the same data.

Example:
typedef union { logic [31:0] int_view; logic [7:0] byte_view[4]; }
data_u;
data_u data;

Enumerated Types: Enumerated types allow you to create a set of named constants.
Example:
typedef enum logic [1:0] {
IDLE = 2'b00,
READ = 2'b01,
WRITE = 2'b10
} state_t;
state_t state;

Enumerated Values: You can specify the values of enumerated constants.

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Example: systemverilog typedef enum logic [2:0] { INIT = 3'b000, RUN = 3'b001, STOP = 3'b010 }
mode_t; mode_t mode;

Type Conversion

 Static Cast: Converts between types without checking values.

Example:
int a = 32;
logic [31:0] b;
b = int'(a);

Dynamic Cast: Checks for out-of-bounds values during conversion.

Example:
state_t s;
int i = 2;
if (!$cast(s, i))
begin
$display("Invalid cast");
end

Streaming Operators: Used to pack and unpack data.

Example:
logic [31:0] data;
byte_array_t bytes;
{<<{bytes}} = data; // Pack data into bytes

2.9 Constants, Strings and Expression Width

Constants: SystemVerilog provides several ways to define constants, which can make our code more
readable and maintainable.

1. Text Macros: The classic way to define constants in Verilog is using text macros. However,
these have global scope and can lead to name conflicts.
o Example:`define TIMEOUT 100
2. Parameters: Parameters are loosely typed and limited in scope to a single module. Verilog-
2001 added typed parameters, which can be declared in a package for broader use.
o Example: parameter int TIMEOUT = 100;
3. const Modifier: SystemVerilog introduces the const modifier, which allows you to declare a
variable that can be initialized but not modified by procedural code.
o Example: systemverilog const int TIMEOUT = 100;

Strings in SystemVerilog

Strings: SystemVerilog significantly improves the handling of strings compared to Verilog.

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1. String Type: SystemVerilog introduces a string type that holds variable-length strings.
Memory for strings is dynamically allocated, so you don't need to worry about running out of
space.
o Example: string my_string = "Hello, World!";
2. String Operations: SystemVerilog provides several built-in methods for string manipulation.
o Getting a Character: getc(N) returns the byte at location N.
o Upper and Lower Case: toupper returns an upper-case copy of the string, and tolower
returns a lower-case copy.
o Concatenation: You can concatenate strings using the {} operator.
o Example: string s1 = "Hello";
string s2 = "World";
string s3 = {s1, ", ", s2, "!"}; // "Hello, World!"

3. String Comparison: There are two ways to compare strings:

o Equality Operator: s1 == s2 returns 1 if the strings are identical, and 0 if they are not.
o Comparison Function: s1.compare(s2) returns 1 if s1 is greater than s2, 0 if they are
equal, and -1 if s1 is less than s2.
o Example: if (s1 == s2) begin
$display("Strings are equal");
end

4. String Formatting: SystemVerilog includes the $sformatf function, which returns a formatted
string.
o Example: string formatted_string; formatted_string = $sformatf("Value: %0d", 42);

These features make it much easier to work with strings and constants in SystemVerilog, enhancing the
readability and maintainability of code.

Expression Width: In SystemVerilog, the width of expressions can sometimes lead to unexpected
results, especially when dealing with different data types and operations. Here are some key points to
consider:

1. Context-Dependent Width:
The width of an expression in SystemVerilog can depend on the context in which it is used. For
example, the width of the result of an addition operation can vary based on the operands involved.

2. Default Widths:
By default, SystemVerilog uses the width of the largest operand in an expression to determine the
width of the result. This can lead to issues if the operands have different widths.

3. Explicit Width Specification:

To avoid ambiguity, you can explicitly specify the width of an expression using casting. For example,
you can cast an operand to a specific width before performing an operation.

4. Common Pitfalls:
 Narrowing Conversions: When a wider operand is assigned to a narrower variable, the higher-
order bits may be truncated, leading to potential data loss.
 Sign Extension: When performing operations on signed numbers, SystemVerilog may extend
the sign bit to preserve the sign of the result, which can affect the width of the expression.

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Examples

1. Addition Example:

bit [3:0] a = 4'b0011;

bit [7:0] b = 8'b00001111;
bit [7:0] result;

// Without casting, the result width is determined by the largest operand

result = a + b; // result is 8 bits wide

2. Using Casting:

bit [3:0] a = 4'b0011;

bit [7:0] b = 8'b00001111;
bit [7:0] result;

// Explicitly cast 'a' to 8 bits before addition

result = {4'b0000, a} + b; // result is 8 bits wide

3. Avoiding Truncation:

bit [3:0] a = 4'b0011;

bit [7:0] b = 8'b00001111;
bit [3:0] result;

// Potential truncation if result is narrower than the operands

result = a + b; // result is 4 bits wide, higher bits of the sum are truncated

 Always be mindful of the widths of operands and results. When in doubt, use explicit casting to
ensure the desired width.
 Check for sign extension when dealing with signed numbers. Ensure that the sign extension does
not inadvertently change the width of your expression.
 Use simulation and synthesis tools to verify that your expressions are being evaluated with the
correct widths. These tools can often catch issues related to expression width that might not be
immediately obvious from the code.

By understanding and managing expression widths in SystemVerilog, one can avoid many common
pitfalls and ensure that designs behave as expected.

DEPARTMENT OF ECE, SMVITM 18