Analog and Digital Electronics Laboratory Manual III Sem

Instructions to students

1. Students should leave their foot wares outside.

2. Students keep their bags in the rack.
3. Students must take care of their valuable things.
4. Students must bring Observation book, record and manual along with pen, pencil, and
eraser Etc., no borrowing from others.
5. Students must handle the trainer kit and other components carefully, as they are
expensive.
6. Before entering to lab, must prepare for Viva for which they are going to conduct
experiment.
7. Before switching on the trainer kit, must show the connections to one of the faculties
or instructors.
8. After the completion of the experiment should return the components to the respective
lab instructors.
9. Before leaving the lab, should check whether they have switch off the power supplies
and keep their chairs properly.
10. Wear your College ID card Do not operate the IC trainer kits without permission.
11. Avoid unnecessary talking while doing the experiment.
12. After completion of the experiment switch off the power and return the components.

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Rules for Maintaining Laboratory Record

1. Write your name, USN and subject on the outside front cover of the record.
Write that same information on the first page inside.
2. Update Table of Contents every time you start each new experiment or topic.
3. Always use pen and write neatly and clearly.
4. Start each new topic (experiment, notes, calculation, etc.) on a right-side (odd
numbered) page.
5. Obvious care should be taken to make it readable, even if you have bad handwriting.
6. Date to be written every page on the top right side corner.
7. On each right side page
 Title of experiment
 Aim/Objective
 Components Required
 Theory/Procedure described clearly in steps
 Result


8. On each left side page

 Pin diagrams
 Circuit diagram
 Tables
 Graphs

9. Use labels and captions for figures and tables.
10. Attach printouts and plots of data as needed. Stick printouts(A4 Size)on the right
side of the lab record.

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ANALOG AND DIGITAL ELECTRONICS LABORATORY

[As per Choice Based Credit System (CBCS) scheme]
(Effective from the academic year 2015-2016)

SEMESTER – III

Laboratory Code : 15CSL37 IA Marks : 20

Number of Lecture Hours/Week : 01I + 02P Exam Marks : 80
Total Number of Lecture Hours : 40 Exam Hours: 03

Course objectives:
These laboratory courses enable students to get practical experience in design,
assembly and evaluation/testing of
 Analog components and circuits including Operational Amplifier, Timer, etc.

 Combinational logic circuits.

 Flip - Flops and their operations

 Counters and Registers using Flip-flops.

 Synchronous and Asynchronous Sequential Circuits.

 A/D and D/A Converters.

Any simulation package like MultiSim / P-spice /Equivalent software may be used.
Faculty-in-charge should demonstrate and explain the required hardware components and
their functional Block diagrams, timing diagrams etc. Students have to prepare a write-up on
the same and include it in the Lab record and to be evaluated.
Laboratory Session-1:
Write-upon analog components; functional block diagram, Pin diagram (if any),
waveforms and description. The same information is also taught in theory class; this helps the
students to understand better.
Laboratory Session-2:
Write-upon Logic design components, pin diagram (if any), Timing diagrams, etc.
The same information is also taught in theory class; this helps the students to understand
better Note: These TWO Laboratory sessions are used to fill the gap between theory classes
and practical sessions. Both sessions are to be evaluated for 20 marks as lab experiments.


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Laboratory Experiments

a) Design and construct a Schmitt trigger using Op-Amp for given UTP and LTP
values and demonstrate its working.
b) Design and implement a Schmitt trigger using Op-Amp using a simulation package
for two sets of UTP and LTP values and demonstrate its working.

a) Design and construct a rectangular waveform generator (Op-Amp relaxation

oscillator) for given frequency and demonstrate its working.
b) Design and implement a rectangular waveform generator (Op-Amp relaxation
oscillator) using a simulation package and demonstrate the change in frequency
when all resistor values are doubled.

3. Design and implement an Astable multivibrator circuit using 555 timer for a given
frequency and duty cycle.

4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using
basic gates.

a) Given a 4-variable logic expression, simplify it using Entered Variable Map and
realize the simplified logic expression using 8:1 multiplexer IC.
b) Design and develop the Verilog /VHDL code for an 8:1 multiplexer. Simulate and
verify it‟s working.

6. Design and implement code converter I) Binary to Gray II) Gray to Binary Code using
basic gates.

7. Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker
using basic Logic Gates with an even parity bit.

a) Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table.
b) Design and develop the Verilog /VHDL code for D Flip-Flop with positive-edge
triggering. Simulate and verify its working.

a) Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-
Flop ICs and demonstrate its working.
b) Design and develop the Verilog / VHDL code for mod-8 up counter. Simulate and
verify its working.

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10. Design and implement an asynchronous counter using decade counter IC to count up
from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).

11. Generate a Ramp output waveform using DAC0800 (Inputs are given to DAC
through IC74393 dual 4-bit binary counter).

Study experiment:
12. To study 4-bitALU using IC-74181.

Course outcomes:
On the completion of this laboratory course, the students will be able to:
1. Use various Electronic Devices like Cathode ray Oscilloscope, Signal generators,
Digital Trainer Kit, Multimeters and components like Resistors, Capacitors, Op amp
and Integrated Circuit.
2. Design and demonstrate various combinational logic circuits.
3. Design and demonstrate various types of counters and Registers using Flip-flops
4. Use simulation package to design circuits.
5. Understand the working and implementation of ALU.

Graduate Attributes (as per NBA)

1. Engineering Knowledge
2. Problem Analysis
3. Design/Development of Solutions
4. Modern Tool Usage

Conduction of Practical Examination:

1. All laboratory experiments (1 to 11) are to be included for practical examination.
2. Students are allowed to pick one experiment from the lot. Strictly follow the
instructions as printed on the cover page of answer script.
3. Marks distribution:
a ) For questions having part a only- Procedure + Conduction + Viva:20 + 50 +10
=80 Marks
b ) For questions having part a and b
Part a- Procedure + Conduction + Viva:10 + 35 +05= 50 Marks
Part b- Procedure + Conduction + Viva:10 + 15 +05= 30 Marks
5. Change of experiment is allowed only once and marks allotted to the procedure part
to be made zero.

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Laboratory Session-1

Write-upon analog components; functional block diagram, Pin diagram (if any),
waveforms and description. The same information is also taught in theory class; this
helps the students to understand better.

DIODE
Diodes must be connected the correct way round, the diagram may be labeled a or +
for anode and k or - for cathode (yes, it really is k, not c, for cathode!). The cathode is
marked by a line painted on the body. Diodes are labeled with their code in small print; you
may need a magnifying glass to read this on small signal diodes.

Testing a diode with a DIGITAL Multimeter

1. Digital Multimeter has a special setting for testing a diode, usually labeled with the
diode symbol.
2. Connect the red (+) lead to the anode and the black (-) to the cathode. The diode
should conduct and the meter will display a value (usually the voltage across the
diode in mV, 1000mV = 1V).
3. Reverse the connections. The diode should NOT conduct this way so the meter will
display "off the scale" (usually blank except for a 1 on the left).

TRANSISTOR
A transistor is a semiconductor device used to amplify or switch electronic signals
and electrical power. It is composed of semiconductor material usually with at least three
terminals for connection to an external circuit. A voltage or current applied to one pair of the
transistor's terminals changes the current through another pair of terminals. Because the
controlled (output) power can be higher than the controlling (input) power, a transistor can
amplify a signal. Today, some transistors are packaged individually, but many more are
found embedded in integrated circuits.

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Testing a transistor with a Multimeter

Set a digital Multimeter to diode test and as described above for testing a diode.
Test each pair of leads both ways (six tests in total):
1. The base-emitter (BE) junction should behave like a diode and conduct one
way only.
2. The base-collector (BC) junction should behave like a diode and conduct one way
only.
3. The collector-emitter (CE) should not conduct either way.

Types of transistor:
There are two types of standard transistors, NPN and PNP, with different circuit
symbols. The letters refer to the layers of semiconductor material used to make the transistor.
Most transistors used today are NPN because this is the easiest type to make from silicon.
SL 100 is an NPN transistor.

RESISTORS
A register is a memory device that can be used to store more than one bit of
information. A register is usually realized as several flip-flops with common control signals
that control the movement of data to and from the register. „ Common refers to the property
that the control signals apply to all flip-flops in the same way „ A register is a generalization
of a flip-flop. Where a flipflop stores one bit, a register stores several bits „ The main
operations on a register are the same as for any storage devices, namely ‹Load or Store: Put
new data into the register ‹Read: Retrieve the data stored in the register (usually without
changing the stored data It is used to control the voltages and the currents in your circuit.

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CAPACITORS
A capacitor (originally known as a condenser) is a passive two-terminal electrical
component used to store electrical energy temporarily in an electric field. The forms of
practical capacitors vary widely, but all contain at least two electrical conductors (plates)
separated by a dielectric (i.e. an insulator that can store energy by becoming polarized). The
conductors can be thin films, foils or sintered beads of metal or conductive electrolyte, etc.
The non-conducting dielectric acts to increase the capacitor's charge capacity. Materials
commonly used as dielectrics include glass, ceramic, plastic film, air, vacuum, paper, mica,
and oxide layers. Capacitors are widely used as parts of electrical circuits in many common
electrical devices. Unlike a resistor, an ideal capacitor does not dissipate energy. Instead, a
capacitor stores energy in the form of an electrostatic field between its plates.

BREADBOARD
A breadboard is a material or a device used to build a prototype of an electronic
circuit. The breadboard has many strips of metal (copper usually) which run underneath the
board. The metal strips are laid out as shown These strips connect the holes on the top of the
board. This makes it easy to connect components together to build circuits. To use the bread
board the legs of components are placed in the holes (the sockets). The holes are made so that
they will hold the component in place. Each hole is connected to one of the metal strips
running underneath the board. The long top and bottom row of holes are usually used for
power supply connections.

INTEGRATED CIRCUIT
An Integrated Circuit (IC) consists of many basic electronic components. An
integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a
microchip) is a set of electronic circuits on one small plate ("chip") of semiconductor
material, normally silicon. This can be made much smaller than a discrete circuit made from

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independent electronic components. ICs can be made very compact, having up to several
billion transistors and other electronic components in an area the size of a human fingernail.

VOLTMETERS
A voltmeter, also known as a voltage meter, is an instrument used for measuring the
potential difference, or voltage, between two points in an electrical or electronic circuit.
Some voltmeters are intended for use in direct current (DC) circuits; others are designed for
alternating current (AC) circuits. Specialized voltmeters can measure radio frequency (RF)
voltage.
A basic analog voltmeter consists of a sensitive galvanometer (current meter) in series
with a high resistance. The internal resistance of a voltmeter must be high. Otherwise it will
draw significant current, and thereby disturb the operation of the circuit under test. The
sensitivity of the galvanometer and the value of the series resistance determine the range of
voltages that the meter can display.

AMMETER
Ammeter means Ampere-meter which measures ampere value. Ampere is the unit of
current so an ammeter is a meter or an instrument which measures current.

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Working Principle of Ammeter:

The main principle of ammeter is that it must have a very low resistance and also inductive
reactance. Now, why do we need this? can't we connect an ammeter in parallel? The answer
to this question is it has very low impedance because it must have very low amount of
voltage drop across it and must be connected in series connection because current is same in
the series circuit. Also due to very low impedence the power loss will be low and if it is
connected in parallel it becomes almost a short circuited path and all the current will flow
through ammeter as a result of high current the instrument may burn. So due to this reason it
must be connected in series. For an ideal ammeter, it must have zero impedance so that it has
zero voltage drop across it so the power loss in the instrument is zero. But the ideal is not
achievable practically.

POTENTIOMETER
This is a very basic instrument used for comparing emf two cells and for calibrating
ammeter, voltmeter and watt-meter. The basic working principle of potentiometer is very
very simple. Suppose we have connected two battery in head to head and tale to tale through
a galvanometer. That means the positive terminals of both battery are connected together and
negative terminals are also connected together through a galvanometer as shown in the
figure. Here in the figure it is clear that if the voltage of both battery cells is exactly equal,
there will be no circulating current in the circuit and hence the galvanometer shows null
deflection. The working principle of potentiometer depends upon this phenomenon.

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OSCILLOSCOPE

An oscilloscope is easily the most useful instrument available for testing circuits because it
allows you to see the signals at different points in the circuit. The best way of investigating
an electronic system is to monitor signals at the input and output of each system block,
checking that each block is operating as expected and is correctly linked to the next.
The screen of this oscilloscope has 8 squares or divisions on the vertical axis, and 10
squares or divisions on the horizontal axis. Usually, these squares are 1 cm in each direction:
Setting up the CRO:
i. Before you switch the oscilloscope on, check that all the controls are in their 'normal'
positions.
1. all push button switches are in the OUT position
2. all slide switches are in the UP position
3. all rotating controls are CENTRED
ii. Check through all the controls and put them in these positions:
iii. Set both VOLTS/DIV controls to 1 V/DIV and the TIME/DIV control to 2 s/DIV, its
slowest setting:
iv. Switch ON, red button, top center:

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The green LED illuminates and, after a few moments, you should see a small bright spot, or
trace, moving fairly slowly across the screen.

v. Find the Y-POS 1 control:

The Y-POS 1 allows you to move the spot up and down the screen. For the present,
adjacent trace so that it runs horizontally across the centre of the screen.
vi. Now investigate the INTENSITY and FOCUS controls:
When these are correctly set, the spot will be reasonably bright but not glaring,
and as sharply focused as possible. (The TR control is screwdriver adjusted. It is only
needed if the spot moves at an angle rather than horizontally across the screen with no
signal connected).

Adjusting the INTENSITY control changes the brightness of the oscilloscope

display. The FOCUS should be set to produce a bright clear trace. If required, TR can be
adjusted using a small screwdriver so that the oscilloscope trace is exactly horizontal
when no signal is connected.
vii. The TIME/DIV control determines the horizontal scale of the graph which
appears on the oscilloscope screen.
viii. The VOLTS/DIV controls determine the vertical scale of the graph drawn on the
oscilloscope screen.

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The diagram shows a lead with a BNC plug at one end and crocodile clips at the other. Adjust
VOLTS/DIV and TIME/DIV until you obtain a clear picture of the signal, which should look
like this:
DC/AC/GND slide switches: In the DC position, the signal input is connected directly to the
Y-amplifier of the corresponding channel, CH I or CH II. In the AC position, a capacitor is
connected into the signal pathway so that DC voltages are blocked and only changing AC
signals are displayed.
In the GND position, the input of the Y-amplifier is connected to 0 V. This allows you to
check the position of 0 V on the oscilloscope screen.
Trace selection switches: The settings of these switches control which traces appear on the
oscilloscope screen.

OP AMP (OPERATIONAL AMPLIFIER)

Electronic amplifiers covert a signal that carries a low amount of energy, whether it is
audio or video, into a signal with a high amount of energy. The signal is not modified, only
amplified. In the case of sound, the signal output is greater in magnitude. In other words, if a
radio is not loud, an amplifier can make it loud.
Amplifiers can also work with light signals to make them brighter. For example, by
increasing the voltage, a signal can become brighter, as in a lamp which may have two or
three brightness settings. Some other examples of amplifiers are speakers, home stereo
systems or public address systems.
An Op-Amp can be conveniently divided in to four main blocks
1. An Input Stage or Input Diff. Amp.
2. The Gain Stage

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3. The Level Translator

4. An Out put Stage

Note: It can be used to perform various mathematical operations such as Addition,
Subtraction, Integration, Differentiation, log etc.

Where:
V+: non-inverting input
V−: inverting input
Vout: output
VS+: positive power supply (sometimes also VDD, VCC, or VCC + )
VS−: negative power supply (sometimes also VSS, VEE, or VCC − )

OP-AMP RELAXATION OSCILLATOR

Op-Amp Relaxation Oscillator is a simple Square wave generator which is also called as
a Free running oscillator or Astable multivibrator or Relaxation oscillator. In this figure the op-
amp operates in the saturation region. Here, a fraction (R 2/(R1+R2)) of output is fed back to the
noninverting input terminal. Thus reference voltage is (R2/(R1+R2)) Vo. And may take values as
+(R2/(R1+R2)) Vsat or - (R2/(R1+R2)) Vsat. The output is also fed back to the inverting input
terminal after integrating by means of a low-pass RC combination. Thus whenever the voltage at
inverting input terminal just exceeds reference voltage, switching takes place resulting in a square
wave output.

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Circuit Diagram
Design:
The period of the output rectangular wave is given as T =2RC ln (1+β/1- β ) ------- 1
Where,
β =R1/R1+ R2 is the feedback fraction
If R1 = R2, then from equation (1) we have T = 2RC ln(3) --------
2 Design for a frequency of 1 kHz (implies T
=1ms ) Let C=0.1μF
Then calculating R as R=T/2 Cln(3) =1*10-3/2*0.1*10-6 * 1.099 = 5*103
= 5K Select R=4.7KΩ
The voltage across the capacitor has a peak voltage of Vc =(R1/R1+ R2) Vsat

SIGNAL/FUNCTION GENERATOR
A function generator is a device that can produce various patterns of voltage at a
variety of frequencies and amplitudes. It is used to test the response of circuits to common
input signals. The electrical leads from the device are attached to the ground and signal input
terminals of the device under test.
Most function generators allow the user to choose the shape of the output from a small
number of options.
• Square wave - The signal goes

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• Sine wave - The signal curves like a sinusoid from high to low voltage.
• Triangle wave - The signal goes from high to low voltage at a fixed rate.

The amplitude control on a function generator varies the voltage diff and low voltage
of the output signal. The frequency control of a function generator controls the rate at which
output signal oscillates. Most function generators allow the user to choose the shape of the
output from a small number of options.

• Square wave - The signal goes directly from high to low voltage.
• Sine wave - The signal curves like a sinusoid from high to low voltage.
• Triangle wave - The signal goes from high to low voltage at a fixed rate.

The amplitude control on a function generator varies the voltage difference between
the high and low voltage of the output signal. The frequency control of a function generator
controls the rate at which output signal oscillates.
Switch on the function generator and adjust the output level to produce a visible
signal on the oscilloscope screen. Adjust TIME/DIV and VOLTS/DIV to obtain a clear
display and investigate the effects of pressing the waveform shape buttons. The rotating
FREQUENCY control and the RANGE switch are used together to determine the frequency
of the output signal.

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MULTIVIBRATOR
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output
waveform is rectangular. The multivibrators are classified as
1. Astable or free running multivibrator It alternates automatically between two states
(low and high for a rectangular output) and remains in each state for a time dependent
upon the circuit constants. It is just an oscillator as it requires no external pulse for its
operation.
2. Monostable or one shot multivibrators: It has one stable state and one quasi stable.
The application of an input pulse triggers the circuit time constants and the output
goes to the quazi stable state, after a period of time determined by the time constant,
the circuit returns to its initial stable state. The process is repeated upon the
application of each trigger pulse.
3. Bistable Multivibrators: It has both stable states. It requires the application of an
external triggering pulse to change the output from one state to other. After the output
has changed its state, it remains in that state until the application of next trigger pulse.
Flip flop is an example.

Connect the pin 2 to the CRO to get the capacitor waveform check the amplitude from the
waveform to get the UTP and LTP values.
Connect pin 3 to CRO to get the output. Find out the TH and TL values.

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555 TIMER
The 555 timer IC was introduced in the year 1970 by Signetic Corporation and gave
the name SE/NE 555 timer. It is basically a monolithic timing circuit that produces accurate
and highly stable time delays or oscillation. When compared to the applications of an op-amp
in the same areas, the 555IC is also equally reliable and is cheap in cost. Apart from its
applications as a monostable multivibrator and astable multivibrator, a 555 timer can also
be used in dc-dc converters, digital logic probes, waveform generators, analog frequency
meters and tachometers, temperature measurement and control devices, voltage regulators
etc. The timer IC is setup to work in either of the two modes – one-shot or monostable or as a
free-running or astable multivibrator.The SE 555 can be used for temperature ranges between
– 55°C to 125° . The NE 555 can be used for a temperature range between 0° to 70°C.

The important features of the 555 timer are :

It operates from a wide range of power supplies ranging from + 5 Volts to + 18 Volts
supply voltage.
 Sinking or sourcing 200 mA of load current.

 The external components should be selected properly so that the timing intervals can be
made into several minutes along with the frequencies exceeding several hundred kilo
hertz.

 The output of a 555 timer can drive a transistor-transistor logic (TTL) due to its high
current output.

 It has a temperature stability of 50 parts per million (ppm) per degree Celsius change in
temperature, or equivalently 0.005 %/ °C.

 The duty cycle of the timer is adjustable.

The maximum power dissipation per package is 600 mW and its trigger and reset inputs has
logic compatibility. More features are listed in the datasheet.

IC Pin Configuration:

The 555 Timer IC is available as an 8-pin metal can, an 8-pin mini DIP (dual-in-package) or
a 14-pin DIP. The pin configuration is shown in the figures.
This IC consists of 23 transistors, 2 diodes and 16 resistors. The use of each pin in the IC is
explained below. The pin numbers used below refers to the 8-pin DIP and 8-pin metal can
packages. These pins are explained in detail, and you will get a better idea after going
through the entire post.

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Pin 1: Grounded Terminal: All the voltages are measured with respect to the Ground
terminal.
Pin 2: Trigger Terminal: The trigger pin is used to feed the trigger input hen the 555 IC is
set up as a monostable multivibrator. This pin is an inverting input of a comparator and is
responsible for the transition of flip-flop from set to reset. The output of the timer depends on
the amplitude of the external trigger pulse applied to this pin. A negative pulse with a dc level
greater than Vcc/3 is applied to this terminal. In the negative edge, as the trigger passes
through Vcc/3, the output of the lower comparator becomes high and the complimentary of Q
becomes zero. Thus the 555 IC output gets a high voltage, and thus a quasi stable state.
Pin 3: Output Terminal: Output of the timer is available at this pin. There are two ways in
which a load can be connected to the output terminal. One way is to connect between output
pin (pin 3) and ground pin (pin 1) or between pin 3 and supply pin (pin 8). The load
connected between output and ground supply pin is called the normally on load and that
connected between output and ground pin is called the normally off load.
Pin 4: Reset Terminal: Whenever the timer IC is to be reset or disabled, a negative pulse is
applied to pin 4, and thus is named as reset terminal. The output is reset irrespective of the
input condition. When this pin is not to be used for reset purpose, it should be connected to +
VCC to avoid any possibility of false triggering.
Pin 5: Control Voltage Terminal: The threshold and trigger levels are controlled using this
pin. The pulse width of the output waveform is determined by connecting a POT or bringing
in an external voltage to this pin. The external voltage applied to this pin can also be used to
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modulate the output waveform. Thus, the amount of voltage applied in this terminal will
decide when the comparator is to be switched, and thus changes the pulse width of the
output. When this pin is not used, it should be bypassed to ground through a 0.01 micro
Farad to avoid any noise problem.
Pin 6: Threshold Terminal: This is the non-inverting input terminal of comparator 1, which
compares the voltage applied to the terminal with a reference voltage of 2/3 VCC. The
amplitude of voltage applied to this terminal is responsible for the set state of flip-flop. When
the voltage applied in this terminal is greater than 2/3Vcc, the upper comparator switches to
+Vsat and the output gets reset.
Pin 7 : Discharge Terminal: This pin is connected internally to the collector of transistor
and mostly a capacitor is connected between this terminal and ground. It is called discharge
terminal because when transistor saturates, capacitor discharges through the transistor. When
the transistor is cut-off, the capacitor charges at a rate determined by the external resistor and
capacitor.
Pin 8: Supply Terminal: A supply voltage of + 5 V to + 18 V is applied to this terminal
with respect to ground (pin 1).

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Laboratory Session-2
Write-upon Logic design components, pin diagram (if any), Timing diagrams, etc. The
same information is also taught in theory class; this helps the students to understand
better.
Logic gates are electronic circuits that operate on one or more input signals to
produce an output signal. The gates are blocks of hardware that produces the equivalent of
logic 1 or logic 0 output signals if input logic requirements are satisfied. Gate INPUTS are
driven by voltages having two nominal values, e.g. 0V and 5V representing logic 0 and logic
1 respectively. The OUTPUTS of a gate provides two nominal values of voltage only, e.g. 0V
and 5V representing logic 0 and logic 1 respectively. There is always a time delay between an
input being applied and the output responding. The different types of logic gates are as
follows:
1. NOT GATE: It has one input and one output. The output is the complement of the input.
2. OR GATE: The gate has two inputs and one output. The output is logic „1‟ when either
of the inputs or both the inputs are at logic‟1‟.
3. AND GATE: The gate has two inputs and one output. The output is logic „1‟ only when
both the inputs are high.
4. NAND GATE: It is an AND gate followed by a NOT gate. It is the complement of AND
gate. The output is logic „0‟ when both the inputs are at logic „1‟, else the output is
always in the high state.
5. NOR GATE: It is an OR gate followed by a NOT gate. It is the complement of
OR gate. The output is logic „1‟ when both the inputs are at logic „0‟, else the output is
always in the low state.
6. EXOR GATE: It is logic gate whose output is in the high state when both the inputs are
not same. When the both the inputs are high and when both are low, the output is low.
7. EX-NOR GATE: It is logic gate whose output is in the high state when the both the
inputs are high and when both are low .The output is low when both the inputs are not
same.

PROCEDURE:
1. Place the IC in the socket of the trainer kit.
2. Make the connections for the gate as shown in the circuit diagram.
3. Verify the Truth Table.
4. Repeat the above steps for other gates in the different IC chips.

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(1) Implementation of Logic Gates

1. NOT Gate: - [IC7404]

2. OR Gate: - [IC7432]

3. AND GATE: - [IC7408]

4. NAND GATE: - [IC7400]

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5. NOR GATE:-[IC 7402]

6. XOR GATE: - [IC 7486]

7. EX-NOR GATE: - [IC4077]

Implementation of Basic Gates Using Universal Gates

Theory: NAND and NOR gates are called as universal gates because all the other basic gates
can be realized using only NAND or NOR gates

Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections for the gate as shown in the circuit diagram.
3. Verify the Truth Table.
Repeat the above steps for other gates in the different IC chips.

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NAND GATE AS:

1) AND GATE

2) OR GATE

3) NOT GATE

4) NOR GATE

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5) EX-OR GATE

6) EX-NOR GATE

NOR GATE AS:

 AND GATE

 OR GATE

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 NOT GATE

 NAND GATE

 EX-OR GATE

 EX-NOR GATE

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Experiment No.1a
To design and implement a Schmitt trigger using Op-Amp for given UTP
and LTP values & demonstrate its working.

Description:
Schmitt Trigger converts an irregular shaped waveform to a square wave or pulse. Here, the
input voltage triggers the output voltage every time it exceeds certain voltage levels called
the upper threshold voltage UTP and lower threshold voltage LTP. The input voltage is
applied to the inverting input. Because the feedback voltage is aiding the input voltage, the
feedback is positive. A comparator using positive feedback is usually called a Schmitt
Trigger. Schmitt Trigger is used as a squaring circuit, in digital circuitry, amplitude
comparator, etc.
Open loop gain of op amp is very high (ideally infinite).Any small difference between VNI
and VINV results into saturation of output voltage ±VSAT .Value of VSAT is limited by the
supply voltage of op amp.
Components Required:
Op amp IC µA 741, Resistor of 10KΩ, 110KΩ, DC regulated power Supply, trainer kit
(+12v & -12v is given to Op amp from this),Signal generator, CRO.
Design:
From theory of Schmitt trigger circuit using op-amp, we have the trip
points UTP= R2*Vref / (R1+R2) + R1*Vsat/(R1+R2) LTP= R2*Vref /
(R1+R2) - R1*Vsat/(R1+R2)
Where Vsat is the positive saturation of the opamp=90% of vcc
Hence given the LTP and UTP values to find the R1, R2 & Vref values the
following design is used
UTP + LTP= 2R2*Vref / (R1+R2)-------(1)
UTP – LTP = 2R1*Vsat/(R1+R2)--------(2)
Let Vsat=12v, UTP=4v and LTP =2v then eq(2) yields
R2=11R1 From Eq(1) we have Vref=(UTP+LTP)(R1+R2) /
2R2= 3.27v
Let R1=10k then R2= 110k

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Circuit Diagram for Schmitt Trigger

Procedure:
1. Before doing the connections, check all the components using multimeter.
2. Make the connection as shown in circuit diagram.
3. Using a signal generator apply the sinusoidal input waveform of peak-to-peak
amplitude of 10V, frequency 1kHz.
4. Keep the CRO in dual mode; apply input(Vin) signal to the channel 1 and observe
the output (Vo) on channel 2 which is as shown in the waveform below. Note the
amplitude levels from the waveforms
5. Now keep CRO in X-Y mode and observe the hysteresis curve.

Result waveform:

Hysteresis curve-

CRO in X-Y mode showing the Hysteresis curve

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Experiment No.1b
To implement a Schmitt trigger using Op-Amp using a simulation package
for two sets of UTP and LTP values & demonstrate its working.
Components to be placed in the schematic:
IC uA 741, Resistor of 10KΩ, 110KΩ, DC regulated power supply, Signal
generator, CRO

Type of analysis: TIME DOMAIN (TRANSIENT)

Run to time: 100msec
Step size: 0.1msec, UTP=4v LTP=2v Vref=3.3v

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Experiment No.2a
Design and construct a rectangular waveform generator (op-amp
relaxation Oscillator) for given frequency and demonstrate its
working

Description:
Op-Amp Relaxation Oscillator is a simple Square wave generator which is also called as a
Free running oscillator or Astable multivibrator or Relaxation oscillator. In this figure the
op-amp operates in the saturation region. Here, a fraction (R1/ (R1+R2)) of output is fed
back to the noninverting input terminal. Thus reference voltage is (R1/ (R1+R2)) Vo. And
may take values as + (R1/ (R1+R2)) Vsat or - (R1/ (R1+R2)) Vsat. The output is also fed
back to the inverting input terminal after integrating by means of a low-pass RC
combination. Thus whenever the voltage at inverting input terminal just exceeds reference
voltage, switching takes place resulting in a square wave output.

Components Required:
Op-amp μA 741, Resistor of 10KΩ,4.7KΩ, Capacitor of 0.1 μF, digital, trainer kit (+12v & -
12v is given to Op amp from this), CRO.

Circuit Diagram:

Design:
The period of the output rectangular wave is given as T =2RC ln (1+β/1- β ) ------- 1
Where,
β =R1/R1+ R2 is the feedback fraction
If R1 = R2, then from equation (1) we have T = 2RC ln(3) -------- 2
Design for a frequency of 1 kHz (implies T=1ms ) Let C=0.1μF

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Then calculating R as R=T/2 Cln(3) =1*10-3/2*0.1*10-6 * 1.099 = 5*103= 5K Select

R=4.7KΩ
The voltage across the capacitor has a peak voltage of Vc =(R1/R1+ R2) Vsat

Procedure:
1. Before making the connections check all the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
2. Observe the voltage waveform across the capacitor on CRO.
3. Also observe the output waveform on CRO. Measure its amplitude and frequency.

Waveforms:

Result:

The frequency of the oscillations = Hz.

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Experiment No.2b
To implement a rectangular waveform generator (Op-Amp relaxation
oscillator) using a simulation package and observe the change in frequency
when all resistor values are doubled.

Waveforms from simulation T= 1ms f=1khz

Run to time: 10ms , Step size: 0.01ms

Waveforms with resistor values doubled

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Experiment No.3
To design and implement an astable multivibrator using 555 Timer for a
given frequency and duty cycle.
Description:
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output
waveform is rectangular. The multivibrators are classified as
1. Astable or free running multivibrator It alternates automatically between
two states (low and high for a rectangular output) and remains in each state for
a time dependent upon the circuit constants. It is just an oscillator as it requires
no external pulse for its operation.
2. Monostable or one shot multivibrators: It has one stable state and one quasi
stable. The application of an input pulse triggers the circuit time constants and
the output goes to the quazi stable state, after a period of time determined by
the time constant, the circuit returns to its initial stable state. The process is
repeated upon the application of each trigger pulse.
3. Bistable Multivibrators: It has both stable states. It requires the application of
an external triggering pulse to change the output from one state to other. After
the output has changed its state, it remains in that state until the application of
next trigger pulse. Flip flop is an example.

Components Required:
555 Timer IC, Resistors of 3.3KΩ, 6.8KΩ, Capacitors of 0.1 μF, 0.01 μF, digital
trainer kit(used to give +5v power supply to 555 IC),CRO.

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Design:
Frequency = 1 kHz and duty cycle =75%, RA = 7.2kΩ & RB =3.6kΩ,
Duty cycle = tH / T = 0.75. Hence tH = 0.75T = 0.75ms and tL = T – tH =
0.25ms. Let C=0.1μF and substituting in the above equations,
So RB= tL/0.693 x C =0.25 x 10-3/0.693 x .1x10-
6=3.6kΩ RA = (tH - 0.693 x RB x C) /0.693 x C
= 0.75 x 10-3 x 0.693 x 3.6 x 103 x 0.1x 10-6 / 0.693 x .1x10-
6=7.2kΩ Choose RA = 6.8kΩ and RB = 3.3kΩ.
Note:
The duty cycle determined by RA & RB can vary only between 50 & 100%. If
RA is much smaller than RB, the duty cycle approaches 50%.

Circuit Diagram:

Connect the pin 2 to the CRO to get the capacitor waveform check the amplitude
from the waveform to get the UTP and LTP values.
Connect pin 3 to CRO to get the output. Find out the TH and TL values.
Procedure:
1. Before making the connections, check the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
th
3. Observe the capacitor voltage waveform at 6 pin of 555 timer on CRO.
rd
4. Observe the output waveform at 3 pin of 555 timer on CRO (shown below).
5. Note down the amplitude levels, time period and hence calculate duty
cycle.
Example:

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Given frequency (f) = 1KHz and duty cycle = 60%

(=0.6) The time period T =1/f = 1ms = tH + tL
Where tH is the time the output is high and tL is the time the output is low.
For an astable multivibrator using 555 Timer we have
tL = 0.693 RB C ------(1)
tH = 0.693 (RA + RB)C --
----(2) T = tH + tL = 0.693 (RA +2 RB) C
Duty cycle = tH / T = 0.6. Hence tH = 0.6 T = 0.6ms and tL = T – tH = 0.4ms.
Let C=0.1μF and substituting in the above equations

Result:
The frequency of the oscillations = 1KHz.

Waveforms:

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Note:
Each division in oscilloscope is 0.2 Time=no of div in x-axis x
time base Amplitude= no of div in y-axis x volt/div Duty cycle=(Ton/Ton +Toff) *100

Duty cycle Duty cycle Ton Toff

Theoretical 75% 0.75ms 0.25ms
Practical

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Experiment No 4.
Design and implement Half adder, Full Adder, Half Subtractor, Full
Subtractor using basic gates.
Components required:

Sl.No Name of The IC Quantity

Component Num
ber
1 AND gate 7408 1
2 OR gate 7432 1
3 Not gate 7404 1
4 EXOR gate 7486 3
5 NAND gate 7400 3
6 NOR gate 7402 3
7 Patch chords
8 Trainer Kit

Theory:

Half adder:
A half adder has two inputs for the two bits to be added and two outputs one from the
sum „ S‟ and other from the carry „ c‟ into the higher adder position. Above circuit is called as
a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry
out from the AND gate.

Full adder:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a
half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output
will be taken from OR Gate.

Half subtractor:
The half subtractor is constructed using X-OR and AND Gate. The half
subtractor has two input and two outputs. The outputs are difference and borrow. The
difference can be applied using X-OR Gate, borrow output can be implemented using
an AND Gate and an inverter.

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Full subtractor:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together gives a full subtractor .The first half subtractor will be C and A
B. The output will be difference output of full subtractor. The expression AB
assembles the borrow output of the half subtractor and the second term is the inverted
difference output of first X-OR.

Logic diagram:

Half adder truth table:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM K-Map for CARRY

SUM = A’B + AB’ CARRY = AB

Full adder

Logic diagram:

Full adder using two half adder

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Truth table:

A B C CARRY SUM

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

K-Map for SUM: K-Map for CARRY:

SUM = A’B’C + A’BC’ + ABC’ + ABC CARRY = AB + BC + AC

Logic diagram:
Half subtractor

Truth table:

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DIFFERENC
A B BORROW E

0 0 0 0

0 1 1 1

1 0 0 1

1 1 0 0

K-Map for DIFFERENCE: K-Map for BORROW:

DIFFERENCE = A’B + AB’ BORROW = A’B

Logic diagram:

Full subtractor

Full subtractor using two half subtractor:

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Truth table:

A B C BORROW DIFFERENCE

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

K-Map for Difference: K-Map for Borrow

Difference = A’B’C + A’BC’ + AB’C’ + ABC Borrow = A’B + BC + A’C

Procedure:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

Result:

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Experiment No.5a
Given any 4-variable logic expression, simplify using Entered Variable
Map and realize the simplified logic expression using 8:1 multiplexer IC.

Description:
The term multiplex means “many to one”. A multiplexer (MUX) has n inputs.
Each line is used to shift digital data serially. There is a single output line. One of the
data stored in the n input line is transferred to the output based on the valued of
control bits. An n to 1 multiplexer requires m control bits where n<=2m.
To construct an 4 variable function we require a 16(i.e., 24) to 1 multiplexer, whereas
using an entered variable map method a 4 variable expression can be realized using
8(i.e.,23) to 1 multiplexer

Components Used:

Sl. No. Equipments and Components Quantity

1 Trainer Kit 1
2 IC 74151 (8:1 MUX) 1
3 IC 7404 (NOT Gate) 1
4 Patch Cords 1 Bunch

Pin Diagrams: IC 74LS151

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Example:
Simplify the following function using EVM technique
f(a,b,c,d)=∑m(2,3,4,5,13,15)+dc(8,9,10,11)

MEV map
Decimal ABCD f Data
entry
0 0000 0
0 Do
1 0001 0
2 0010 1
1 D1
3 0011 1
4 0100 1
1 D2
5 0101 1
6 0110 0
0 D3
7 0111 0
8 1000 X
X D4
9 1001 X
10 1010 X
X D5
11 1011 X
12 1100 0
D D6
13 1101 1
14 1110 0
D D7
15 1111 1

Circuit Diagram

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Procedure:
1. Verify all components & patch chords whether they are in good condition or not.
2. Make connections as shown in the circuit diagram.
3. Give supply to the trainer kit.
4. Provide input data to circuit via switches
5. Verify truth table sequence & observe outputs.

Result:
The truth table is verified.

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Experiment No.5b
Write the verilog /VHDL code for 8:1 MULTIPLEXER. Simulate and
verify its working.
Truth table for 8:1 Multiplexer:

Inputs Output
sel (2) sel(1) sel(0) Y
0 0 0 D(0)
0 0 1 D(1)
0 1 0 D(2)
0 1 1 D(3)
1 0 0 D(4)
1 0 1 D(5)
1 1 0 D(6)
1 1 1 D(7)

VHDL code for 8:1 Multiplexer (Behavioral modeling):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8to1 is
Port( D:in std_logic_vector(7 downto 0);
sel: in std_logic_vector(2 downto 0);
Y: out std_logic);
end mux8to1;
architectural Behavioral of mux8to1 is
begin
Y<=D(0) when sel=”000” else
D(1) when sel=”001” else
D(2) when sel=”010” else
D(3) when sel=”011” else
D(4) when sel=”100” else
D(5) when sel=”101” else
D(6) when sel=”110” else
D(7);
end Behavioral;

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Output:

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Experiment No 6.
Design and implement code converter I) Binary to Gray II) Gray to Binary
Code using basic gates.

Description:
Gray Code is one of the most important codes. It is a non-weighted code which
belongs to a class of codes called minimum change codes. In this codes while
traversing from one step to another step only one bit in the code group changes. In case
of Gray Code two adjacent code numbers differs from each other by only one bit.
Binary to gray code conversion is a very simple process. There are several steps to do
this types of conversions.
Steps given below elaborate on the idea on this type of conversion.
1. The M.S.B. of the gray code will be exactly equal to the first bit of the given
binary number.
2. Now the second bit of the code will be exclusive-or of the first and second bit
of the given binary number, i.e if both the bits are same the result will be 0 and
if they are different the result will be 1.
3. The third bit of gray code will be equal to the exclusive-or of the second and
third bit of the given binary number. Thus the Binary to gray code conversion
goes on. One example given below can make your idea clear on this type of
conversion.

Gray code to binary conversion is again very simple and easy process. Following
steps can make your idea clear on this type of conversions.
1. The M.S.B of the binary number will be equal to the M.S.B of the given gray code. Now
if the second gray bit is 0 the second binary bit will be same as the previous or the first
bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and if it was
0 it will be 1.

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2. This step is continued for all the bits to do Gray code to binary conversion. One
example given below will make your idea clear.

Equipment and components required:

Sl. No. Equipment and Components Quantity

1 Trainer Kit 1
2 IC 7486 (XOR Gate) 1
4 IC 7408 (AND Gate) 2
5 IC 7432 (OR Gate) 1
6 IC 7404 (NOT Gate) 2
7 Patch cords 1 bunch

To Convert Binary to Gray code:

Truth table:

Inputs Outputs
B1 B2 B3 B4 G1 G2 G3 G4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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K-Map for G1:

B3B4
B1B2
00 01 11 10

00 0 0
0 0

G1=B1
01 0 0 0 0

11 1 1 1 1

10 1 1 1 1

K-Map for G2:

B3B4
B1B2
00 01 11 10

00 0 0
0 0
G2=B1B2+B1B2
G2=B1 + B2
01 1 1 1 1

11 0 0 0 0

10 1 1 1 1

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K-Map for G3:

B3B4
B1B2
00 01 11 10

00 0 1 1
0
G3=B2B3+B2B3
01 1 1 0 0 G3=B2 + B3

1 1 0 0
11

10
0 0 1 1

K-Map for G4:

B3B4
B1B2
00 01 11 10

00 0 0 1
1
G4=B3B4+B3B4
01 0 1 0 1 G4=B3 + B4

0 1 0
11 1

10 0 1 0 1

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Realization of Binary to Gray code conversion using XOR Gates:

B1 B2 B3 B4

G1

G2

G3

G4

Realization of Binary to Gray code conversion using Basic Gates:

B1 B2 B3 B4
G1

G2

G3

G4

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Procedure:

(i) Connect the circuit as per design.

(ii) Apply the input combination and verify the truth table.

To convert Gray code to Binary:

Truth Table:

Inputs Outputs
G1 G2 G3 G4 B1 B2 B3 B4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

K-Map for B1:

GG
G1G2 3 4
00 01 11 10

00 0 0
0 0

B1=G1
01 0 0 0 0

11 1 1 1 1

10 1 1 1 1

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K-Map for B2:

GG
G1G2 3 4
00 01 11 10

00 0 0 B2=G1G2+G1G2
0 0

B2=G1 + G2
01 1 1 1 1

11 0 0 0 0

10 1 1 1 1

K-map for B3:

GG
G1G2 3 4
00 01 11 10

00 0 1 1
0

B3=G1 + G2 + G3
01 1 1 0 0

0 0
11 1 1

10 1 1 0 0

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K-Map for B4:

GG
G1G2 3 4
00 01 11 10

00 0 1 0 1

01 1 0 0
1
B4=G1 + G2 + G3 + G4
0 0
11 1 1

10 1 0 1 0

Realization of Gray code to Binary using XOR gates:

G1 B1

G2 B2

G3 B3

G4 B4

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Realization of Gray code to Binary code using Basic Gates:

G1 G2 G3 G4

B1

B2

B3

B4

Procedure:
(i) Connect the circuit as per design.
(ii) Apply the input combination and verify the truth table.

Result:
Binary to gray code conversion and vice versa is realized using EX-OR gates.

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Experiment No 7.
Design and verify the Truth Table of 3-bit Parity Generator and 4-bit
Parity Checker using basic Logic Gates with an even parity bit.

Description:
The parity generating technique is one of the most widely used error detection techniques
for the data transmission. In digital systems, when binary data is transmitted and processed,
data may be subjected to noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s.
Hence, parity bit is added to the word containing data in order to make number of 1s
either even or odd. Thus it is used to detect errors , during the transmission of binary data.
The message containing the data bits along with parity bit is transmitted from transmitter
node to receiver node.
 Parity Generator:
It is combinational circuit that accepts an n-1 bit stream data and generates the
additional bit that is to be transmitted with the bit stream. This additional or extra bit is
termed as a parity bit.
In even parity bit scheme, the parity bit is “0” if there are even number of 1s in the data
stream and the parity bit is “1” if there are odd number of 1s in the data stream.
Even Parity Generator- Let us assume that a 3-bit message is to be transmitted with an even
parity bit. Let the three inputs A, B and C are applied to the circuits and output bit is the
parity bit P. The total number of 1s must be even, to generate the even parity bit P.
 Parity Checker
It is a logic circuit that checks for possible errors in the transmission. This circuit can
be an even parity checker or odd parity checker depending on the type of parity generated at
the transmission end. When this circuit is used as even parity checker, the number of input
bits must always be even. When a parity error occurs, the „sum even‟ output goes low and
„sum odd‟ output goes high. If this logic circuit is used as an odd parity checker, the number
of input bits should be odd, but if an error occurs the „sum odd‟ output goes low and „sum
even‟ output goes high.
Even Parity Checker-Consider that three input message along with even parity bit is
generated at the transmitting end. These 4 bits are applied as input to the parity checker circuit
which checks the possibility of error on the data. Since the data is transmitted with even
parity, four bits received at circuit must have an even number of 1s.

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If any error occurs, the received message consists of odd number of 1s. The output of
the parity checker is denoted by PEC (parity error check).

3-bit Parity Generator:

Truth Table for 3-bit Parity Generator:

3-bit message Even parity bit generator

A B C P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

K-Map Simplification for P:

A BC
00 01 11 10

P=ABC+ABC+ABC+ABC
0 0 1
1 0 P=A + B + C

1
1 0 1 0

Realization 3-bit parity generator with XOR gates:

A B C

P=A + B + C

Realization 3-bit parity generator with Basic gates:

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A B C

P=A + B + C

4-bit Parity Checker:

Truth table for 4-bit Parity Checker:

4-bit received message Parity error

A B C P check(CP)
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

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K-Map Simplification for CP:

AB CP
00 01 11 10

00 0 1 1
0

01 1 0 1 0
CP=(A + B) + (C + P)

11 0 1 0 1

10 1 0 1 0

Realization of 4-bit parity checker using XOR gates:

A
B
CP
C
P

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Realization of 4-bit parity checker using Basic gates:

A B C P

CP

Procedure:
(i) Connect the circuit as per design.
(ii) Apply the input combination and verify the truth table.

Result:
3 bit parity generator and 4 bit parity checker is verified.

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Experiment No.8a:
Realize a J-K Master/Slave FF using NAND gates and verify its truth table.

Description:
A flip-flop is a device very much like a latch in that it is a bistable multivibrator,
having two states and a feedback path that allows it to store a bit of information. The
difference between a latch and a flip-flop is that a latch is asynchronous, and the
outputs can change as soon as the inputs do (or at least after a small propagation
delay). A flip-flop, on the other hand, is edge-triggered and only changes state when a
control signal goes from high to low or low to high.
Master Slave Flip Flop:
The control inputs to a clocked flip flop will be making a transition at
approximately the same times as triggering edge of the clock input occurs. This can
lead to unpredictable triggering.
A JK master flip flop is positive edge triggered, whereas slave is negative edge
triggered. Therefore master first responds to J and K inputs and then slave. If J=0 and
K=1, master resets on arrival of positive clock edge. High output of the master drives
the K input of the slave. For the trailing edge of the clock pulse the slave is forced to
reset. If both the inputs are high, it changes the state or toggles on the arrival of the
positive clock edge and the slave toggles on the negative clock edge. The slave does
exactly what the master does.

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Equipment and Components required:

SL No. Equipments and Components Quantity

1 IC Trainer Kit 1
2 IC 7400 (2 input NAND Gate) 2
3 IC 7410 (3 input NAND Gate) 1
4 Patch Cord 1 Bunch

Truth table
J K Q
0 0 No Change
0 1 0
1 0 1
1 1 Toggle

Circuit Diagram:

J 7410
7400 7400
7400 Q

CLK

7400 Q
7400
7400
K 7410

7400
7400

Procedure:
(i) Connect the circuit as shown in the above diagram.
(ii) Apply the input combination and verify the truth table.

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Experiment No.8b
Write the verilog/ VHDL code for D Flip-Flop with positive- edge
triggering. Simulate and verify its working.
Description:
D- flip flop is a data flip flop the truth table summarizes the operation of the D – flip flop. It
has a single input D and two output Q and Q‟

Truth Table:

Clock(CLK) D Q
1 0 0
2 1 1
3 0 0
4 1 1

VHDL code for D Flip Flop (Behavioral modeling):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dflipflop is
Port( D,CLK : in std_logic;
Q: inout std_logic;
QBAR: inout std_logic);
end dflipflop;
architectural Behavioral of dflipflop is
begin
process(CLK) is
begin

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if rising_edge(CLK) then
Q<=D;
end if;
end process;
QBAR<= not Q;
end Behavioral;

Result:

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Experiment No.9a
Design and implement a mod n (n<8) synchronous up counter using JK
Flip Flop ICs and demonstrate its working.
Description:
The ripple counter requires a finite amount of time for each flip flop to change state. This
problem can be solved by using a synchronous parallel counter where every flip flop is
triggered in synchronism with the clock, and all the output which are scheduled to change do
so simultaneously.
The counter progresses counting upwards in a natural binary sequence from count 000 to
count 100 advancing count with every negative clock transition and get back to 000 after this
cycle.

Pin Diagrams:74LS76

IC: 7408

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Component and Equipment required:

Sl. No. Component Quantity

1 IC Trainer Kit 1
2 IC 7476 (JK Flip Flop IC) 1
3 IC 7408 (AND Gate IC) 1
4 Patch Cord 1 Bunch

Function Table:

PR CLR CLK J K Q Q’
L H X X X H L
H L X X X L H
L L X X X H H
H H L L Q0 Q0’

H H H L H L

H H L H L H

H H H H Toggle

Transition Table:

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

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Procedure:
1. Verify all the components and patch cords for good working condition.
2. Make connection as shown in the circuit diagram.
3. Give supply to the trainer kit
4. Provide input data to circuit via switches and verify the truth table.

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Experiment No.9b
Write the verilog/ VHDL code for mod-8 up counter. Simulate and verify
its working.

Truth Table:

Clock (CLK) R E Q
0 1 0 0000
1 0 1 0001
2 0 1 0010
3 0 1 0011
4 0 1 0100
5 0 1 0101
6 0 1 0110
7 0 1 0111
8 0 1 0000

VHDL code for Mod-8 counter (Behavioral modeling):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mod8upcounter is
Port( R,CLK,E : in std_logic;
Q: inout std_logic_vector(3 downto 0));
end mod8upcounter;
architectural Behavioral of mod8upcounter is
begin
process(CLK,R) is
begin
if R=‟1‟ then Q<=”0000”;
else if rising_edge(CLK) then
if E=‟1‟ then
Q<=Q+1;
end if;

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if Q=”0111” then
Q<=”0000”
end if;
end if:
end if;
end process;
end Behavioral;

Result:

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Experiment No.10
Design and implement asynchronous counter using decade counter IC to
count up from 0 to n (n≤9) and demonstrate on seven segment display
(using IC-7447).

Description:
Asynchronous counter is a counter in which the clock signal is connected to the
clock input of only first stage flip flop. The clock input of the second stage flip flop is
triggered by the output of the first stage flip flop and so on. This introduces an inherent
propagation delay time through a flip flop. A transition of input clock pulse and a transition
of the output of a flip flop can never occur exactly at the same time. Therefore, the two flip
flops are never simultaneously triggered, which results in asynchronous counter operation.

Components and Equipment required:

Sl. No. Component Quantity

1 IC Trainer Kit 1
2 IC 7490 (Decade counter IC) 1
3 IC 7447 (Decoder IC) 1
4 IC 7410 (3 input NAND Gate) 1
5 DRB 1
6 7-Segment Display 1
7 Patch Cord 1 Bunch

Pin Diagrams: 7480 and 7447

Design and implementation:

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Count up from 0 to 9:

Clock Counter Output ( IC7490) Decimal Output

Q3 Q2 Q1 Q0 (7-Segment Display)
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 1 0 0 0 8
9 1 0 0 1 9
10 0 0 0 0 0

MOD 10
VCC

VCC 1KΩ

1 5 12 7 16 a 3 or 8
13 7
CLK 14 9 b a
1 12 6
2 c f b
8 2 7447 11 4
GND 3 7490 g
d 2
6 11 6 10
e
GND LT 3 9 1 e c
7 f 9
4
BI/BRO 4 15 d
NC g
RBI 5 14 10
NC 13 10 8 5 Open

7-segment Display
GND GND

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Count from 0 to 7:

Clock Counter Output ( IC7490) Decimal

Q3 Q2 Q1 Q0 Output
(7-Segment
Display)
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 0 0 0 0 0

VCC
MOD 8
VCC
1K

1 5 12 7 16 a 3 or 8
13 7
CLK 14 9 b a
1 12 6
2 c f b
8 2 7447 11 4
3 7490 g
d 2
6 11 6 10
e
GND LT 3 9 1 e c
7 f 9
BI/BRO 4 15 d
NC 4 g
RBI 5 14 10
NC 13 10 8 5 Open

7-segment Display
GND GND

Procedure:
(i) Connect the circuit as shown in the above diagram.
(ii) Apply the input combination and verify the truth table.

Note:

 LT stands for Lamp Test. When LT is low, all the segments on the 7-segment display
are lit regardless of DCBA.

 BI stands for Blanking Input. When BI is low, the display is blank so all the segments
on the 7-segment display are off regardless of DCBA.

 RBI stands Ripple Blanking Input. When RBI is low and DCBA=0000 the display is
blank otherwise the number is displayed on the display. This is used to remove leading
zeroes from a number.

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Experiment No.11
Generate a Ramp output waveform using DAC0800(Inputs are given to
DAC through IC74393 dual 4-bit binary counter).
Description:

DAC 0800:
 To convert the digital signal to analog signal a Digital-to-Analog Converter (DAC) has
to be employed.

 The DAC will accept a digital (binary) input and convert to analog voltage or current.
 Every DAC will have "n" input lines and an analog output.
 The DAC require a reference analog voltage (Vref) or current (Iref) source.
 The smallest possible analog value that can be represented by the n-bit binary code is
called resolution.
 The resolution of DAC with n-bit binary input is 1/2n of reference analog value.
 Every analog output will be a multiple of the resolution.
 The DAC0800 require a positive and a negative supply voltage in the range of ± 5V to
±18V.
 It can be directly interfaced with TTL, CMOS, PMOS and other logic families.
 For TTL input, the threshold pin should be tied to ground (VLC = 0V).
 The reference voltage and the digital input will decide the analog output current, which
can be converted to a voltage by simply connecting a resistor to output terminal or by
using an op-amp I to V converter.

Equipments and components required:

Sl. No. Equipments and components Quantity

1 IC Trainer Kit 1
2 CRO 1
3 DAC0800 (Digital to Analog Converter IC) 1
4 IC 74393 (Dual 4-bit binary counter) 1
5 IC 7421 (4 input AND Gate) 1
6 Resistors:5KΩ 2
7 Resistor: 10KΩ 1
8 Capacitor: 0.1μf and 0.01μf 2
9 Patch Cord 1 Bunch

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Design and implementation:

Circuit Diagram:

+12v

VCC -12v
0.1μf CRO
2 12 3 13
14
4
1 8 5
CLK B1 10K
9 6
B2
1 5K
10 7 14
B3 +5V
2 6 13
74393 11 8
7421 B4 DAC0800
4
7 6 9 5K
B5 15
5
5 10
B6 16
4 11
B7
3 12
B8
0.01μf
1 2

Procedure:
(i) Connect the circuit as shown.
(ii) Apply the input clock pulse.
(iii) Observe the waveform at CRO

Waveform:
Voltage

Time

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Study experiment
Experiment No 12
To study 4-bitALU using IC-74181.

Description:
ALU stands for the arithmetic and logical unit and is one of the important unit in
almost all the calculating machine these days be it with the hand-held mobile, or computers.
All the computational work in the system are carried out by this unit. The typical ALU sizes
are: 4-bit ALU: ALU that processes two 4-bit numbers.8-bit ALU: ALU that processes two
8-bit numbers. Still in the latest systems ALU sizes are 16, 32, 64-bit etc.Figure-12.1 shows
the block diagram of a typical ALU.


Figure-12.1: Block Diagram of ALU

In figure-12.1, the 1x2 selector on the left is as a mode selector to select one of the two units
i.e. either the arithmetic unit or the logical unit. The function select lines are then used to
select one of the many functions of arithmetic or the logical type.

MSI package for ALU:- IC 74181 a 4-bit Arithmetic and logical unit:

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Figure-12.2: Pin Diagram of IC 74181 ALU

Figure-12.3: Internal Architecture of IC 74181

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Function of ALU as seen from figure 12.3:

1. The ALU has two 4-bit input lines A3-A0, B3-B0, and a 4-bit function select
lines S3-S0.
2. One mode select line „M‟ that is used to select ALU for either arithmetic or the
logical function.
3. It has four output lines f3-f0.
4. Carry-in Cn is used in cascade mode.
5. When the size is to be increased to 8-bit operations two 74181 can be cascaded and
Cn+4 will be used as input to Cn line of next stage.

The function table of IC 74181 ALU is given in figure-12.5. It shows the functions
selected depending on the Cn, M and S3-S0 lines.

Equipment Required:
IC 74181 ,LEDs, Power Supply, CRO, Multimeter

Circuit diagram:
LEDs are connected at the input A and B lines and the select lines to indicate
the value of the inputs A and B. The LEDs at the select lines are used to specify the

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function of the ALU. The LEDs at the output are used to test and verify the output. The
whole implementation is shown in figure 12.6

Figure-12.6: implementation of ALU

with IC 74181

Procedure:
1. Keep the datasheet of IC 74181 ready.
2. Insert the IC on the Breadboard.
3. Make connections as shown in figure-12.6
4. Verify the connections

Result:
The above circuit when connected to power supply gives correct result as per
the function table.

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Sample Viva Questions

1. Why operational amplifier is called by its name?
2. Explain the advantages of OPAMP over transistor amplifiers.
3. List the OPAMP ideal characteristics.
4. Give the symbol of OPAMP
5. Explain the various applications of OPAMP
6. Define UTP and LTP
7. Mention the applications of schmitt trigger
8. What is a square wave generator/ Regenerative comparator?
9. Give the hysterisis curve of a schmitt trigger
10. What is a bipolar and unipolar devices? Give examples
11. Define resolution
12. Explain the need of D/A and A/D converters.
13. List the different types of A/D and D/ A converters
14. What is a multivibrators?
15. What is a bistable multivibrators?
16. Give the applications of monostable and astable multivibrators
17. Explain the working of 555 timer as astable and monostable multivibrator
18. Why astable multivibrator is called as free running multivibrato
19. Define duty cycle.
20. List the applications of 555 timer
21. Explain 555 timer as astable multivibrator to generate a rectangular
wave of duty cycle of less than 0.5
22. Define a logic gate.
23. What are basic gates?
24. Why NAND and NOR gates are called as universal gates?
25. State De morgans theorem
26. Give examples for SOP and POS
27. Explain how transistor can be used as NOT gate
28. Realize logic gates using NAND and NOR gates only
29. List the applications of EX-OR and EX~NOR gates
30. What is a half adder?

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31. What is a full adder?

32. Differentiate between combinational and sequential circuits. Give examples
33. Give the applications of combinational and sequential circuits
34. Define flip flop
35. What is an excitation table?
36. What is race around condition?
37. How do you eliminate race around condition?
38. What is minterm an d max term?
39. Define multiplexer/ data selector
40. What is a demultiplexer?
41. Give the applications of mux and demux
42. What is a encoder and decoder?
43. Compare mux and encoder
44. Compare demux and decoder
45. What is a priority encoder?
46. What are counters? Give their applications.
47. Compare synchronous and asynchronous counters
48. What is modulus of a number?
49. What is a shift register?
50. What does LS stand for, in 74LSOO?
51. What is positive logic and negative logic?
52. What are code converters?
53. What is the necessity of code conversions?
54. What is gray code?
55. Realize the Boolean expressions for
a) Binary to gray code conversion
b) Gray tonbinary code conversion

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