The University of Zambia

School of Engineering

COURSE CODE: EEE 3132

COURSE TITLE: COMPUTER ENGINEERING
Course Instructors: Dr. Eng Lukumba Phiri, PhD
Eng AD Ngoyi
Tutors: Ms Muyanje & Mr. Sanga M
29th July, 2024
1
 Background

• Rationale:
• Due to the critical role computers are playing in today's society, it has
become imperative to train students in electrical engineering on
fundamentals, advanced concepts, and principles of computer
engineering. Nowadays, knowledge and understanding of computer
engineering have become skills that are sought-after by many
employers in both public and private sectors.
• Aim:
• This course aims at equipping students with knowledge and
understanding of concepts, analysis design, construction, principles of
operations, and characteristics of modern computer systems.

2
 Learning Objectives and Outcomes (1 of 2)

• After having learnt this course students will have acquired testable
knowledge and skills in the following fields:
1. When given a business problem, students will be able to analyze,
design, and develop a computer solution model.
2. When given a problem involving automation, students will be able
to analyze, design, and propose hardware and software solution
models.
3. When given a problem involving information processing, students
will be able to analyze, design, and propose hardware and software
platforms for an appropriate solution.
3
 Learning Objectives and Outcomes (2 of 2)
By the end of the 1. Understand techniques for measuring the performance
programme, the of computer systems and the limitations of these
graduate should techniques
be 2. Analyse the impact of a change made to a computer’s
able to: architectural design
3. Evaluate the effectiveness of the use of parallel
processing in different environments
4. Learn about methods for designing multiprocessor
systems

4
 Course Outline

1. Software
• Machine, assembly language programming. High-level languages,
structured programming, efficient programming. Program design
techniques. Timing Charts.
• Computer programming with an emphasis on C++ programming an
Object-Oriented Programming language: OOP principles, Inheritance,
Classes and Objects, Polymorphism, Separation of Interface and
Implementation; plus the introduction of generic programming and
C++ Templates.

5
 Course Outline

2. Classification of Processors
• Processor architecture; 8-bit processors, 16-bit processors. Memory
structures and technologies. Memory maps, standard I/O, memory
mapped I/O, block addressing SSCs.
3. Communications
• Communication protocols; handshaking, polling, interrupts, DMA. Serial
and parallel communication USART's, UART's, PPI's, DM¡ control.
Peripheral devices; keyboards, CRTs, printers, disk drives, MODEM's.

6
 Course Outline
4. System Development
Editing, linking, and location. Development systems and in-circuit emulation. Programming
languages; machine code, assembly, high-level language. Assemblers, interpreters, and
compilers. Data structures real, integer, floating point, characters excess-64, ASCII, Baudot.
Multiprogramming and multiprocessing. Semaphores and re-entrant codes.

5. Special Purpose Systems

Desktop computers, development systems, data loggers, introduction to PLCs, control
training systems. System software; monitor, operating, and multi-user. CP/M and DOS
structures, UNIX.

7
 Course Pre-requisite
Course Pre-requisite: Introduction to Information Technology (ENG 2139)

Time Allocation
Lectures 4 hours/ week
Laboratory/Tutorials 3 hours/week
Assessment:
Assignments/ Tutorials: 8-10 [5%]
Laboratories/Mini-Projects: 6-10 [15%]
Tests: 2 [20% ]
Final Examination: 60%

8
 Assessments
Continuous Assessment Weight
Assignments 5%
Tests 20%
Laboratory 15%
Final Examination 60%

9
 Prescribed Test
1. Short K.L., Microprocessors and Programmed Logic, 2nd Ed., 1997,
Prentice Hall IPE, ISBN 0-13-5806062.
2. Programming: Principles and Practice Using C++, 2nd Ed., 2014,
Paperback, ISBN-13: 978-0321992789 or ISBN-10: 0321992784
3. G. Buttazzo, Hard Real-Time Computer Systems: Predictable Scheduling
Algorithms and Applications, 3rd Ed., Springer, 2011
4. M. Wolf, Computers as Components:
5. Principles of Embedded Computing System Design, 4th Edition,
6. Morgan Kaufman/Elsevier Publishers 2016, ISBN 978-0-12-805387-4

10
 Prescribed Test
7. Daniel W. Lewis, Fundamental of Embedded Software with ARM Cortex M3,
2nd Edition, Pearson 2013, ISBN 978-0-13-291654-7
8. Z. Navabi, Embedded Core Design with FPGAs, McGraw-Hill, 2007, ISBN-13:
9780071474818 (ISBN-10: 0071474811)
9. D. C. Black, J. Donovan, B. Bunton & A. Keist, SystemC: From the Ground Up,
2nd Edition, 2010, ISBN 978-0-387-69958-5
10. F. Vahid & T. Givargis, Embedded System Design, 1st Edition John Wiley 2002,
ISBN 0-471-38678-2
11. Alan Burns and Andy Wellings, Real-time Systems & Programming Languages,
Addison-Wesley 2001, ISBN 0 201 72988 1
12. Embedded Processors and Micro-controllers Data Sheets are available at the
Course Website http://www.ecb.torontomu.ca/~courses/ee8205/

11
 Course Work - Scheme
Lecture Topic
1 Introduction to Computer Engineering
2 Introduction to Assembly Language
3 Implementing C Language Constructs

4 Input/Output
5 Embedded Bus Protocols
6 Time Sharing
7 Concurrency Basics

12
 Course Work - Scheme
Week Topic
8 Locks: a synchronization primitive to efficiently support mutual
exclusion
9 Condition Variables and Semaphores
10 Introduction to Real-Time Scheduling

11 Conventional Scheduling Algorithms

12 (Aperiodic) Real-Time Scheduling
Algorithms
13 Real-Time Scheduling Algorithms
for Periodic Tasks
14 Resource Access Protocols

13
 Conclusion

• The Course Computer Engineering will contribute to development of

highly skilled human resources for the digital communication industry
in the respective specialties of Computer Networking &
Communication System Engineering
• UNZA to maintain its leadership role in producing BEng level
graduates for the country and the region

14
Course Work - Scheme

15
 Introduction
EEE3132: Computer Engineering
Dr. Lukumba Phiri
[email protected]
Electrical and Electronic Engineering
University of Zambia
Overview
• Embedded Software Systems: Course Management
• Real-time and Embedded Systems
• Embedded System Applications
• Characteristics of Embedded Systems
Text by Wolf: part of Chapter 1, Text by Navabi: part of Chapters 8 and 9

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Course Text-Reference Books and other Material
• M. Wolf, Computers as Components:
Principles of Embedded Computing System Design, 4th Edition,
Morgan Kaufman/Elsevier Publishers 2016, ISBN 978-0-12-805387-4
• Daniel W. Lewis, Fundamental of Embedded Software with ARM Cortex M3,
2nd Edition, Pearson 2013, ISBN 978-0-13-291654-7
• Z. Navabi, Embedded Core Design with FPGAs, McGraw-Hill, 2007,
ISBN-13: 9780071474818 (ISBN-10: 0071474811)
• D. C. Black, J. Donovan, B. Bunton & A. Keist, SystemC: From the Ground
Up, 2nd Edition, 2010, ISBN 978-0-387-69958-5
• F. Vahid & T. Givargis, Embedded System Design, 1st Edition John Wiley
2002, ISBN 0-471-38678-2
• Alan Burns and Andy Wellings, Real-time Systems & Programming
Languages, Addison-Wesley 2001, ISBN 0 201 72988 1
Embedded Processors and Micro-controllers Data Sheets are available at the
Course Website http://www.ecb.torontomu.ca/~courses/ee8205/

In addition to the text/reference books, lectures may contain material from research articles
to be identified by the instructor.

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 Introduction
• What are Embedded Systems?
• Challenges in Embedded Computing System Design
• Design Methodologies
Main Aim of the Course
• To introduce embedded computer systems
▪ Software and hardware components of an embedded system
• To understand real-time operating systems
• Embedded Computer Architecture
• Hardware Software Codesign
Ideally Student should have the knowledge of:
• Basics of Programming C or C++ and Computer Architectures
• Introduction to Operating Systems

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 What is an Embedded/Real-time System?
Most real-time systems (RTS) are also embedded systems.
• An embedded system is an information processing system
that responds to externally generated input stimuli within a
finite and specified period.
▪ The correctness depends not only on the logical result but also
the time it was delivered
▪ Failure to respond is as bad as the wrong response!
• Embedded system: any device that includes a programmable
computer but is not itself a general-purpose computer.
• Take advantage of application characteristics to optimize the
design:

Don’t need all the general-purpose bells and whistles.

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 Embedding a Computer

Digital
Output Analog

Analog
Input
CPU Digital

Embedded Mem
Computer

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 Embedded Systems
• Electronic devices that incorporate a computer (usually a
microprocessor) within their implementation.
• A computer is used in such devices primarily as a means to
simplify the system design and to provide flexibility.
• Often the user of the device is not even aware that a
computer is present.
• Embedded Systems Rule the World
▪ Embedded processors account for 100% of worldwide
microprocessor production.
▪ Embedded:desktop = 100:1
▪ 99% of all processors are for the embedded systems market.
▪ Number of embedded processors in a typical home is
estimated at 50-60.
(A recent ACURA Model has more than 50 processors)
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 Embedded CPU Applications

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 Some Embedded and PC Systems

▪ Cell phones, PCs and

TVs manufactured
and shipped per year.
▪ More than 1 billion
cell phones shipped
in 2006 as compare
200 million PCs.
▪ A 2006 survey of
U.S. families found
that they owned on
average 12 gadgets

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 Early History of Embedded Systems
• First microprocessor was Intel 4004 in early 1970’s.
• HP-35 calculator used several chips to implement a
microprocessor in 1972.
• Automobiles used microprocessor-based engine
controllers starting in 1970’s.
▪ Control fuel/air mixture, engine timing, etc.
▪ Multiple modes of operation: warm-up, cruise, hill climbing, etc.
▪ Provides lower emissions, better fuel efficiency.
• Microcontroller: includes I/O devices, on-board memory.
• Digital signal processor (DSP): microprocessor optimized
for digital signal processing.
Typical embedded word sizes: 8-bit, 16-bit, and 32-bit.

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 A Typical Embedded System

Real- Engineering
Time
Algorithms for Interface
Clock Digital Control System

Data Logging Remote

Monitoring System

Database

Data Retrieval Display

and Display Devices

Operator Operator
Console Interface

Embedded Computer

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 Real Time Systems
• Real-time systems (RTS) process events.
• Events occurring on external inputs cause other events to
occur as outputs.
• Minimizing response time is usually a primary objective, or
otherwise the entire system may fail to operate properly.
Types of Real Time System
• Hard real-time — e.g. Flight control systems.
• Soft real-time — e.g. Data acquisition system.
• Real real-time — e.g. Missile guidance system.
• Firm real-time

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 Types of Real Time System
• Hard real-time — systems where it is absolutely imperative that
responses occur within the required deadline.
For example: Flight control systems.
• Soft real-time — systems where deadlines are important, but
which will still function correctly if deadlines are occasionally
missed. For example: Data acquisition system.
• Real real-time — systems which are hard real-time and which
the response times are very short.
For example: Missile guidance system.
• Firm real-time — systems which are soft real-time but in which
there is no benefit from late delivery of service.
A single system may have all hard, soft, and real real-time subsystems.
In reality many systems will have a cost function associated with
missing each deadline.
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 Multi-Tasking and Concurrency
• Most real-time systems are also embedded systems with several
inputs and outputs and multiple events occurring independently.
• Separating tasks simplifies programming but requires somehow
switching back and forth among the three tasks (multi-tasking).
• Concurrency is the appearance of simultaneous execution of
multiple tasks.
Concurrent Tasks for a Thermostat
/* Monitor Temperature */ /* Monitor Time of Day */ /* Monitor Keypad */
do forever { do forever { do forever {
measure temp ; measure time ; check keypad ;
if (temp < setting) if (6:00am) if (raise temp)
start furnace ; setting = 72oF ; setting++ ;
else if (temp > else if (11:00pm) else if (lower temp)
setting + delta) setting = 60oF ; setting-- ;
stop furnace ; } }
}

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 Embedded System Applications
Aerospace Navigation systems, automatic landing
systems, flight attitude controls, engine
controls, space exploration
(e.g., the Mars Pathfinder).
Automotive Fuel injection control, passenger environmental
controls, anti-lock braking, air bag controls,
GPS mapping.
Children's Nintendo's "Game Boy", Mattel's "My
Toys Interactive Pooh", Tiger Electronics’ "Furby".

Communi- Satellites; network routers, switches, hubs.

cations
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 Embedded System Applications

Computer Printers, scanners, keyboards, displays,

Peripherals modems, hard disk drives, CD/DVD-ROM
drives.
Home Dishwashers, microwave ovens, VCRs,
televisions, stereos, fire/security alarm
systems, lawn sprinkler controls, thermostats,
cameras, clock radios, answering machines.

Industrial Elevator controls, surveillance systems,

robots.
Instrumen- Data collection, oscilloscopes, signal
tation generators, signal analyzers, power supplies.
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 Embedded System Applications

Medical Imaging systems (e.g., XRAY, MRI, and

ultrasound), patient monitors, and heart
pacers.
Office FAX machines, copiers, telephones, and
Automation cash registers.

Personal Personal Digital Assistants (PDAs),

pagers, cell phones, wristwatches, video
games, portable MP3 players, GPS.

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 Embedded Real-Time Software Examples
Property FAX Machine CD/DVD Player
Microprocessor: 16-bit 16-bit
Number of Threads: 6 9-12
Read-Write Memory 2048 Bytes 512 Bytes
(RAM):
Total RAM Actually Used: 1346 Bytes (66%) 384 Bytes (75%)
Amount Used by Kernel: 250 Bytes (19%) 146 Bytes (38%)
Read-Only Memory 32.0 KB 32.0 KB
(ROM):
Total ROM Actually Used: 28.8 KB (90%) 17.8 KB (56%)
Amount Used by Kernel: 2.5 KB (8.7%) 2.3 KB (13%)

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 Embedded System Examples
• Aircraft and jet engine control
• Satellites, Space crafts
• Nuclear reactor and power system control
• Networking devices like routers, switches etc.
• Personal digital assistant (PDA).
• Printer, Plotters etc.
• Cell phone
• Television and other Consumer Electronics
• Household appliances
• Automobile: engine, brakes, dash, etc.

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 Automotive Embedded Systems
Today’s high-end automobile may have 100 microprocessors:
• 4-bit microcontroller checks seat belt
• Microcontrollers run dashboard devices
• 16/32-bit microprocessor controls engine

BMW 850i brake and stability control system

• Anti-lock brake system (ABS): Pumps brakes to reduce
skidding.
• Automatic Stability Control (ASC+T): Controls engine to
improve stability.
• ABS and ASC+T communicate.
ABS was introduced first---needed to interface to existing
ABS module.
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 Embedded Systems and Automobile

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 Anti-lock Brake System (ABS)

Sensor Sensor

Wheel Wheel

Brake Brake

Hydraulic
ABS Pump

Brake Brake
Wheel Wheel

Sensor Sensor

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 Electrohydraulic Brake

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 Embedded System Application
Fluid Control System Interface

Pipe

Input flow Flow meter

reading

Processing

Valve
Output valve
angle
Time
Computer

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 Embedded System Applications
Programmable Digital Thermostat
Uses: 4-bit Microprocessor

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 Embedded System Applications
Miele Dishwashers
Microprocessor: 8-bit Motorola 68HC05

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 DVD Player

Microprocessor:
32-bit RISC
(Reduced
Instruction Set
Computer)

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IBM Research’s Linux Wristwatch Prototype

Microprocessor
32-bit ARM RISC

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 Vitality’s GlowCap

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 Vitality’s GlowCap

• GlowCap has a
tiny Amtel 8-bit
picoPower AVR
Processor
• Help People to take
their medication on-
time.
• Sense when the
bottle is opened.
• Connect to Vitality
server and transmit
information
wirelessly.

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 Intel WISP RFID

TIMSP430F1232: Low
Power Micro-controller

• 16-bit CPU
• 8 Kbytes of flash
memory
• 256 bytes of RAM
• 10-bit –ADC with
200 kilo-samples/second
• CPU can run at 8MHz
with 3.3V supply voltage

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 MAR’s Rovers
Pathfinder-1997, Spirit/Opportunity-2003 and Curiosity-2012

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 2003 MAR’S Rover
Spirit/Opportunity
• Use BAE Systems
RAD6000 32-bit
RISC Processor
• Radiation
hardened IBM
POWER series
6000 CPU
• Employ VxWorks
Embedded Real-
time Operating
System
from Wind River.

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 Mars Rover RAD6000 Flight Computer
FPGA-based

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MARS Rover 2020 - Perseverance Rover
Landed February 2021

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 Comparison of embedded Computer Systems
for Mars Rovers
Operating
Rover (mission,year) CPU RAM Storage
system
Sojourner Rover 2MHz Intel
512KB 176 KB Custom cyclic
(Pathfinder 1997) 80C85
executive
Pathfinder Lander (1997) 20MHz IBM 128 6 MB VxWorks
(Base station for Sojourner rover) RAD6000 MB (EEPROM) (multitasking)
20 MHz IBM 128 VxWorks
Spirit and Opportunity RAD6000 MB
256 MB
(multitasking)
(Mars Exploration Rover, 2004)

Curiosity (Mars Science 200 MHz IBM 256 VxWorks

2GB
Laboratory, 2011) RAD750 MB (multitasking)

Perseverance 200 MHz IBM

256 2GB VxWorks
2 Compute Elements RAD750 Flash Memory
MB 256KB EEPROM (multitasking)
(Mars Rover, 2020) Landed 2021 PowerPC 750

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 Characteristics of an RTS
• Large and complex — vary from a few hundred lines of assembler
or C to 20 million lines of Ada code estimated for the Space
Station Freedom
• Concurrent control of separate system components — devices
operate in parallel in the real world; better to model this
parallelism by concurrent entities in the program.
• Facilities to interact with special purpose hardware — need to be
able to program devices in a reliable and abstract way
• Extreme reliability and safe — embedded systems typically
control the environment in which they operate; failure to control
can result in loss of life, damage to environment or economic loss.
• Guaranteed response times — we need to be able to predict with
confidence the worst-case response times for systems; efficiency is
important, but predictability is essential

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 Characteristics of Embedded Systems
• Sophisticated functionality.
• Real-time operation.
• Low manufacturing cost.
• Low power.
• Designed to tight deadlines by small teams.

Functional complexity
• Often have to run sophisticated algorithms or multiple
algorithms.
Cell phone, laser printer.
• Often provide sophisticated user interfaces.

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 Design goals
• Performance.
Overall speed, deadlines.
• Functionality and user interface.
• Manufacturing cost.
• Power consumption.
• Other requirements
(physical size, etc.)

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 Non-functional Requirements
• Many embedded systems are mass-market items that must
have low manufacturing costs.
• Limited memory, microprocessor power, etc.
• Power consumption is critical in battery-powered devices.
• Excessive power consumption increases system cost even in
wall-powered devices.
Power
• Custom logic is a clear winner for low power devices.
• Modern microprocessors offer features to help control
power consumption.
• Software design techniques can help reduce power
consumption.

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 Power and Clock
Intel x86 Power Requirements
• Pentium-4 made a dramatic jump in power.
• Core-2 reverts to simpler pipeline with lower power.

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 10 Years of Intel CPUs
Compared
Prime95 test code calculate prime numbers in
rapid succession and will do this until:
(a) It finds a unique prime number and notify.
(b) We stop the test.
(c) CPU hardware fails and the test fails due to
a miscalculation (worst-case scenario)

• Inel Celeron G1820 consumed the least

amount of power, followed by Pentium
G3220, and then the Core i3-4350.
• Between the Core i3-4350 and i5-4690K,
there are i5-2500K and i5-760, while the
Core i7-870 consumes roughly the same
amount of power as the i5-4690K.
• Core 2 Duo E6600 consumed the same
amount of power as the i7-4790K and
2700K. The Core 2 Quad processors
consumed considerably more, reaching a
total system consumption of 170 watts.

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 ARM vs. x86 Power

iMX6 is Cortex A7, A9 and M4 multicore CPUs NXP SoCs

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 NXP iMX6 Multiple ARM Processors

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 Platforms

Embedded computing platform: hardware architecture +

associated software.
Many platforms are multiprocessors.

Examples:
• Single-chip multiprocessors for cell phone base band.
• Automotive network + processors.

Heterogeneous systems:
• Some custom logic for well-defined functions
• CPUs+software for everything else

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 The Performance Paradox
Microprocessors use much more logic to implement a
function than does custom logic.

But microprocessors are often at least as fast:

• Heavily pipelined
• Large design teams
• Aggressive VLSI technology

In general-purpose computing, performance often means

average-case, may not be well defined.
In real-time systems, performance means meeting deadlines.
• Missing the deadline by even a little is bad.
• Finishing ahead of the deadline may not help.
© LP EEE3132: Introduction-to-Embedded Systems Page: 45
 Characterizing Performance
We need to analyze the system at several
levels of abstraction to understand
performance:
• CPU
• Platform
• Program
• Task
• Multiprocessor

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 Design Goals
Reliability
• Mission Critical
• Life-Threatening Application
• 24/7/365 and cannot reboot!
Performance
• Multitasking and Scheduling
• Optimized I/O, Assembly Language
• Limits, Inaccuracies of Fixed Precision
Cost
• Consumer Market: Minimize Manufacturing Cost.
• Fast Time to Market Required
• No chance for future modification

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 Challenges in Embedded System Design
• How much hardware do we need?
▪ How big is the CPU? Memory?
• How do we meet our deadlines?
▪ Faster hardware or cleverer software?
• How do we minimize power?
▪ Turn off unnecessary logic? Reduce memory accesses?
Does it really work?
• Is the specification correct?
• Does the implementation meet the spec?
• How do we test for real-time characteristics?
• How do we test on real data?
How do we work on the system?
• What is our development platform?

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 Design Methodologies
• A procedure for designing a system.
• Understanding your methodology helps you ensure you didn’t
skip anything.
• Compilers, software engineering tools, computer-aided design
(CAD) tools, etc., can be used to:
▪ Help automate methodology steps;
▪ Keep track of the methodology itself.

Top-down design:
• Start from most abstract description;
• Work to most detailed.
Bottom-up design:
•Work from small components to big system.
Real design uses both techniques

© LP EEE3132: Introduction-to-Embedded Systems Page: 49

 Summary

• Embedded computers are all around us.

Many systems have complex embedded hardware and
software.
• Embedded systems pose many design
challenges:
▪ Design time,
▪ Deadlines,
▪ Power, etc.
• Design methodologies help us manage the
design process.

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 Where are we heading?
• Embedded Computer Systems
• Hardware Software Co-design of Embedded System
• Embedded CPUs and ARM Cortex M3/M4 Processors
• Cortex M3 Programming for Embedded Applications
• Real-time Operating System (RTX) and Scheduling
• SystemC and Hardware Software Co-design
• Embedded System Co-synthesis
• Embedded System on Programmable Chips
(if time permits)
• Fault-tolerant Embedded Computer Systems
• Embedded System Case Studies
• A Typical Embedded System Example
© LP EEE3132: Introduction-to-Embedded Systems Page: 51
 Overview of
Microprocessors
Lecturer: Dr. Lukumba Phiri,
PhD.

Week3 1
Lecture overview
⚫ Introduction to microprocessors
⚫ Instruction set architecture
⚫ Typical commercial microprocessors

Week3 2
Microprocessors
⚫ A microprocessor is a CPU on a single chip.
⚫ If a microprocessor, its associated support
circuitry, memory and peripheral I/O
components are implemented on a single
chip, it is a microcontroller.

Week3 3
Microprocessors
⚫ Microprocessor Based Embedded System:
⚫ CPU for Computers
⚫ No: RAM, ROM, I/O on CPU chip itself
⚫ Ex: Intel‘s 8085 (MAT385), 8086, Motorola‘s
680xx

Week3 4
Microprocessors
⚫ Microcontroller Based Embedded System:
⚫ A Small Computer or System on Chip (SoC)
⚫ On-chip RAM, ROM, I/O ports...
⚫ Example: TI‘s MSP430, Motorola‘s 6811,
Intel‘s 8051, Zilog‘s Z8 and PIC 16X

Week3 5
Microprocessors

Week3 6
Microprocessor types
⚫ Microprocessors can be characterized based
on
⚫ the word size
⚫ 8 bit, 16 bit, 32 bit, etc. processors
⚫ Instruction set structure
⚫ RISC (Reduced Instruction Set Computer), CISC
(Complex Instruction Set Computer)
⚫ Functions
⚫ General purpose, special purpose such image
processing, floating point calculations
⚫ And more … Week3 7
Typical microprocessors
⚫ Most commonly used
⚫ 68K
⚫ Motorola
⚫ x86
⚫ Intel
⚫ IA-64
⚫ Intel
⚫ MIPS
⚫ Microprocessor without interlocked pipeline stages
⚫ ARM
⚫ Advanced RISC Machine
⚫ PowerPC
⚫ Apple-IBM-Motorola alliance
⚫ Atmel AVR
⚫ A brief summary will be given later
Week3 8
Microprocessor applications
⚫ A microprocessor application system can be
abstracted in a three-level architecture
⚫ ISA is the interface between hardware and software

FORTRAN 90 C program
program
FORTRAN 90 C program
program compiled compiled
to ISA program to ISA program
Software
ISA level
Hardware
ISA program executed
by hardware

Hardware

Week3 9
ISA
⚫ Stands for Instruction Set Architecture
⚫ Provides functional specifications for software
programmers to use/program hardware to
perform certain tasks
⚫ Provides the functional requirements for
hardware designers so that their hardware
design (called micro-architectures) can
execute software programs.

Week3 10
What makes an ISA
⚫ ISA specifies all aspects of a computer
architecture visible to a programmer
⚫ Basic
⚫ Instructions
▪ Instruction format
▪ Addressing modes
⚫ Native data types
⚫ Registers
⚫ Memory models
⚫ advanced
⚫ Interrupt handling Week3 11

▪ To be covered in the later lectures

Instructions
⚫ This is the key part of an ISA
⚫ specifies the basic operations available to a
programmer
⚫ Example:
⚫ Arithmetic instructions
⚫ Instruction set is machine oriented
⚫ Different machine, different instruction set
⚫ For example
▪ 68K has more comprehensive instruction set than ARM

Week3 12
Instructions (cont.)
⚫ Instruction set is machine oriented
⚫ Same operation, could be written differently in
different machine
⚫ AVR
▪ Addition: add r2, r1 ;r2  r2+r1
▪ Branching: breq 6 ;branch if equal condition is true
▪ Load: ldi r30, $F0 ;r30  Mem[F0]
⚫ 68K:
▪ Addition: add d1,d2 ;d2  d2+d1
▪ Branching: breq 6 ;branch if equal condition is true
▪ Load: mov #1234, D3 ;d3  1234

Week3 13
Instructions (cont.)
⚫ Instructions can be written in two languages
⚫ Machine language
⚫ made of binary digits
⚫ Used by machines
⚫ Assembly language
⚫ a textual representation of machine language
⚫ Easier to understand than machine language
⚫ Used by human beings

Week3 14
Machine code vs. assembly
code
⚫ There is a one-to-one mapping between the
machine code and assembly code
⚫ Example (Atmel AVR instruction):
For increment register 16:
⚫ 1001010100000011 (machine code)

⚫ inc r16 (assembly language)

⚫ Assembly language also includes directives
⚫ Instructions to the assembler
⚫ Example:
⚫ .def temp = r16
Week3 15

⚫ .include “mega64def.inc”
Data types
⚫ The basic capability of using different classes of values.
⚫ Typical data types
⚫ Numbers
⚫ Integers of different lengths (8, 16, 32, 64 bits)
▪ Possibly signed or unsigned
▪ Commonly available
⚫ Floating point numbers, e.g. 32 bits (single precision) or 64 bits
(double precision)
▪ Available in some processors such as PowerPC
⚫ BCD (binary coded decimal) numbers
▪ Available in some processors, such as 68K
⚫ Non-numeric
⚫ Boolean
⚫ Characters
Week3 16
 Data types (cont.)
⚫ Different machines support different data
types in hardware
⚫ e.g. Pentium II:
Data Type 8 bits 16 bits 32 bits 64 bits 128 bits
Signed integer ✓ ✓ ✓
Unsigned integer ✓ ✓ ✓
BCD integer ✓
Floating point ✓ ✓

⚫ e.g. Atmel AVR:

Data Type 8 bits 16 bits 32 bits 64 bits 128 bits
Signed integer ✓ Partial
Unsigned integer ✓ Partial
BCD integer
Floating point

Week3 17
Registers
⚫ Two types
⚫ General purpose
⚫ Special purpose
⚫ Used for special functions
⚫ e.g.
▪ Program Counter (PC)
▪ Status Register
▪ Stack pointer (SP)
▪ Input/Output Registers.

Week3 18
General Purpose Registers
⚫ A set of registers in the machine
⚫ Used for storing temporary data/results
⚫ For example
⚫ In (68K) instruction add d3, d5, operands are stored in
general registers d3 and d5, and the result are stored in d5.
⚫ Can be structured differently in different machines
⚫ For example
⚫ Separated general purpose registers for data and address
▪ 68K
⚫ Different numbers registers and different size of each
registers
▪ 32 32-bit in MIPS
Week3 19
▪ 16 32-bit in ARM
Program counter
⚫ Special register
⚫ For storing memory address of currently executed
instruction
⚫ Can be of different size
⚫ E.g. 16 bit, 32 bit
⚫ Can be auto-incremented
⚫ By the instruction word size
⚫ Gives rise the name “counter”

Week3 20
Status register
⚫ Contains a number of bits with each bit
associated with CPU operations
⚫ Typical status bits
⚫ V: Overflow
⚫ C: Carry
⚫ Z: Zero
⚫ N: Negative
⚫ Used for controlling program execution flow

Week3 21
Memory models
⚫ Data processed by CPU is usually large and cannot
be held in the registers at the same time.
⚫ Both data and program code need to be stored in
memory.
⚫ Memory model is related to how memory is used to
store data
⚫ Issues
⚫ Addressable unit size
⚫ Address spaces
⚫ Endianness
⚫ Alignment Week3 22
Addressable unit size
⚫ Memory has units, each of which has an
address
⚫ Most common unit size is 8 bits (1 byte)
⚫ Modern processors have multiple-byte unit
⚫ For example:
⚫ 32-bit instruction memory in MIPS
⚫ 16-bit Instruction memory in AVR

Week3 23
Address spaces
⚫ The range of addresses a processor can
access.
⚫ The address space can be one or more than one
in a processor. For example
⚫ Princeton architecture or Von Neumann architecture
▪ A single linear address space for both instructions and data
memory
⚫ Harvard architecture
▪ Separate address spaces for instructions and data
memories

Week3 24
Address spaces (cont.)
⚫ Address space is not necessarily just for
memories
⚫ E.g, all general purpose registers and I/O
registers can be accessed through memory
addresses in AVR
⚫ Address space is limited by the width of the
address bus.
⚫ The bus width: the number of bits the address is
represented

Week3 25
Endianness
⚫ Memory objects
⚫ Memory objects are basic entities that can be
accessed as a function of the address and the
length
⚫ E.g. bytes, words, longwords
⚫ For large objects (>byte), there are two
ordering conventions
⚫ Little endian – little end (least significant byte)
stored first (at lowest address)
⚫ Intel microprocessors (Pentium etc)
⚫ Big endian – big end stored first
Week3 26
⚫ SPARC, Motorola microprocessors
Endianness (cont.)
⚫ Most CPUs produced since ~1992 are
“bi-endian” (support both)
⚫ some switchable at boot time
⚫ others at run time (i.e. can change dynamically)

Week3 27
Big Endian & Little Endian
⚫ Example: 0x12345678—a long word of 4
bytes. It is stored in the memory at address
0x00000100
Address data
⚫ big endian: 0x00000100 12
0x00000101 34
0x00000102 56
0x00000103 78

Address data
⚫ little endian: 0x00000100 78
0x00000101 56
0x00000102 34
0x00000103
Week3
12 28
Alignment
⚫ Often multiple bytes can be fetched from
memory
⚫ Alignment specifies how the (beginning)
address of a multiple-byte data is determined.
⚫ data must be aligned in some way. For example
⚫ 4-byte words starting at addresses 0,4,8, …
⚫ 8-byte words starting at addresses 0, 8, 16, …
⚫ Alignment makes memory data accessing
more efficient
Week3 29
Example
⚫ A hardware design that has data fetched from
memory every 4 bytes

⚫ Fetching an unaligned data (as shown)

means to access memory twice.

Week3 30
Instruction format
⚫ Is a definition
⚫ how instructions are represented in binary code
⚫ Instructions typically consist of
⚫ Opcode (Operation Code)
⚫ defines the operation (e.g. addition)
⚫ Operands
⚫ what’s being operated on
⚫ Instructions typically have 0, 1, 2 or 3
operands
Week3 31
Instruction format examples

OpCode OpCode Opd

OpCode Opd1 Opd2 OpCode Opd1 Opd2 Opd3

Week3 32
Example (AVR instruction)
⚫ Subtraction with carry
⚫ Syntax: sbc Rd, Rr
⚫ Operation: Rd ← Rd – Rr – C
⚫ Rd: Destination register. 0  d  31
⚫ Rr: Source register. 0  r  31, C: Carry
⚫ Instruction format
0 0 0 0 1 0 r d d d d d r r r r
15 0

⚫ OpCode uses 6 bits (bit 9 to bit 15).

⚫ Two operands share the remaining 10 bits.
Week3 33
Instruction lengths
⚫ The number of bits an instruction has
⚫ For some machines – instructions all have
the same length
⚫ E.g. MIPS machines
⚫ For other machines – instructions can have
different lengths
⚫ E.g. M68K machine

Week3 34
Instruction encoding
⚫ Operation Encoding
⚫ 2n operations needs at least n bits
⚫ Operand Encoding
⚫ Depends on the addressing modes and access
space.
⚫ For example: An operand in direct register addressing
mode requires at most 3 bits if the the number of
registers it can be stored is 8.
⚫ With a fixed instruction length, more encoding
of operations means less available bits for
encoding operands
Week3 35
⚫ Tradeoffs should be concerned
Example 1
⚫ A machine has:
⚫ 16 bit instructions
⚫ 16 registers (i.e. 4-bit register addresses)
⚫ Instructions could be formatted like this:

OpCode Operand1 Operand2 Operand3

⚫ Maximally 16 operations can be defined.

⚫ But what if we need more instructions and some
instructions only operate on 0, 1 or 2 registers?
Week3 36
Example 2
⚫ For a 16 bit instruction machine with 16
registers, design OpCodes that allow for
⚫ 14 3-operand instructions
⚫ 30 2-operand instructions
⚫ 30 1-operand instructions
⚫ 32 0-operand instructions

Week3 37
Addressing modes
⚫ Instructions need to specify where to get operands from
⚫ Some possibilities
⚫ Values are in the instruction
⚫ Values are in the register
⚫ Register number is in the instruction
⚫ Values are in memory
⚫ address is in instruction
⚫ address is in a register
▪ register number is in the instruction
⚫ address is register value plus some offset
▪ register number is in the instruction
▪ offset is in the instruction (or in a register)
⚫ These ways of specifying the operand locations are called
addressing modes
Week3 38
Immediate Addressing
⚫ The operand is from the instruction itself
⚫ I.e the operand is immediately available from the
instruction
⚫ For example, in 68K
addw #99, d7

⚫ Perform d7  99 + d7; value 99 comes from the

instruction
⚫ d7 is a register Week3 39
Register Direct Addressing
⚫ Data from a register and the register number
is directly given by the instruction
⚫ For example, in 68K
addw d0,d7
⚫ Perform d7  d7 + d0; add value in d0 to value in d7
and store result to d7
⚫ d0 and d7 are registers

Week3 40
Memory direct addressing
⚫ The data is from memory, the memory
address is directly given by the instruction
⚫ We use notion: (addr) to represent memory
value with a given address, addr
⚫ For example, in 68K
addw 0x123A, d7

⚫ Perform d7  d7 + (0x123A); add value in memory

location 0x123A to register d7
Week3 41
Memory Register Indirect
Addressing
⚫ The data is from memory, the memory
address is given by a register and the register
number is directly given by the instruction
⚫ For example, in 68K
addw (a0),d7
⚫ Perform d7  d7 + (a0); add value in memory
with the address stored in register a0, to register
d7
⚫ For example, if a0 = 100 and (100) = 123, then this adds
123 to d7 Week3 42
Memory Register Indirect
Auto-increment
⚫ The data is from memory, the memory
address is given by a register, which is
directly given by the instruction; and the value
of the register is automatically increased – to
point to the next memory object.
⚫ Think about i++ in C
⚫ For example, in 68K
addw (a0)+,d7

⚫ d7  d7 + (a0); a0  a0 + 2
Week3 43
Memory Register Indirect
Auto-decrement
⚫ The data is from memory, the memory
address is given by a register and the register
number is directly given by the instruction;
but the value of the register is automatically
decreased before such an operation.
⚫ Think --i in C
⚫ For example, in 68K
addw -(a0),d7

⚫ a0  a0 –2; d7  d7 + (a0);
Week3 44
Memory Register Indirect with
Displacement
⚫ Data is from the memory with the address
given by the register plus a constant
⚫ Used in the access of a member in a data
structure
⚫ For example, in 68K
addw a0@(8), d7

⚫ d7  (a0+8) +d7

Week3 45
Address Register Indirect with
Index and displacement
⚫ The address of the data is sum of the initial address
and the index address as compared to the initial
address plus a constant
⚫ Used in accessing element of an array
⚫ For example, in 68K
addw a0@(d3)8, d7

⚫ d7  (a0 + d3+8)
⚫ With a0 as an initial address and d3 as an index
dynamically pointing to different elements, plus a constant
for a certain member in an array element.
Week3 46
RISC
⚫ RICS stands for reduced instruction set
computer
⚫ Smaller and simpler set of instructions
⚫ Smaller: small number of instructions in the instruction
set
⚫ Simpler: instruction encoding is simple
▪ Such as fixed instruction length
⚫ All instructions take about the same amount of
time to execute

Week3 47
CISC
⚫ CISC stands for complex instruction set
computer
⚫ Each instructions can execute several low-level
operations
⚫ Such operations of load memory, arithmetic and store
memory in one instructions
⚫ Required complicated hardware support
⚫ All instructions take different amount of time to
execute

Week3 48
Recall: Typical processors
⚫ Most commonly implemented in hardware
⚫ 68K
⚫ Motorola
⚫ x86
⚫ Intel
⚫ IA-64
⚫ Intel
⚫ MIPS
⚫ Microprocessor without interlocked pipeline stages
⚫ ARM
⚫ Advanced RISC Machine
⚫ PowerPC
⚫ Apple-IBM-Motorola alliance
Week3 49

⚫ Atmel AVR
X86
⚫ CISC architecture
⚫ 16 bit → 32-bit → 64-bit
⚫ Words are stored in the little endian order
⚫ Allow unaligned memory access.
⚫ Current x86-processors employs a few “extra”
decoding steps to (during execution) split (most) x86
instructions into smaller pieces (micro-instructions)
which are then readily executed by a RISC-like
micro-architecture.
⚫ Application areas (dominant)
⚫ Desktop, portable computer, small servers
Week3 50
68K
⚫ CISC processor
⚫ Early generation, hybrid 8/16/32 bit chip (8-bit
bus)
⚫ Late generation, fully 32-bit
⚫ Separate data registers and address registers
⚫ Big endian
⚫ Area applications
⚫ Early used in for calculators, control systems,
desktop computers
⚫ Later used in microcontroller/embedded
Week3 51

microprocessors.
MIPS
⚫ RISC processor
⚫ A large family designs with different configurations
⚫ Deep pipeline (>=5 stages)
⚫ With additional features
⚫ Clean instruction set
⚫ Could be booted either big-endian or little-endian
⚫ Many application areas, including embedded
systems
⚫ The design of the MIPS CPU family, together with
SPARC, another early RISC architecture, greatly
influenced later RISC designs
Week3 52
ARM
⚫ 32-bit RISC processor
⚫ Three-address architecture
⚫ No support for misaligned memory accesses
⚫ 16 x 32 bit register file
⚫ Fixed opcode width of 32 bit to ease decoding and
pipelining, at the cost of decreased code density
⚫ Mostly single-cycle execution
⚫ With additional features
⚫ Conditional execution of most instructions
▪ reducing branch overhead and compensating for the lack of
a branch predictor
▪ Powerful indexed addressing modes
Week3 53
⚫ Power saving
PowerPC
⚫ Superscalar RISC
⚫ 32-bit, 64-bit implementation
⚫ With both big-endian and little endian modes,
can switch from one mode to the other at run-
time.
⚫ Intended for high performance PC, for high-
end machines

Week3 54
Reading Material
⚫ Chap.2 in Microcontrollers and
Microcomputers.

Week3 55
Questions
1. Given an address bus width in a
processor as 16-bit, determine the
maximal address space.
2. Assume a memory address is 0xFFFF,
how many locations this address can
represent if the related computer is?
I) a Harvard machine
II) a Von Neumann machine
Week3 56
 EEE 3132 - Week 4 & 5
The 80x86 Microprocessor
Architecture
 Brief History of the 80x86 Family
• Evolution from 8080/8085 to 8086
– In 1987, Intel introduced a 16-bit microprocessor called the 8086
– It was a major improvement over the previous generation 8080/8085
microprocessors
• 1 Mbyte memory (20 address lines) vs 8080/8085’s capability of 64 Kbytes
• 8080/8085 was an 8 bit system, meaning that the data larger than 8 bits should
be broken into 8-bit pieces to be processed by the CPU; in contrast 8086 is a 16
bit microprocessor
• 8086 is pipelined vs nonpipelined 8080/8085; in a system with pipelining the
data and address busses are busy transferring data while the CPU is processing
information
• Evolution from 8086 to 8088
– 8086 is a microprocessor with a 16-bit data bus internally and externally
– Internal because all registers are 16 bits wide
– External because the data bus was 16 bits to transfer data in and out of the
CPU
– There was a resistance in using the 16 bit external data bus since at that
time peripherals were designed around 8-bit microprocessors
– Intel then came out with the 8088 version with 8-bit data bus
2
Brief History - Continued
• Success of 8088
– IBM picked up the 8088 as their microprocessor of choice in designing
the IBM PC
– All specification of the hardware and software of the PC are made
public by IBM and Microsoft (in contrast with Apple computers)
• Other microprocessors: 80386, 80386, 80486
– Intel introduced 80286 in 1982
– 16 bit internal and external data buses
– 24 address lines (16 Mbyte main memory)
– Virtual memory: a way of fooling the microprocessor into thinking that it
has access to almost unlimited amount of memory by swapping data
between disk storage and RAM
– Real mode vs protected mode
– Intel unveiled the 80386 (sometimes called the 80386DX) in 1985;
internally and externally a 32 bit microprocessor with a 32 bit address
bus (4 Gbyte physical memory)
– Numeric data processing chips were made available: 8087, 80287,
80387 etc.

3
Evolution of Intel’s microprocessors

4
Virtual 8086 Mode
• Real Mode
– Only one program can be run one time
– All of the protection and memory management functions are turned off
– Memory space is limited to 1MB
• Virtual 8086 Mode
– The 386 hands each real mode program its own 1MB chunk of memory
– Multiple 8086 programs to be run simultaneously but protected from
each other (multiple MSDOS prompts)
– Due to time sharing, the response becomes much slower as each new
program is launched
– The 386 can be operated in Protected Mode and Virtual 8086 mode at
the same time.
– Because each 8086 task is assigned the lowest privilege level, access
to programs or data in other segments is not allowed thus protecting
each task.
– We’ll be using the virtual 8086 mode in the lab experiments on PCs that
do have either Pentiums or 486s.

5
 The 80286 and above - Modes of Operation
•Real Mode
•The address space is limited to 1MB using address lines A0-19;
the high address lines are inactive
•The segmented memory addressing mechanism of the 8086 is retained
with each segment limited to 64KB
•Two new features are available to the programmer
–Access to the 32 bit registers
–Addition of two new segments F and G

•Protected Mode
–Difference is in the new addressing mechanism and protection levels
–Each memory segment may range from a single byte to 4GB
–The addresses stored in the segment registers are now interpreted as
pointers into a descriptor table
–Each segment’s entry in this table is eight bytes long and identifies the
base address of the segment, the segment size, and access rights
–In 8088/8086 any program can access the core of the OS hence crash the
system. Access Rights are added in descriptor tables. 6
Brey 59
 Virtual Memory
• 286 onward supported Virtual Memory Management and Protection
• Unlimited amount of main memory assumed
• Two methods are used:
– Segmentation
– Paging
• Both techniques involve swapping blocks of user memory with hard disk
space as necessary
– If the program needs to access a block of memory that is indicated to be stored in
the disk, the OS searches for an available memory block (typically using a least
recently used algorithm) and swaps that block with the desired data on the hard
drive
– Memory swapping is invisible to the user
– Segmentation: the block size is variable ranging up to 4GB
– Paging: Block sizes are always 4 KB at a time.
• A final protected mode feature is the ability to assign a privilege level to
individual tasks (programs). Tasks of lower privilege level cannot access
programs or data with a higher privilege level. The OS can run multiple
programs each protected from each other.

Mazidi 648
7
The 8086 and 8088
• The 8086 microprocessor represents the foundation upon which all
the 80x86 family of processors have been built
• Intel has made the commitment that as new generations of
microprocessors are developed, each will maintain software
compatibility with this first generation part.
– For example, a program designed to run on an Intel 386
microprocessor, which also runs on a Pentium, is upward compatible.
• Processor model
– BIU (Bus Interface Unit) provides hardware functions including
generation of the memory and I/O addresses for the transfer of data
between itself and the outside world
– EU (Execution Unit) receives program instruction codes and data from
the BIU executes these instructions and stores the results in the general
registers.
– EU has no connection to the system busses; it receives and outputs all
its data through the BIU.

8
Execution and Bus Interface Units

9
Fetch and Execute Cycle
• Fetch and execute cycles overlap
– BIU outputs the contents of the IP onto the address bus
– Register IP is incremented by one or more than one for the next
instruction fetch
– Once inside the BIU, the instruction is passed to the queue; this queue
is a first-in-first-out register sometimes likened to a pipeline
– Assuming that the queue is initially empty the EU immediately draws
this instruction from the queue and begins execution
– While the EU is executing this instruction, the BIU proceeds to fetch a
new instruction.
• BIU will fill the queue with several new instructions before the EU is ready to
draw its next instruction
– The cycle continues with the BIU filling the queue with instructions and
the EU fetching and executing these instructions

10
Pipelined Architecture
• Three conditions that will cause the EU to enter a wait mode
– when the instruction requires access to a memory location not in the
queue
– when the instruction to be executed is a jump instruction; the instruction
queue should be flushed out (known as branch penalty too much
jumping around reduces the efficiency of the program)
– during the execution of slow instructions
• for example the instruction AAM (ASCII Adjust for Multiplication) requires 83
clock cycles to complete for an 8086
• 8086 vs 8088
– BIU data bus width 8 bits for 8088, BIU data bus width 16 bits for 8086
– 8088 instruction queue is four bytes instead of six
– 8088 is found to be 30% slower than 8086
• WHY
– Long instructions provide more time for the BIU to fill the queue

11
 Nonpipelined vs pipelined architecture
Time

Fetch Execute Fetch Execute Fetch Execute

Non-pipelined architecture
BIU
F F F F F F Read
Data Fd Fd Fd F F

EU
Wait E E E Er Wait E E Ej Wait E

Pipelined architecture
Er: a request for data not in the queue
Ej: jump instruction occurs Fd: Discarded
12
Registers of the 8086/80286 by Category
Category Bits Register Names
General 16 AX,BX,CX,DX

8 AH,AL,BH,BL,CH,CL,DH,DL

Pointer 16 SP (Stack Pointer), Base Pointer (BP)

Index 16 SI (Source Index), DI (Destination Index)

Segment 16 CS(Code Segment)

DS (Data Segment)
SS (Stack Segment)
ES (Extra Segment)
Instruction 16 IP (Instruction Pointer)

Flag 16 FR (Flag Register)

13
General Purpose Registers
H L
15 8 7 0
AX (Accumulator)
AH AL
BX (Base Register)
BH BL
CX (Used as a counter)
CH CL
DX (Used to point to data in I/O operations)
DH DL

• Data Registers are normally used for storing temporary

results that will be acted upon by subsequent instructions
• Each of the registers is 16 bits wide (AX, BX, CX, DX)
• General purpose registers can be accessed as either 16 or 8
bits e.g., AH: upper half of AX, AL: lower half of AX
14
Data Registers

Register Operations
AX Word multiply, word divide, word I/O

AL Byte multiply, byte divide, byte I/O, decimal arithmetic

AH Byte multiply, byte divide

BX Store address information

CX String operations, loops

CL Variable shift and rotate

DX Word multiply, word divide, indirect I/O

15
Pointer and Index Registers
SP Stack Pointer

BP Base Pointer

SI Source Index

DI Destination Index

IP Instruction Pointer

The registers in this group are all 16 bits wide

Low and high bytes are not accessible
These registers are used as memory pointers
• Example: MOV AH, [SI]
Move the byte stored in memory location
whose address is contained in register SI to register AH
IP is not under direct control of the programmer
16
Computer Programming
• Machine Language vs Assembly Language
– Machine language or object code is the only code a computer can
execute but it is nearly impossible for a human to work with
– E4 27 88 C3 E4 27 00 D8 E6 30 F4 the object code for adding two
numbers input from the keyboard
• When programming a microprocessor, programmers often use
assembly language
– This involves 3-5 letter abbreviations for the instruction codes
(mnemonics) rather than the binary or hex object codes

Source code 17
 Edit, Assemble, Test, and Debug Cycle
• Using an editor, the source code of the program is
created. This means selecting the appropriate instruction
mnemonics to accomplish the task
• A compiler program which examines the source code file
generated by the editor and determines the object code for
each instruction in the program, is then run. In assembly
language programming, this is called an assembler
(MASM (Chapter 2 of the textbook, DEBUG: Appendix A
of the textbook, etc., )
• The object code produced by the computer is loaded into
the target computer’s memory and is then run.
• Debugging: locating and fixing the source of error
• High-level programming Languages
– Basic, Pascal, C, C++
18
MOV Instruction
• MOV destination,source
– 8 bit moves
• MOV CL,55h
• MOV DL,CL
• MOV BH,CL
• Etc.
– 16 bit moves
• MOV CX,468Fh
• MOV AX,CX
• MOV BP,DI
• Etc.

19
MOV Instruction
• Data can be moved among all registers but data cannot be
moved directly into the segment registers (CS,DS,ES,SS).
– To load as such, first load a value into a non-segment register and then
move it to the segment register
MOV AX,2345h
MOV DS,AX

• Moving a value that is too large into a register will cause an

error
MOV BL,7F2h ; illegal
MOV AX,2FE456h ; illegal

• If a value less than than FFh is moved into a 16 bit register. The
rest of the bits are assumed to be all zeros.

MOV BX,5 ; BX = 0005 with BH = 00 and BL = 05

20
MOV Instruction

• MOV AX,58FCH 
• MOV DX,6678H 
• MOV SI,924BH 
• MOV BP,2459H 
• MOV DS,2341H x
• MOV CX,8876H 
• MOV CS,3F47H x
• MOV BH,99H 

21
ADD Instruction
• ADD destination,source
• The ADD instruction tells the CPU to add the source and destination
operands and put out the results in the destination

DESTINATION = DESTINATION + SOURCE

MOV AL,25H
MOV BL,34h
ADD AL,BL ; (AL should read 59h once the instruction is executed)
MOV DH,25H
ADD DH,34h ; (AL should read 59h once the instruction is executed)

Immediate operand

22
Origin and Definition of a Segment

• A segment is an area of memory that includes up to 64

Kbytes and begins on an address divisible by 16 (such
an address ends with an hex digit 0h or 0000b)
– 8085 could address 64Kbytes 16 address lines
• In the 8085, 64 K is for code, data, and stack
• In the 8086/88, 64 K is assigned to each category
– Code segment
– Data segment
– Stack Segment
– Extra Segment

23
Advantages of Segmented Memory
• One program can work on several different sets of data. This is done
by reloading register DS to a new value.
• Programs that reference logical addresses can be loaded and run
anywhere in the memory: relocatable
• Segmented memory introduces extra complexity in both hardware in
that memory addresses require two registers.
• They also require complexity in software in that programs are limited
to the segment size
• Programs greater than 64 KB can be run on 8086 but the software
needed is more complex as it must switch to a new segment.
• Protection among segments is provided.

24
Segment Registers

25
Logical and Physical Addresses
• Addresses within a segment can range from address 0 to address
FFFFh. This corresponds to the 64Kbyte length of the segment
called an offset
• An address within a segment logical address
• Ex. Logical address 0005h in the code segment actually
corresponds to B3FF0h + 5 = B3FF5h. Example 1:
15 0 Segment base value: 1234h
Offset: 0022h
OFFSET VALUE
12340h
+ 0022h
19 5 0
12362h is the physical 20 bit address
SEGMENT REGISTER 0h
Two different logical addresses may
correspond to the same physical
address.
ADDER D470h in ES 2D90h in SS
ES:D470h SS:2D90h
20 BIT PHYSICAL ADDRESS
26
 Example
•If DS=7FA2H and the offset is 438EH
a) Calculate the physical address 8FA1F

7FA20 + 438E = 83DAE

b) calculate the lower range

7FA20 + 0000 = 7FA20

FFFF

c) Calculate the upper range of the data segment 83DAE

7FA20 + FFFF = 8FA1F

d) Show the logical Address

7FA20
7FA2:438E

mazidi
27
 Example
Question:
Assume DS=578C. To access a Data in 67F66 what should we do?
67F66
678BF

DS=578C capability

change
DS 578C0

To any value
between
57F7h - 67F6h
28
Code Segment
• To execute a program, the 8086 fetches the instructions
(opcodes and operands) from the code segment
• The logical address is in the form CS:IP

• Example: If CS = 24F6h and IP = 634Ah, show

• The logical address
• The offset address
and calculate
• The physical address
• The lower range
• The upper range

29
Logical Address vs Physical Address in the CS

CS:IP Machine Mnemonics

Language
1132:0100 B057 MOV AL,57h
1132:0102 B686 MOV DH,86h
1132:0104 B272 MOV DL,72h
1132:0106 89D1 MOV CX,DX
1132:0108 88C7 MOV BH,AL
1132:010A B39F MOV BL,9F
1132:010C B420 MOV AH,20h
1132:010E 01D0 ADD AX,DX
1132:0110 01D9 ADD CX,BX
1132:0112 05351F ADD AX, 1F35h

• Show how the code resides physically in the memory

30
Data Segment
• Assume that a program is written to add 5 bytes of data
25h,12h,15h,1Fh, and 2Bh.
• One way to do it
MOV AL,00h
ADD AL, 25h
ADD AL, 12h
ADD AL,15h
ADD AL,1Fh
ADD AL,2Bh
• Data and code are mixed in the instructions here
• The problem with it is if the data changes, the code must
be searched for every place the data is included and
data retyped.
• It is a good idea then to set aside an area of memory
strictly for data

31
 Data Segment
• The data is first placed in the memory locations
DS:0200 = 25h
DS:0201 = 12h
DS:0202 = 15h
DS:0203 = 1Fh
DS:0204 = 2Bh
• Then the program is written as
MOV AL,0
ADD AL,[0200] ; bracket means add the contents of DS:0200 to AL
ADD AL,[0201]
ADD AL,[0202]
ADD AL,[0203]
ADD AL,[0204]

• If the data is stored at a different offset address, say 450 h, the

program need to be rewritten
32
Data Segment
• The term pointer is used for a register holding an offset address
• Use BX as a pointer
MOV AL,0
MOV BX,0200h
ADD AL,[BX]
INC BX
ADD AL,[BX]
INC BX
ADD AL,[BX]
INC BX
ADD AL,[BX]
INC BX
ADD AL,[BX]

• If the offset address of data is to be changed, only one

instructions will need to be modified

33
 16 bit Segment Register Assignments

Type of Default Alternate Offset

Memory Segment Segment
Reference

Instruction Fetch CS none IP

Stack SS none SP,BP

Operations

General Data DS CS,ES,SS BX, address

String Source DS CS,ES,SS SI, DI, address

String ES None DI
Destination

Brey
34
Little Endian Convention
“Little Endian” means that the low-order byte of the number
is stored in memory at the lowest address, and the high-
order byte at the highest address. (The little end comes
first.)
Intel uses Little Endian Convention.
For example, a 4 byte LongInt
Byte3 | Byte2 | Byte1 |Byte0 will be arranged in memory
as follows: • Adobe Photoshop -- Big Endian
Base Address+0 Byte0 • BMP (Windows and OS/2 Bitmaps) – little Endian
Base Address+1 Byte1 • GIF -- Little Endian
Base Address+2 Byte2 • IMG (GEM Raster) -- Big Endian
• JPEG -- Big Endian
Base Address+3 Byte3

35
 Computer Operating Systems
• What happens when the computer is first turned on?
• MS-DOS
– A startup program in the BIOS (Basic Input Output System) is
executed
– This program in turn accesses the master boot record on the
floppy or hard disk drive
– A loader then transfers the system files IO.SYS
– IO.SYS calls MSDOS.SYS. MS-DOS.SYS is basically the kernel of the
operating system.
– After initializing, MS-DOS.SYS then calls the command interpreter
COMMAND.COM which is loaded into memory. This puts the
DOS prompt on the screen that gives the user access to DOS’s
built-in commands like DIR, COPY, VER.

36
 Memory Map of a PC

The 640 K Barrier

Upper memory
DOS was designed to run block
on the original IBM PC
8088 microprocessor,
1Mbytes of main memory

IBM divided this 1Mb

address space into specific
blocks
640 K of RAM (user Conventional
memory
RAM)
384 K reserved for
ROM functions (control
programs for the video 37
 MS-DOS Functions and BIOS Services
BIOS: usually stored in ROM
– tells the CPU what to do at startup
– these routines provide access to the peripheral devices of the PC,
such as the keyboard, video, printer, and disk
– To test all the devices connected to the PC and alert if error
• Access to the BIOS is done through the software interrupt
instruction Int n
• For example, the BIOS keyboard services are accessed
using the instruction INT 16h
• In addition to BIOS services, DOS also provides higher
level functions
– INT 21h
– More details later

38
More About RAM
• Memory management is one of the most important
functions of the DOS operating systems and should be
left to DOS
• Therefore, we do not assign any values for the
DS,CS,SS registers; this is the job of DOS
• It is very important to remember that
– The DS,CS, and DS values we will experiment will be different
than those used by the textbook; do not worry

39
 Flag (Status) Register
15 FlagsH FlagsL 0
X X X X OF DF IF TF SF ZF X AF X PF X CF
• Six of the flags are status indicators reflecting properties
of the last arithmetic or logical instruction.
• For example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then the following happen
– AL = 80h
– CF = 0; there is no carry out of bit 7
– PF = 0; 80h has an odd number of ones
– AF = 1; there is a carry out of bit 3 into bit 4
– ZF = 0; the result is not zero
– SF = 1; bit seven is one
– OF = 1; the sign bit has changed
• Can be used to transfer program control to a new
memory location
ADD AL,1
JNZ 0100h 40
Example
• Show how the flag register is
affected by
– MOV AX, 34F5h
– ADD AX,95EBh Aux carry

0011 0100 1111 0101 Direction flag

1001 0101 1110 1011
overflow sign parity
zero carry
1100 1010 1110 0000
interrupt

41
TF, IF, and DF
• Three of the flags can be set or reset directly by the programmer
ands are used to control the operation of the microprocessor, these
are TF, IF, and DF.
• When TF (Trap Flag) is set, control is passed to special address
after each instruction is executed. Normally a program to display all
the registers and flags is stored there. Single-stepping mode.
• When IF (Interrupt Flag) is set, external interrupt requests on the
8086’s interrupt line INTR is enabled.
– For example a printer may spend several seconds printing a page of
text from its internal buffer
– When it is ready for new data, the printer control circuit drives the
8086’s INTR input line
– The processor then suspends whatever it is doing and begins running
the printer interrupt service routine (ISR)
– When the routine has finished via a IRET (interrupt return) instruction
control is transferred back to the original instruction in the main program
that was executing when the interrupt occurred
– Hardware and software interrupts
• DF (Direction Flag ) is used with block move instructions (more later!!).
– DF = 1 then the block memory pointer will automatically decrement
– DF = 0, then the block memory pointer will automatically increment
42
Memory Address Space and Organization

• Word
• Double Word
• Aligned Word
• Misaligned Word

43
Even addressed and odd-addressed banks

44
 Dedicated, Reserved and General Purpose Memory
•Some address locations have dedicated functions and should not be used as
general memory for storage of data or instructions of a program
FFFFF
BIOS System ROM (Dedicated)
F0000
System Area Video & H/D Controller BIOS ROM 384 K
(Dedicated)
BFFFF
Video RAM (128 K)
A0000
9FFFF
TPA
Transient 1 MB
FREE TPA
Program 640 K
Area I/O.SYS--COMMAND.COM-- MSDOS

DOS + BIOS R/W Area

User Def Int. Pointers (Reserved)

Interrupt Vectors (Dedicated) 0h

00000H
Brey 19
Mazidi 32
45
The Stack
• The stack is used for temporary storage of information such as data
or addresses; for instance when a call is executed the 8088
automatically pushes the current value of CS and IP onto the stack.
• Other registers can also be pushed
• Near the end of the subroutine, pop instructions can be used to pop
values back from the stack into the corresponding registers

PUSH POP
End of
SS:0000h stack
SP

Top of
SS:SP stack

SS Bottom of
SS:FFFEh Stack
46
Example for PUSH
• Given
– SS = 0105h
– SP = 0008h
– AX = 1234h
– What is the outcome of the PUSH AX instruction?
• ABOS = 01050 + FFFEh = 1104h
• ATOS = 01050 + 0008h = 1058h

• Decrement the SP by 2 and write AX into the word location 1056h.

SS:0006 1056h AL 34h SP 00h 06h

SS:0007 1057h AH
12h
SS:0008 1058h NOT USED

47
Example for POP

• What is the outcome of the following

POP AX
POP BX
– if originally 1058h contained AABBh?
• Read into the specified register from the stack and
increment the stack pointer for each POP operation
• At the first POP
– AX = 1234h SP = 0008h
• At the second POP
– BX = AABBh SP = 000Ah

48
 Addressing Modes

• When the 8088 executes an instruction, it performs the specified function

on data
• These data, called operands,
– May be a part of the instruction
– May reside in one of the internal registers of the microprocessor
– May be stored at an address in memory
• Register Addressing Mode
– MOV AX, BX
– MOV ES,AX
– MOV AL,BH
• Immediate Addressing Mode
– MOV AL,15h
– MOV AX,2550h
– MOV CX,625

49
Direct Addressing Mode
MOV CX, [address]

Example:
MOV AL,[03]
AL=?
BEED
02003 FF

50
 Register Indirect Addressing Mode
BX
MOV AX, DI
SI

BEED

51
Example for Register Indirect Addressing
• Assume that DS=1120, SI=2498 and AX=17FE show the memory
locations after the execution of:

MOV [SI],AX

DS (Shifted Left) + SI = 13698.

With little endian convention:
Low address 13698 → FE
High Address 13699 → 17

52
 Based-Relative Addressing Mode
DS:BX
MOV AH, [ ] + 1234h
SS:BP

3AH
BX +
AX

DS

1234

53
 Indexed Relative Addressing Mode
SI ] + 1234h
MOV AH, [ DI

Example: What is the physical address MOV [DI-8],BL if DS=200 & DI=30h ?
DS:200 shift left once 2000 + DI + -8 = 2028 54
Based-Indexed Relative Addressing Mode
• Based Relative + Indexed Relative
• We must calculate the PA (physical address)

CS
SS BX SI 8 bit displacement
PA= DS : BP + DI + 16 bit displacement
ES

MOV AH,[BP+SI+29] The

or register
MOV AH,[SI+29+BP] order does
or not matter
MOV AH,[SI][BP]+29

55
 Based-Indexed Addressing Mode

MOV BX, 0600h

MOV SI, 0010h ; 4 records, 4 elements each.
MOV AL, [BX + SI + 3]

OR

MOV BX, 0600h

MOV AX, 004h ;
MOV CX,04;
MUL CX
MOV SI, AX
MOV AL, [BX + SI + 3]

56
Summary of the addressing modes
Addressing Mode Operand Default Segment

Register Reg None

Immediate Data None

Direct [offset] DS

Register Indirect [BX] DS

[SI] DS
[DI] DS
Based Relative [BX]+disp DS
[BP]+disp SS
Indexed Relative [DI]+disp DS
[SI]+disp DS
Based Indexed [BX][SI or DI]+disp DS
Relative [BP][SI or DI]+disp SS

57
 16 bit Segment Register Assignments

Type of Default Alternate Offset

Memory Segment Segment
Reference

Instruction Fetch CS none IP

Stack SS none SP,BP

Operations

General Data DS CS,ES,SS BX, address

String Source DS CS,ES,SS SI, DI, address

String ES None DI
Destination

Brey
58
 Segment override
Segment CS DS ES SS
Registers
Offset Register IP SI,DI,BX SI,DI,BX SP,BP

Instruction Examples Override Segment Used Default Segment

MOV AX,CS:[BP] CS:BP SS:BP

MOV DX,SS:[SI] SS:SI DS:SI

MOV AX,DS:[BP] DS:BP SS:BP

MOV CX,ES:[BX]+12 ES:BX+12 DS:BX+12

MOV SS:[BX][DI]+32,AX SS:BX+DI+32 DS:BX+DI+32

59
Example for default segments
• The following registers are used as offsets. Assuming that the
default segment used to get the logical address, give the segment
register associated?

a) BP b)DI c)IP d)SI, e)SP, f) BX

• Show the contents of the related memory locations after the

execution of this instruction
MOV [BP][SI]+10,DX
if DS=2000, SS=3000,CS=1000,SI=4000,BP=7000,DX=1299 (all
hex)

SS(0)=30000
30000+4000+7000+10=3B010

60
 Assembly Language
• There is a one-to-one relationship between assembly and machine
language instructions
• What is found is that a compiled machine code implementation of a
program written in a high-level language results in inefficient code
– More machine language instructions than an assembled version of an
equivalent handwritten assembly language program
• Two key benefits of assembly language programming
– It takes up less memory
– It executes much faster

61
 Languages in terms of applications

• One of the most beneficial uses of assembly language programming

is real-time applications.
• Real time means the task required by the application must be
completed before any other input to the program that will alter its
operation can occur
• For example the device service routine which controls the operation
of the floppy disk drive is a good example that is usually written in
assembly language
• Assembly language not only good for controlling hardware devices
but also performing pure software operations
– searching through a large table of data for a special string of characters
– Code translation from ASCII to EBCDIC
– Table sort routines
– Mathematical routines
• Assembly language: perform real-time operations
• High-level languages: Those operations mostly not critical in time.

62
 Converting Assembly Language
Instructions to Machine Code
OPCODE D W MOD REG R/M

• An instruction can be coded with 1 to 6 bytes

• Byte 1 contains three kinds of information:
– Opcode field (6 bits) specifies the operation such as add, subtract, or move
– Register Direction Bit (D bit)
• Tells the register operand in REG field in byte 2 is source or destination operand
– 1:Data flow to the REG field from R/M
– 0: Data flow from the REG field to the R/M
– Data Size Bit (W bit)
• Specifies whether the operation will be performed on 8-bit or 16-bit data
– 0: 8 bits
– 1: 16 bits
• Byte 2 has two fields:
– Mode field (MOD) – 2 bits
– Register field (REG) - 3 bits
– Register/memory field (R/M field) – 2 bits
63
Continued
• REG field is used to identify the register for the first operand

REG W=0 W=1

000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

64
Continued
• 2-bit MOD field and 3-bit R/M field together specify the second
operand

65
 Examples

• MOV BL,AL
• Opcode for MOV = 100010
• We’ll encode AL so
– D = 0 (AL source operand)
• W bit = 0 (8-bits)
• MOD = 11 (register mode)
• REG = 000 (code for AL)
• R/M = 011
OPCODE D W MOD REG R/M
100010 0 0 11 000 011
MOV BL,AL => 10001000 11000011 = 88 C3h
ADD AX,[SI] => 00000011 00000100 = 03 04 h
ADD [BX][DI] + 1234h, AX => 00000001 10000001 h
=> 01 81 34 12 h 66
 Software
• The sequence of commands used to tell a microcomputer what to do is
called a program
• Each command in a program is called an instruction
• 8088 understands and performs operations for 117 basic instructions
• The native language of the IBM PC is the machine language of the
8088
• A program written in machine code is referred to as machine code
• In 8088 assembly language, each of the operations is described by
alphanumeric symbols instead of just 0s or 1s.

ADD AX, BX
Source operand
Opcode
Destination operand
67
 Instructions

[LABEL:] MNEMONIC [OPERANDS] [; COMMENT]

Address identifier
Max 31 characters Does not generate any machine code
Instruction
: indicates it opcode
generating instruction

Ex. START: MOV AX,BX ; copy BX into AX

68
DEBUG program instruction set (page 825 mzd)

• Debug instructions
• List of commands
– a Assemble [address] you can type in code this way
– c range address ; compare c 100 105 200
– d [range] ; Dump d 150 15A
– e address [list] ; Enter e 100
– f Fill range list F 100 500 ‘ ‘
– g Go [=address] addresses runs the program
– h Value1 Value2 ; addition and subtraction H 1A 10
– i Input port I 3F8
– r Show & change registers Appears to show the same thing as t,
but doesn't cause any code to be executed.
– t Trace either from the starting address or current location.
– u UnAssemble

69
Some examples with debug
0100 mov ax,24b6
0103 mov di, 85c2
0106 mov dx,5f93
0109 mov sp,1236
010c push ax
010d push di
010e int 3

Display the stack contents after execution.

-D 1230 123F

70
Some examples with DEBUG
• 0100 mov al,9c
• 0102 mov dh,64
• 0104 add al,dh
• 0109 int 3

trace these three commands and observe the flags

• After the code has been entered with the A command

• Use CX to store data indicating number of bytes to save.
BX is the high word.
• Use N filename.com
• Then W command to write to file.
• L loads this file.

71
 Example

Copy the contents of a block of memory (16 bytes) starting at

location 20100h to another block of memory starting at 20120h

MOV AX,2000
MOV DS,AX 100-10f
MOV SI, 100
MOV DI, 120
MOV CX, 10
120-12f
NXTPT: MOV AH, [SI]
MOV [DI], AH
INC SI
INC DI
DEC CX
JNZ NXTPT
72
 Dec Hex Bin
2 2 00000010

ORG ; THREE
Assembly
Language
Programming

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
OBJECTIVES
this chapter enables the student to:
• Flag concepts
• Instruction Types in 8086
• Assembly language program basics.
• Flow charts summary
• Code simple Assembly language instructions.
• Assemble, link, and run a simple Assembly language
program.
• Procedures
• Code control transfer instructions such as conditional
and unconditional jumps and call instructions.
The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
FLAG REGISTER

• Many Assembly language instructions alter flag

register bits & some instructions function differently
based on the information in the flag register.
• The flag register is a 16-bit register sometimes
referred to as the status register.
– Although 16 bits wide, only some of the bits are used.
• The rest are either undefined or reserved by Intel.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
FLAG REGISTER

• Six flags, called conditional flags, indicate some

condition resulting after an instruction executes.

– These six are CF, PF, AF, ZF, SF, and OF.
– The remaining three, often called control flags, control
the operation of instructions before they are executed.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
bits of the flag register

• Flag register bits used in x86 Assembly language

programming, with a brief explanation each:
– CF (Carry Flag) - Set when there is a carry out, from d7 after an
8-bit operation, or d15 after a 16-bit operation.
• Used to detect errors in unsigned arithmetic operations.
– PF (Parity Flag) - After certain operations, the parity
of the result's low-order byte is checked.
• If the byte has an even number of 1s, the parity flag is set to 1;
otherwise, it is cleared.
– AF (Auxiliary Carry Flag) - If there is a carry from d3 to d4 of an
operation, this bit is set; otherwise, it is cleared.
• Used by instructions that perform BCD (binary coded
decimal) arithmetic.
The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
bits of the flag register

• Flag register bits used in x86 Assembly language

programming, with a brief explanation each:
– ZF (Zero Flag) - Set to 1 if the result of an arithmetic or logical operation is zero;
otherwise, it is cleared.

– SF (Sign Flag) - Binary representation of signed numbers uses the most significant bit as the
sign bit.
• After arithmetic or logic operations, the status of this sign
bit is copied into the SF, indicating the sign of the result.
– TF (Trap Flag) - When this flag is set it allows the program to single-step, meaning to execute
one instruction at a time.
• Single-stepping is used for debugging purposes.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
bits of the flag register

• Flag register bits used in x86 Assembly language

programming, with a brief explanation each:
– IF (Interrupt Enable Flag) - This bit is set or cleared to enable/disable only
external maskable interrupt requests.

– DF (Direction Flag) - Used to control the direction of string operations.

– OF (Overflow Flag) - Set when the result of a signed number operation is too large, causing
the high-order
bit to overflow into the sign bit.
• Used only to detect errors in signed arithmetic operations.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
flag register and ADD instruction

• Flag bits affected by the ADD instruction:

– CF (carry flag); PF (parity flag); AF (auxiliary carry flag).
– ZF (zero flag); SF (sign flag); OF (overflow flag).

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
flag register and ADD instruction

• Flag bits affected by the ADD instruction:

– CF (carry flag); PF (parity flag); AF (auxiliary carry flag).
– ZF (zero flag); SF (sign flag); OF (overflow flag).

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
flag register and ADD instruction

• It is important to note differences between 8- and

16-bit operations in terms of impact on the flag bits.
– The parity bit only counts the lower 8 bits of the result
and is set accordingly.

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flag register and ADD instruction

• The carry flag is set if there is a carry beyond bit d15

instead of bit d7.
– Since the result of the entire 16-bit operation is zero (meaning
the contents of BX), ZF is set to high.

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flag register and ADD instruction

• Instructions such as data transfers (MOV) affect no flags.

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use of the zero flag for looping

• A widely used application of the flag register is the use of

the zero flag to implement program loops.
– A loop is a set of instructions repeated a number of times
• More on details on LOOPS later!

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use of the zero flag for looping

• As an example, to add 5 bytes of data, a counter can be

used to keep track of how many times the loop needs to
be repeated.
– Each time the addition is performed the counter
is decremented and the zero flag is checked.
• When the counter becomes zero, the zero flag is
set (ZF = 1) and the loop is stopped.

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use of the zero flag for looping

• Register CX is used to hold the counter.

– BX is the offset pointer.
• (SI or DI could have been used instead)

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use of the zero flag for looping

• AL is initialized before the start of the loop

– In each iteration, ZF is checked by the JNZ instruction
• JNZ stands for "Jump Not Zero“, meaning that if ZF = 0,
jump to a new address.
• If ZF = 1, the jump is not performed, and the instruction
below the jump will be executed.

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use of the zero flag for looping

• JNZ instruction must come immediately after the

instruction that decrements CX.
– JNZ needs to check the effect of "DEC CX" on ZF.
• If any instruction were placed between them, that instruction might
affect the zero flag.

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Addressing Modes

• Register Addressing Mode

– MOV AX, BX
– MOV ES,AX
– MOV AL,BH
• Immediate Addressing Mode
– MOV AL,15h
– MOV AX,2550h
– MOV CX,625

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Direct Addressing Mode

MOV CX, [address]

BEED Example:
MOV AL,[03]
AL=?
02003 FF

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19
Register Indirect Addressing Mode

B
X
MOV AX, DI
SI

BEED

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Example for Register Indirect Addressing

• Assume that DS=1120, SI=2498 and AX=17FE show the memory locations
after the execution of:

MOV [SI],AX

DS (Shifted Left) + SI = 13698.

With little endian convention:
Low address 13698 → FE
High Address 13699 → 17

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21
Based-Relative Addressing Mode

DS:BX
MOV AH, [ SS:BP ] + 1234h

3AH
BX
+

AX

DS

1234

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Indexed Relative Addressing Mode

MOV AH, [ SI
DI
] + 1234h

Example: What is the physical address MOV [DI-8],BL if DS=200 & DI=30h ?
DS:200 shift left once 2000 + DI + -8 = 2028

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Based-Indexed Relative Addressing Mode

• Based Relative + Indexed Relative

• We must calculate the PA (physical address)

CS
SS BX SI 8 bit displacement
PA= DS : BP + DI + 16 bit displacement
ES

MOV AH,[BP+SI+29] The register

or order does not
MOV AH,[SI+29+BP] matter
or
MOV AH,[SI][BP]+29

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Based-Indexed Addressing Mode

MOV BX, 0600h

MOV SI, 0010h ; 4 records, 4 elements each.
MOV AL, [BX + SI + 3]

OR

MOV BX, 0600h

MOV AX, 004h ;
MOV CX,04;
MUL CX
MOV SI, AX
MOV AL, [BX + SI + 3]

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25
Summary of the addressing modes

Addressing Mode Operand Default Segment

Register Reg None

Immediate Data None

Direct [offset] DS

Register Indirect [BX] DS

[SI] DS
[DI] DS
Based Relative [BX]+disp DS
[BP]+disp SS
Indexed Relative [DI]+disp DS
[SI]+disp DS
Based Indexed [BX][SI or DI]+disp DS
Relative [BP][SI or DI]+disp SS

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26
 16 bit Segment Register Assignments
Segment CS DS ES SS
Registers
Offset IP SI,DI,BX SI,DI,BX SP,BP
Register
Type of Memory Default Segment Alternate Segment Offset
Reference

Instruction Fetch CS none IP

Stack Operations SS none SP,BP

General Data DS CS,ES,SS BX, address

String Source DS CS,ES,SS SI, DI, address

String Destination ES None DI

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27
Segment override

Instruction Examples Override Segment Used Default Segment

MOV AX,CS:[BP] CS:BP SS:BP

MOV DX,SS:[SI] SS:SI DS:SI

MOV AX,DS:[BP] DS:BP SS:BP

MOV CX,ES:[BX]+12 ES:BX+12 DS:BX+12

MOV SS:[BX][DI]+32,AX SS:BX+DI+32 DS:BX+DI+32

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Example for default segments

• The following registers are used as offsets. Assuming that the default
segment used to get the logical address, give the segment register
associated?

a) BP b)DI c)IP d)SI, e)SP, f) BX

• Show the contents of the related memory locations after the execution of
this instruction
MOV [BP][SI]+10,DX
if DS=2000, SS=3000,CS=1000,SI=4000,BP=7000,DX=1299 (all hex)

SS(0)=30000
30000+4000+7000+10=3B010

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29
Assembly Language

• There is a one-to-one relationship between assembly and

machine language instructions
• What is found is that a compiled machine code
implementation of a program written in a high-level
language results in inefficient code
– More machine language instructions than an assembled version of
an equivalent handwritten assembly language program
• Two key benefits of assembly language programming
– It takes up less memory
– It executes much faster

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30
Languages in terms of applications

• One of the most beneficial uses of assembly language programming is real-time

applications.
• Real time means the task required by the application must be completed before any
other input to the program that will alter its operation can occur
• For example the device service routine which controls the operation of the floppy
disk drive is a good example that is usually written in assembly language
• Assembly language not only good for controlling hardware devices but also
performing pure software operations
– searching through a large table of data for a special string of characters
– Code translation from ASCII to EBCDIC
– Table sort routines
– Mathematical routines
• Assembly language: perform real-time operations
• High-level languages: Those operations mostly not critical in time.

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31
 Converting Assembly Language
Instructions to Machine Code
OPCODE D W MOD REG R/M

• An instruction can be coded with 1 to 6 bytes

• Byte 1 contains three kinds of information:
– Opcode field (6 bits) specifies the operation such as add, subtract, or move
– Register Direction Bit (D bit)
• Tells the register operand in REG field in byte 2 is source or destination operand
– 1:Data flow to the REG field from R/M
– 0: Data flow from the REG field to the R/M
– Data Size Bit (W bit)
• Specifies whether the operation will be performed on 8-bit or 16-bit data
– 0: 8 bits
– 1: 16 bits
• Byte 2 has two fields:
– Mode field (MOD) – 2 bits
– Register field (REG) - 3 bits
– Register/memory field (R/M field) – 2 bits

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32
Continued

• REG field is used to identify the register for the first operand

REG W=0 W=1

000 AL AX
001 CL CX
010 DL DX

011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

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33
Continued

• 2-bit MOD field and 3-bit R/M field together specify the second operand

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34
2.6: FULL SEGMENT DEFINITION
the emu8086 assembler
• A simple, popular assembler for 8086 Assembly
language programs is called emu8086.

See emu8086 screenshots on page 80 - 82 of your textbook.

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2.6: FULL SEGMENT DEFINITION
the emu8086 assembler

Download the emu8086

assembler from this website:
http://www.emu8086.com

See a Tutorial on how to use it at:

http://www.MicroDigitalEd.com

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2.6: FULL SEGMENT DEFINITION
EXE vs. COM files
• The EXE file is used widely as it can be of any size.
– There are occasions when, due to a limited amount of memory,
one needs to have very compact code.
• COM files must fit in a single segment.
– The x86 segment size is 64K bytes, thus the COM file cannot be
larger than 64K.
• To limit the size to 64K requires defining the data inside
the code segment and using the end area
of the code segment for the stack.
– In contrast to the EXE file, the COM file has no separate data
segment definition.

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2.6: FULL SEGMENT DEFINITION
EXE vs. COM files
• The header block, which occupies 512 bytes of memory, precedes every EXE
file.
– It contains information such as size, address location
in memory, and stack address of the EXE module.
– The COM file does not have a header block.

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2.7: FLOWCHARTS AND PSEUDOCODE
structured programming

• Structured programming uses three basic types

of program control structures:
– Sequence.
– Control.
– Iteration.

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2.7: FLOWCHARTS AND PSEUDOCODE
structured programming
• Principles a structured program should follow:
– The program should be designed before it is coded.
• By using flowcharting or pseudocode, the design is clear
those coding, as well as those maintaining the program later.
– Use comments within the program and documentation.
• This will help other figure out what the program does
and how it does it.
– The main routine should consist primarily of calls to subroutines that
perform the work of the program.
• Sometimes called top-down programming.
• Using subroutines to accomplish repetitive tasks saves
time in coding, and makes the program easier to read.

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2.7: FLOWCHARTS AND PSEUDOCODE

• Principles a structured program should follow:

– Data control is very important.
• The programmer should document the purpose of each variable, and which
subroutines might alter its value.
• Each subroutine should document its input/output variables, and which input
variables might be altered within it.

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2.7: FLOWCHARTS AND PSEUDOCODE
flowcharts

• Flowcharts use graphic symbols to

represent different types of program
operations.
– The symbols are connected together
to show the flow of execution of the
program.
• Flowcharting has been standard
industry practice for decades.
– Flowchart templates help you draw
the symbols quickly and neatly.

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2.7: FLOWCHARTS AND PSEUDOCODE
pseudocode
• An alternative to flowcharts, pseudocode, involves
writing brief descriptions of the flow of the code.
– SEQUENCE is executing instructions one after the other.

Figure 2-15
SEQUENCE
Pseudocode vs. Flowchart

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2.7: FLOWCHARTS AND PSEUDOCODE
pseudocode
• An alternative to flowcharts, pseudocode, involves
writing brief descriptions of the flow of the code.
– IF-THEN-ELSE and IF-THEN are control programming structures,
which can indicate one statement or a group
of statements.

Figure 2-16
IF-THEN-ELSE
Pseudocode vs. Flowchart

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2.7: FLOWCHARTS AND PSEUDOCODE
pseudocode
• An alternative to flowcharts, pseudocode, involves writing brief
descriptions of the flow of the code.
– IF-THEN-ELSE and IF-THEN are control programming structures,
which can indicate one statement or a group
of statements.

Figure 2-17
IF-THEN
Pseudocode vs. Flowchart

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2.7: FLOWCHARTS AND PSEUDOCODE
pseudocode
• An alternative to flowcharts, pseudocode, involves writing brief
descriptions of the flow of the code.
– REPEAT-UNTIL and WHILE-DO are iteration control structures,
which execute a statement or group of statements repeatedly.

Figure 2-18
REPEAT-UNTIL
Pseudocode vs. Flowchart

REPEAT-UNTIL structure always

executes the statement(s) at least
once, and checks the condition
after each iteration.

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2.7: FLOWCHARTS AND PSEUDOCODE
pseudocode
• An alternative to flowcharts, pseudocode, involves
writing brief descriptions of the flow of the code.
– REPEAT-UNTIL and WHILE-DO are iteration control structures,
which execute a statement or group of statements repeatedly.

Figure 2-19
WHILE-DO
Pseudocode vs. Flowchart

WHILE-DO may not execute the

statement(s) at all, as the condition
is checked at the beginning of
each iteration.

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2.7: FLOWCHARTS AND PSEUDOCODE
control structures

Flowchart vs. pseudocode for Program

showing steps for
initializing/decrementing counters.
Housekeeping, such as initializing the
data segment register in the MAIN
procedure are not included in the
flowchart or pseudocode.

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2.7: FLOWCHARTS AND PSEUDOCODE
control structures

• The purpose of flowcharts or pseudocode is to show the program

flow, and what the program does.
– Pseudocode gives the same information as a flowchart,
in a more compact form.
• Often written in layers, in a top-down manner.
– Code specific to a certain language or operating platform
is not described in the pseudocode or flowchart.
• Ideally, one could take a flowchart or pseudocode
and code the program in any language.

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Assembly Language

• There is a one-to-one relationship between assembly and

machine language instructions
• What is found is that a compiled machine code
implementation of a program written in a high-level language
results in inefficient code
– More machine language instructions than an assembled
version of an equivalent handwritten assembly language
program
• Two key benefits of assembly language programming
– It takes up less memory
– It executes much faster

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2.2: ASSEMBLE, LINK, AND RUN A PROGRAM

• There are assembler & linker programs.

– Many editors or word processors can be used to create
and/or edit the program, and produce an ASCII file.
– The steps to create an executable Assembly language program
are as follows:

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2.2: ASSEMBLE, LINK, AND RUN A PROGRAM

• The source file must end in ".asm“.

– The ".asm" file is assembled by an assembler, like MASM or
EMU8086 etc.
• The assembler will produce an object file and a list file, along with
other files useful to the programmer.
• The extension for the object file must be ".obj".
– This object file is input to the LINK program, to produce
the executable program that ends in ".exe".
– The ".exe" file can be run (executed) by the microprocessor.

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ORG 100h is a compiler directive (it tells compiler how to handle
the source code). This directive is very important when you work
with variables. It tells compiler that the executable file will be loaded
at the offset of 100h (256 bytes), so compiler should calculate the
correct address for all variables when it replaces the variable names
with their offsets. Directives are never converted to any real
machine code.
Why executable file is loaded at offset of 100h? Operating system
keeps some data about the program in the first 256 bytes of the

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2.2: ASSEMBLE, LINK, AND RUN A PROGRAM

Before feeding the ".obj" file

into LINK, all syntax errors
must be corrected.
Fixing these errors will not
guarantee the program will
work as intended, as the program
may contain conceptual errors.

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2.2: ASSEMBLE, LINK, AND RUN A PROGRAM
LINKing the program

• The assembler creates the opcodes, operands & offset addresses under the
".obj" file.
• The LINK program produces the ready-to-run program with the ".exe"
(EXEcutable) extension.
– The LINK program sets up the file so it can be loaded
by the OS and executed.
• The program can be run at the OS level, using the following command: C>myfile
– When the program name is typed in at the OS level, the OS loads the
program in memory.
• Referred to as mapping, which means that the program is mapped into
the physical memory of the PC.

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2.2: ASSEMBLE, LINK, AND RUN A PROGRAM
TITLE directives

– It is common to put the NAME of the PROGRAM

immediately after the TITLE pseudo-instruction.
• And a brief description of the function of the program.
– The text after the TITLE pseudo-instruction cannot be
exceed 60 ASCII characters.

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Software

• The sequence of commands used to tell a microcomputer what to do is

called a program
• Each command in a program is called an instruction
• 8088 understands and performs operations for 117 basic instructions
• The native language of the IBM PC is the machine language of the
8088
• A program written in machine code is referred to as machine code
• In 8088 assembly language, each of the operations is described by
alphanumeric symbols instead of just 0s or 1s.

ADD AX, BX

Opcode Source operand

Destination operand

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2.0: ASSEMBLY LANGUAGE

• An Assembly language program is a series of statements, or lines.

– Either Assembly language instructions, or statements called
directives.
• Directives (pseudo-instructions) give directions to the
assembler about how it should translate the Assembly
language instructions into machine code.

• Assembly language instructions consist of four fields:

[label:] mnemonic [operands][;comment]
– Brackets indicate that the field is optional.
• Do not type in the brackets.

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2.1: DIRECTIVES AND A SAMPLE PROGRAM

• The program loads AL & BL with DATA1 & DATA2,

ADDs them together, and stores the result in SUM.

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2.1: DIRECTIVES AND A SAMPLE PROGRAM
assembly language instructions

[label:] mnemonic [operands][;comment]

• The label field allows the program to refer to a line of
code by name.
– The label field cannot exceed 31 characters.
• A label must end with a colon when it refers to an
opcode generating instruction.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.1: DIRECTIVES AND A SAMPLE PROGRAM
assembly language instructions
[label:] mnemonic [operands][;comment]
• The mnemonic (instruction) and operand(s) fields
together accomplish the tasks for which the program
was written.

– The mnemonic opcodes are ADD and MOV.

– "AL,BL" and "AX,6764" are the operands.
• Instead of a mnemonic and operand, these fields could
contain assembler pseudo-instructions, or directives.
• Directives do not generate machine code and are used
only by the assembler as opposed to instructions.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.1: DIRECTIVES AND A SAMPLE PROGRAM
assembly language instructions
[label:] mnemonic [operands][;comment]

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.1: DIRECTIVES AND A SAMPLE PROGRAM
assembly language instructions

[label:] mnemonic [operands][;comment]

• The comment field begins with a ";" and may be at the
end of a line or on a line by themselves.
– The assembler ignores comments.
• Comments are optional, but highly recommended to
make it easier to read and understand the program.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.4: CONTROL TRANSFER INSTRUCTIONS
rules for names in Assembly language

• The names used for labels in Assembly language programming consist of…
– Alphabetic letters in both upper- and lowercase.
– The digits 0 through 9.
– Question mark (?); Period (.); At (@)
– Underline (_); Dollar sign ($)
• Each label name must be unique.
– They may be up to 31 characters long.
• The first character must be an alphabetic or special character.
– It cannot be a digit.
– The period can only be used as the first character.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
x86 data types

• The 8088/86 processor supports many data types.

– Data types can be 8- or 16-bit, positive or negative.
• The programmer must break down data larger than
16 bits (0000 to FFFFH, or 0 to 65535 in decimal).
– A number less than 8 bits wide must be coded as
an 8-bit register with the higher digits as zero.
• A number is less than 16 bits wide must use all 16 bits.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
Compiler directives

Syntax for a variable declaration:

name DB value

name DW value

DB - stays for Define Byte.

DW - stays for Define Word.

name - can be any letter or digit combination, though it should start with a letter.
It's possible to declare unnamed variables by not specifying the name (this variable
will have an address but no name).

value - can be any numeric value in any supported numbering system

(hexadecimal, binary, or decimal), or "?" symbol for variables that are not
initialized.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
DB define byte

• One of the most widely used data directives, it allows

allocation of memory in byte-sized chunks.
– This is the smallest allocation unit permitted.
– DB can define numbers in decimal, binary, hex, & ASCII.
• D after the decimal number is optional.
• B (binary) and H (hexadecimal) is required.
• To indicate ASCII, place the string in single quotation marks.
• DB is the only directive that can be used to define ASCII
strings larger than two characters.
– It should be used for all ASCII data definitions.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
DB define byte
• Some DB examples:

– Single or double quotes can be used around ASCII

strings.
• Useful for strings, which should contain a single quote,
such as "O'Leary".

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.1: DIRECTIVES AND A SAMPLE PROGRAM
data segment

• The DB directive is used by the assembler to allocate

memory in byte-sized chunks.
– Each is defined as DB (define byte).
• Memory can be allocated in different sizes.
– Data items defined in the data segment will be
accessed in the code segment by their labels.
• DATA1 and DATA2 are given initial values in the data
section.
• SUM is not given an initial value.
– But storage is set aside for it.

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Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
DataTypes and Data Definition

DATA1 DB 25
DATA2 DB 10001001b
DATA3 DB 12h
ORG 0010h ;indicates distance from initial DS location
DATA4 DB “2591”
ORG 0018h ;indicates distance from initial DS location
DATA5 DB ?

This is how data is initialized in the data segment

0000 19
0001 89
0002 12
0010 32 35 39 31
0018 00

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70
DB DW DD

; how it looks like in memory

.data
MESSAGE2 DB '1234567' 31 32 33 34 35 36 37

MESSAGE3 DW 6667H 67 66

data1 db 1,2,3 123

db 45h 45

db 'a' 61

db 11110000b F0

data2 dw 12,13 0C 00 0D 00

dw 2345h 45 23

dd 300h 00 03 00 00

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Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prent ic eHall - Upper Saddle River, NJ 07458
71
More Examples

DB 6 DUP(FFh); fill 6 bytes with ffh

DW 954
DW 253Fh ; allocates two bytes
DW 253Fh

DD 5C2A57F2h ;allocates four bytes

DQ 12h ;allocates eight bytes

COUNTER1 DB COUNT
COUNTER2 DB COUNT

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Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prent ic eHall - Upper Saddle River, NJ 07458
72
2.5: DATA TYPES AND DATA DEFINITION
DB define byte
• List file for DB examples.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
DW define word
• DW is used to allocate memory 2 bytes (one word) at a
time:

• List file for DW examples.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
EQU equate

• EQU associates a constant value with a data label.

– When the label appears in the program, its constant value will be
substituted for the label.
– Defines a constant without occupying a memory location.
• EQU directive assigns a symbolic name to a string or constant.
– Maxint equ 0ffffh
– COUNT EQU 2
• EQU for the counter constant in the immediate addressing mode:
COUNT EQU 25
• Assume a constant (a fixed value) used in many different places in the
data and code segments. By use of EQU, one can change it once and
the assembler will change all of them.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
DD define doubleword
• The DD directive is used to allocate memory locations that are 4 bytes (two
words) in size.
– Data is converted to hex & placed in memory locations
• Low byte to low address and high byte to high address.

• List file for DD examples.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
DQ define quadword
• DQ is used to allocate memory 8 bytes (four words) in size, to
represent any variable up to 64 bits wide:

• List file for DQ examples.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
directives
• Figure 2-7 shows the memory dump of the data section,
including all the examples in this section.
– It is essential to understand the way operands are stored in
memory.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
directives
• All of the data directives use the little endian format.
– For ASCII data, only DB can define data of any length.
• Use of DD, DQ, directives for ASCII strings of more
than 2 bytes gives an assembly error.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
directives
• Review "DATA20 DQ 4523C2", residing in memory
starting at offset 00C0H.
– C2, the least significant byte, is in location 00C0, with
23 in 00C1, and 45, the most significant byte, in 00C2.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
directives
• When DB is used for ASCII numbers, it places them
backwards in memory.
– Review "DATA4 DB '2591'" at origin 10H:32,
• ASCII for 2, is in memory location 10H;35; for 5, in 11H; etc.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
More assembly – OFFESET, SEG, EQU

• OFFSET
– The offset operator returns the distance of a label or variable from the
beginning of its segment. The destination must be 16 bits
– mov BX, offset count
• SEG
– The segment operator returns the segment part of a label or variable’s
address.
Push DS
Mov AX, seg array
Mov DS, AX
Mov BX, offset array
.
Pop DS

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82
DUP (Duplicate)

• DUP operator only appears after a storage allocation directive.

– db 20 dup(?)

number DUP ( value(s) )

number - number of duplicate to make (any constant value).
value - expression that DUP will duplicate.

for example:
c DB 5 DUP(9)
is an alternative way of declaring:
c DB 9, 9, 9, 9, 9

one more example:

d DB 5 DUP(1, 2)
is an alternative way of declaring:
d DB 1, 2, 1, 2, 1, 2, 1, 2, 1, 2

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.5: DATA TYPES AND DATA DEFINITION
DUP duplicate

• DUP will duplicate a given number of characters.

– Two methods of filling six memory locations with FFH.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
5. : DATA TYPES AND DATA DEFINITION
DUP duplicate
• List file for DUP examples.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
The PTR Operator - Byte or word or doubleword?

• INC [20h] ; is this byte/word/dword? or

• MOV [SI],5
– Is this byte 05?
– Is this word 0005?
– Or is it double word 00000005?

• To clarify we use the PTR operator

– INC BYTE PTR [20h]
– INC WORD PTR [20h]
– INC DWORD PTR [20h]
• or for the MOV example:
– MOV byte ptr [SI],5
– MOV word ptr[SI],5

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Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prent ic eHall - Upper Saddle River, NJ 07458
86
The PTR Operator

• Would we need to use the PTR

operator in each of the following?

MOV AL,BVAL MOV AL,BVAL

MOV DL,[BX]
MOV DL,[BX]
SUB [BX],byte ptr 2
SUB [BX],2 MOV CL,byte ptr WVAL
ADD AL,BVAL+1
MOV CL,WVAL
ADD AL,BVAL+1

.data
BVAL DB 10H,20H
WVAL DW 1000H

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87
ORG 100h MOV AL, var1 MOV BX, var2 RET ; stops the program. VAR1 DB 7 var2 DW 1234h

2.5: DATA TYPES AND DATA DEFINITION

ORG origin
• ORG is used to indicate the beginning of the offset
address.
– ORG 100h is a compiler directive (it tells compiler how to handle the source code). This
directive is very important when you work with variables. It tells compiler that the executable
file will be loaded at the offset of 100h (256 bytes), so compiler should calculate the correct
address for all variables when it replaces the variable names with their offsets. Directives are
never converted to any real machine code.

ORG 100h

MOV AL, var1

MOV BX, var2

RET ; stops the program.

VAR1 DB 7
var2 DW 1234h

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Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
Equivalent code using only DB

ORG 100h

DB 0A0h
DB 08h
DB 01h

DB 8Bh
DB 1Eh
DB 09h
DB 01h

DB 0C3h

DB 7

DB 34h
DB 12h

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
Procedures
• A procedure is a group of instructions designed to
accomplish a specific function.
– A code segment is organized into several small procedures to
make the program more structured.
• Every procedure must have a name defined by the PROC
directive.
– Followed by the assembly language instructions, and closed by
the ENDP directive.
• The PROC and ENDP statements must have the same label.
– The PROC directive may have the option FAR or NEAR.
• The OS requires the entry point to the user program
to be a FAR procedure.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
Procedures

• The syntax for procedure declaration:

name PROC
; here goes the code
; of the procedure ...
RET
name ENDP

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
Example Proc

ORG 100h
main proc ; this is optional but very strongly recommended
MOV AL, 1
MOV BL, 2

CALL m2
CALL m2
CALL m2
CALL m2

RET ; return to operating system.

main endp ; this is optional but very strongly recommended

m2 PROC
MUL BL ; AX = AL * BL.
RET ; return to caller.
m2 ENDP

END ;main program should end with END

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
assembly language subroutines

It is common to have one main program and

many subroutines to be called from the main.
Each subroutine can be a separate module,
tested separately, then brought together.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.3: MORE SAMPLE PROGRAMS
various approaches to Program 2-1
• Variations of Program 2-1 clarify use of addressing
modes, and show that the x86 can use any general-
purpose register for arithmetic and logic operations.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.3: MORE SAMPLE PROGRAMS
• Program 2-1, and the list file generated when the program was assembled.
TITLE ADD_5_BYTES
org 100h
DATA_IN DB 25H,12H,15H,1FH,2BH
SUM DB ?
MAIN PROC FAR
MOV AX,@DATA
MOV DS, AX
MOV CX,5
MOV BX, OFFSET DATA_IN
MOV AL,0
CALL ADDC
MOV SUM, AL
MOV AH, 4CH
INT 21H
RET
MAIN ENDP
ADDC PROC ; A PROCEDURE USED!!!!!!
AGAIN: ADD AL, [BX]
INC BX
DEC CX
JNZ AGAIN
RET
ADDC ENDP
END

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.3: MORE SAMPLE PROGRAMS
analysis of Program 2-1
• Program 2-1, explained instruction by instruction:
– "MOV CX,05" will load the value 05 into the CX register.
• Used by the program as a counter for iteration (looping).
– "MOV BX,OFFSET DATA_IN" will load into BX the
offset address assigned to DATA_IN.
• The assembler starts at offset 0000? and uses memory for
the data, then assigns the next available offset memory for SUM (in this
case, 0005).
– "ADD AL,[BX]" adds the contents of the memory location pointed at by the
register BX to AL.
• Note that [BX] is a pointer to a memory location.
– "INC BX" increments the pointer by adding 1 to BX.
• This will cause BX to point to the next data item. (next byte)

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.3: MORE SAMPLE PROGRAMS
analysis of Program 2-1
• Program 2-1, explained instruction by instruction:

– "DEC CX" will decrement (subtract 1 from) the CX

counter and set the zero flag high if CX becomes zero.
– "JNZ AGAIN" will jump back to the label AGAIN as
long as the zero flag is indicating that CX is not zero.
• "JNZ AGAIN" will not jump only after the zero flag has
been set high by the "DEC CX" instruction (CX becomes
zero).
– When CX becomes zero, this means that the loop is
completed and all five numbers have been added to AL

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.3: MORE SAMPLE PROGRAMS
analysis of Program 2-2
Write a program that adds four words of data and saves the result. The values will be 234DH,1DE6H,
3BC7H and 566AH. Verify the result is: D364H
TITLE ADDS_4_words_data
ORG 100H
DATA_IN DW 234DH, 1DE6H, 3BC7H,566AH
ORG 10H
SUM DW ? ; The 16-bit data (a word) is stored with the low-order byte first, referred to as "little
endian.“
MAIN PROC FAR
MOV AX,@DATA
MOV DS, AX
MOV CX,4
MOV DI, OFFSET DATA_IN
MOV BX,00 ADD_16 PROC
CALL ADD_16 ADD_LP: ADD BX,[DI]
MOV SI, OFFSET SUM INC DI
MOV [SI], BX INC DI
DEC CX
MOV AH, 4CH
JNZ ADD_LP
INT 21H RET
MAIN ENDP ENDP ADD_16
END

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.3: MORE SAMPLE PROGRAMS
analysis of Program 2-2
• The address pointer is incremented twice, since the operand being
accessed is a word (two bytes).
– The program could have used "ADD DI,2" instead of using "INC
DI" twice.
• "MOV SI,OFFSET SUM" was used to load the pointer for the
memory allocated for the label SUM.
• "MOV [SI],BX" moves the contents of register BX to memory
locations with offsets 0010 and 0011.
• Program 2-2 uses the ORG directive to set the offset addresses for
data items.
– This caused SUM to be stored at DS:0010.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
Example program

Copy the contents of a block of memory (X bytes) starting at location SI to another

block of memory starting at DIh

MOV AX,2000
MOV DS,AX 100-10f
MOV SI, 100
MOV DI, 120
MOV CX, 10
NXTPT: MOV AH, [SI]
MOV [DI], AH 120-12f
INC SI
INC DI
DEC CX
JNZ NXTPT

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prent ic eH all- Upper Saddle River, NJ 07458
10 0
2.3: MORE SAMPLE PROGRAMS
analysis of Program 2-3
• ACTUAL EXAMPLE TO RUN
TITLE TRANSFER_6_BYTES
ORG 100H
DATA_IN DB 25H,4FH,85H,1FH,2BH,0C4H
ORG 10H
COPY DB 6 DUP (?)
MAIN PROC FAR
MOV AX,@DATA
MOV DS, AX
MOV SI,OFFSET DATA_IN
MOV DI,OFFSET COPY
MOV CX, 06H
MOV_LOOP: MOV AL,[SI]
MOV [DI],AL
INC SI
INC DI
DEC CX
JNZ MOV_LOOP
MOV AH,4CH
INT 21H
MAIN ENDP
END

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.3: MORE SAMPLE PROGRAMS
analysis of Program 2-3

• C4 was coded in the data segments as 0C4.

– Indicating that C is a hex number and not a letter.
• Required if the first digit is a hex digit A through F.
• This program uses registers SI & DI as pointers
to the data items being manipulated.
– The first is a pointer to the data item to be copied.
– The second points to the location the data is copied to.
• With each iteration of the loop, both data pointers
are incremented to point to the next byte.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.6: FULL SEGMENT DEFINITION
segment definition
• The SEGMENT and ENDS directives indicate the beginning &ending of a
segment, in this format:

– The label, or name, must follow naming conventions and be unique.

• The [options] field gives important information to the
assembler for organizing the segment, but is not required.
– The ENDS label must be the same label as in the SEGMENT directive.
• In full segment definition, the ".MODEL" directive is not used.

LABEL SEGMENT DATA

DATA_IN DB 25H,4FH,85H,1FH,2BH,0C4H
ORG 10H
COPY DB 6 DUP (?)
END SEGMENT DATA

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.6: FULL SEGMENT DEFINITION
segment definition

Figure 2-8

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.6: FULL SEGMENT DEFINITION
segment definition
• using full segment definition.

See the entire program listing on page 78 of your textbook.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.6: FULL SEGMENT DEFINITION
segment definition
• rewritten using full segment definition.
TITLE TRANSFER
STSEG SEGMENT
DB 32 DUP (?)
STSEG ENDS
DTSEG SEGMENT
ORG 10H
DATA_IN DB 25H,4FH,85H,1FH,2BH,0C4H
ORG 28H
COPY DB 6 DUP (?)
DTSEG ENDS
CDSEG SEGMENT
MAIN PROC FAR
ASSUME CS:CDSEG, DS:DTSEG, SS:STSEG
MOV AX,DTSEG
MOV DS,AX
MOV SI, OFFSET DATA_IN
MOV DI, OFFSET COPY
MOV CX,06H
MOV_LOOP: MOV AL,[SI]
MOV [DI],AL
INC SI
INC DI
DEC CX
JNZ MOV_LOOP
MOV AH,4CH
INT 21H
MAIN ENDP
CDSEG ENDS
END MAIN
The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.6: FULL SEGMENT DEFINITION
stack segment definition
• The stack segment shown contains the line
"DB 64 DUP (?)" to reserve 64 bytes of memory
for the stack.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.6: FULL SEGMENT DEFINITION
data segment definition
• In full segment definition, the SEGMENT directive names the data
segment and must appear before the data.
– The ENDS segment marks the end of the data segment:

• The code segment also begins and ends with SEGMENT and ENDS
directives:

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.6: FULL SEGMENT DEFINITION
code segment definition
• Immediately after PROC, the ASSUME directive, associates
segments with specific registers.
– By assuming the segment register is equal to the segment
labels used in the program.
• If an extra segment had been used, ES would
also be included in the ASSUME statement.
– ASSUME tells the assembler which of the segments, defined by
SEGMENT, should be used.
• Also helps the assembler to calculate the offset
addresses from the beginning of that segment.
• In "MOV AL, [BX] " the BX register is the offset of the data
segment.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.6: FULL SEGMENT DEFINITION
code segment definition

• On transfer of control from OS to the program, of

the three segment registers, only CS and SS have the
proper values.
– The DS value (and ES) must be initialized by the program.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
 code segment
main proc
start:
data segment mov ax,data
DATA_IN DW 234DH, 1DE6H, 3BC7H,566AH mov ds,ax
SUM DW ? ;referred to as "little endi MOV CX,4
ends MOV DI, OFFSET DATA_IN
MOV BX,00
ADD_LP: ADD BX,[DI]
stack segment INC DI
dw 128 dup(0) INC DI DEC
ends CX JNZ
ADD_LP
MOV SI, OFFSET SUM
MOV [SI], BX
MOV AH, 4CH
INT 21H
ret
end main
ends

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.4: CONTROL TRANSFER INSTRUCTIONS
conditional jumps
• Conditional jumps have mnemonics such as JNZ (jump not zero)
and JC (jump if carry).
– In the conditional jump, control is transferred to a new location
if a certain condition is met.
– The flag register indicates the current condition.
• For example, with "JNZ label", the processor looks at the zero flag
to see if it is raised.
– If not, the CPU starts to fetch and execute instructions from the
address of the label.
– If ZF = 1, it will not jump but will execute the next instruction
below the JNZ.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.4: CONTROL TRANSFER INSTRUCTIONS
conditional jumps

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.4: CONTROL TRANSFER INSTRUCTIONS
short jumps

• All conditional jumps are short jumps.

– The address of the target must be within -128 to +127 bytes of
the IP.
• The conditional jump is a two-byte instruction.
– One byte is the opcode of the J condition.
– The second byte is a value between 00 and FF.
• An offset range of 00 to FF gives 256 possible addresses.
• In a jump backward, the second byte is the
2's complement of the displacement value

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.4: CONTROL TRANSFER INSTRUCTIONS
CALL statements
• For control to be transferred back to the caller, the last
subroutine instruction must be RET (return).
– For NEAR calls, the IP is restored..
• Assume SP = FFFEH:

– Since this is a NEAR call, only IP

is saved on the stack.
• The IP address 0206, which belongs
to the "MOV AX,142F" instruction,
is saved on the stack.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
2.4: CONTROL TRANSFER INSTRUCTIONS
short jumps
• The last instruction of the called subroutine must be a
RET instruction that directs the CPU to POP the top 2
bytes of the stack into the IP and resume executing at
offset address 0206.
– The number of PUSH and POP instructions (which alter the SP)
must match.
• For every PUSH there must be a POP.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
 Dec Hex Bin
2 2 00000010

ENDS ; THREE

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
 EEE3132: MICROPROCESSORS I
8086

Lecture Notes # 7
Dr. Lukumba Phiri
• Introduction to Assembly Programming
• Program Segments
 EEE3132: MICROPROCESSORS I
8086
Introduction to Assembly Language Programming
• ADD instruction

ADD destination, source; dest = dest + source

mnemonic operands

Example:
MOV AL,24H ;move 24H into AL
MOV DL,11H ;move 11H into DL
ADD AL,DL ;AL=AL+DL (AL=35H)(DL =11H)

MOV CH,24H ;move 24H into CH

MOV BL,11H ;move 11H into BL
ADD CH,BL ;CH=CH+BL (CH=35H)

MOV CH,24H ;load one operand into CH

ADD CH,11H ;add the second operand to CH (CH=35H)
 EEE3132: MICROPROCESSORS I
8086
Introduction to Assembly Language Programming
• ADD instruction

ADD destination, source; dest = dest + source

mnemonic operands

❖ If destination register is followed by an immediate data as the source, it is called

the immediate operand.
MOV CH,24H
ADD CH,11H

❖ 8-bit registers can hold FFH (255) as the maximum value. Addition of larger
numbers can be performed by the 16-bit nonsegment registers.

MOV AX,34EH
MOV DX,6A5H
ADD DX,AX ;DX=DX+AX (DX=9F3H)
MOV CX,34EH
ADD CX,6A5H ;CX=34EH+6A5=9F3H
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Segment
▪ A segment is an area of memory that includes up to 64K bytes and begins an address
evenly divisible by 16 (such an address ends in 0H).
▪ Assembly Language Program consists of three segments:
❖ code segment : contains the program code (instructions)
❖ data segment : used to store data to be processed by the program
❖ stack segment: used to store information temporarily.

• Logical and Physical Address

▪ Physical Address is the 20-bit address that actually put on the address bus. (in 8086)
❖ Has a range of 00000H - FFFFFH
▪ Segment Address is a 16-bit address of the segment block.
Each segment is a block of 64 KB of memory space.
▪ Offset Address is a location within 64K byte segment range.
Has a range of 0000H - FFFFH
▪ Logical Address consists of segment address and offset address.
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Memory Segmentation in 8086 Microprocessor
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Addressing in Code Segment
▪ To execute a program, the 8086 fetches the instructions from the code segment.

▪ The logical address of an instruction consists CS (Code Segment) and IP(instruction pointer).

▪ Logical Address in Code segment is represented by using segment address in CS register and
Offset Address in IP register as follows:

CS:IP (16 bit CS and 16 bit IP making

total of 32 bits)

Example: If CS register contains 2500H and IP register contains 95F3H. What is the
Locical Adress in the code segment?

CS:IP → 2500:95F3 (default in adressing is hex. You don’t need H)

 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Addressing in Code Segment
Physical Address is generated by shifting the CS one hex digit to the left and adding IP. Physical
address is 20 bit address which can be generated by using a logical address as follows.

1. Start with CS
2. Shift left CS (insert 0 as the Least significant digit)
3. Add IP

Example: If CS register contains 1980H and IP register contains 78FEH. What is the
Physical Adress in the code segment?

Logical address: CS:IP → 1980:78FE

1. Start with CS 1980

2. Shift left CS 19800
3. Add IP 78FE (19800+ 78FE =210FE)

Physical address: The microprocessor will retrieve the instruction from the memory locations
starting from 210FE (20 bit address).
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Addressing in Code Segment
Example: If CS=24F6H and IP=634AH, determine:
a) The logical address
b) The offset address
c) The physical address
d) The lower range of the code segment
e) The upper range of the code segment

Solution:
a) The logical address is; 24F6:634A
b) The offset address is; 634A
c) The Physical address is; 24F60+634A= 2B2AA
d) The lower range of the code segment: 24F6:0000 → 24F60+0000 = 24F60
e) The upper range of the code segment: 24F6:FFFF → 24F60+FFFF = 34F5F
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Addressing in Data Segment
• The area of memory allocated strictly for data is called data segment.

• Data segment contains variables containing single values and arrays of values, where code
segment only contain program instructions.

▪ Logical Address in Data Segment is represented by using segment address in DS register and
Offset Address in BX, SI or DI registers.

DS:BX
DS:SI
DS:DI

▪ At any time three locations in the data segment are pointed with DS:BX, DS:SI and DS:DI
respectively.
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Addressing in Data Segment

Example: If DS=7FA2H and the offset is 438EH, determine:

a) The physical address
b) The lower range of the data segment
c) The upper range of the data segment
d) Show the logical address

Solution:
a) The Physical address is; 7FA20+438E = 83DAE
b) The lower range: 7FA20+0000= 7FA20
c) The upper range: 7FA20+FFFF = 8FA1F
d) The logical address is; 7FA2:438E
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Addressing in Data Segment
Why do we use data segment?
Assume that a program is needed to add 5 bytes of data (25H, 12H, 15H,1FH and 2BH)

One way: MOV AL,00H ;initialize AL

ADD AL,25H
ADD AL,12H
ADD AL,15H code and data are mixed
ADD AL,1FH (bad programming practice)
ADD AL,2BH ; AL=25+12+15+1F+2B

Better way: Assume that the Data segment contains the array of bytes starting from offset
address 0200H.
DS:01FF ?
MOV AL,0 ;clear AL DS:0200 25
ADD AL,[0200];add the contents of DS:200 to AL DS:0201 12
ADD AL,[0201];add the contents of DS:201 to AL code and data are separated
ADD AL,[0202];add the contents of DS:202 to AL DS:0202 15
(good programming practice)
ADD AL,[0203];add the contents of DS:203 to AL DS:0203 1F
ADD AL,[0204];add the contents of DS:204 to AL DS:0204 2B
DS:0205 ?
Data Segment
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Little endian convention
Given 8-bit (1-byte) data, bytes are stored one after the other in the memory. However given16-
bit (2-bytes) of data how are date stored?

Example: MOV AX,35F3H ;load 35F3H into AX

MOV [1500],AX ; copy contents of AX to offset 1500H

In such a case the low byte goes to the low memory location and high byte goes to the high
memory location.
DS:1500 = F3 DS:1501 = 35

This convention is called little endian convention: This convention is used by Intel.

Big endian convention is the opposite, where the

high byte goes to the low address and low byte
goes to the high address. Motorolla microprocessor
uses this convention.
 EEE3132: MICROPROCESSORS I
8086

Lecture Continued
• Pushing and Popping Operations (Stack)
• Flag Registers and bit fields
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Addressing in Stack Segment

• What is a stack, and why is it needed?

The stack is a section of RAM used by the CPU to store information temporarily. CPU needs
this storage area since there are only limited number of registers.

• How stacks are accessed

SS (stack segment) and SP (stack pointer) must be loaded to access stack in the memory.
Every register in the CPU (except segment registers and SP) can be stored in the stack and
loaded from the stack.

▪ Logical Address in Stack Segment is represented by using segment address in SS register and
Offset Address in SP register.

SS:SP
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Stack: Pushing and Popping Operations
• Push Instruction
Storing the CPU register in the stack is called a push.

PUSH source; Copy the content of source (16-bit register) into stack

mnemonic operand * SP register is decremented by 2

Example: Given that SP=1456H, what are the contents of AX, top of the stack and SP after the
execution of the following instruction.

MOV AX,2174H SS:1453 ?

PUSH AX SS:1454 74
SS:1455 21
Solution: AX=2174H (stays the same), SP=1454H (decremented by 2),
SS:1456 ?
SS:1457 ?
SS:1458 ?
Stack Segment
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Stack: Pushing and Popping Operations
• Pushing onto the stack
Storing the CPU register in the stack is called a push.

Example: SP=1236H, AX=24B6H, DI=85C2H, and DX=5F93H, show the contents of the stack
as each of the following instructions is executed.
PUSH AX
PUSH DI
PUSH DX
SS:1230 93
Solution:
SS:1231 5F
Note that in 80x86 the lower byte of
SS:1232 C2 C2 the register is stored to the lower
SS:1233 85 85 address. (Little Endian Convention)
SS;1234 B6 B6 B6

SS;1235 24 24
24
SS:1236

START After After After

SP=1236 PUSH AX PUSH DI PUSH DX
SP=1234 SP=1232 SP=1230
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Stack: Pushing and Popping Operations
• Pop Instruction
Loading the contents of the stack into the CPU register is called a pop.

POP destination; Copy the top of the stack into destination (16-bit register)
mnemonic operand * SP register is incremented by 2

Example: Assume that SP=134AH and the illustration on the right SS:1349 ?
shows the content of the top of the stack. What will be the content SS:134A 76
of AX and SP after of after the execution of the following instruction.
SS:134B FC

POP AX SS:134C ?
SS:134E ?
Solution: AX=FC76H and SP=134CH (incremented by 2), SS:134F ?

Stack Segment
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Stack: Pushing and Popping Operations
• Popping the stack
Loading the contents of the stack into the CPU register is called a pop.

Example: Assume that the stack is shown below, and SP=18FAH, show the contents of the
stack and registers as each of the following instructions is executed.
POP CX
POP DX
POP BX
SS:18FA 23

SS:18FB 14
Solution:
SS:18FC 6B 6B
Note that in 80x86 the byte in the
SS:18FD 2C 2C Low address goes into the low byte.
SS;18FE 91 91 91 the byte in the high address goes into
F6
the high byte. (Little Endian Convention)
SS;18FF F6 F6

SS:1900
START After After
After
SP=18FA POP CX POP DX
POP BX
SP=18FC SP=18FE
SP=1900
CX=1423 DX=2C6B BX=F691
 EEE3132: MICROPROCESSORS I
8086
Introduction to Program Segments
• Logical vs. physical address of the stack
• Calculating the physical address for the stack, the same principle is applied as was used for
the code and data segments. Physical address depends on the value of stack segment (SS)
register and the stack pointer (SP).

Example: If SS=3500H and SP:FFFEH

a) Calculate the physical address: 35000+FFFE = 44FFE
b) Calculate the lower range of the stack: 35000+0000 = 35000
c) Calculate the upper range of the stack segment: 35000+FFFF = 44FFF
d) Show the logical address of the stack: 3500:FFFE
 EEE3132: MICROPROCESSORS I
8086
Introduction to Assembly Language Programming
• The Flag Register (FR) and bit fields
• The flag register is a 16-bit register sometimes referred as the status register. Although
the register is 16-bit. Not all the bits are used.

• Conditional flags: 6 of the flags are called the conditional flags, meaning that they
indicate some condition that resulted after an instruction was executed. These 6 are: CF,
PF, AF, ZF, SF, and OF.

• The 16 bits of the flag registers:

 EEE3132: MICROPROCESSORS I
8086
Introduction to Assembly Language Programming
• The Flag Register (FR) and bit fields
CF, the Carry Flag: This flag is set whenever there is a carry out, either from d7 after an 8-bit
operation, or from d15 after a 16-bit data operation.
PF, the Parity Flag: After certain operations, the parity of the result’s low-order byte is
checked. If the byte has an even number of 1s, the parity flag is set to 1; otherwise, it is cleared.
AF, the Auxiliary Carry Flag: If there is a carry from d3 to d4 of an operation this bit is set to
1, otherwise cleared (set to 0).
ZF, the Zero Flag: The ZF is set to 1 if the result of the arithmetic or logical operation is zero,
otherwise, it is cleared (set to 0).
SF, the Sign Flag: MSB is used as the sign bit of the binary representation of the signed
numbers. After arithmetic or logical operations the MSB is copied into SF to indicate the sign of
the result.
TF, the Trap Flag: When this flag is set it allows the program to single step, meaning to
execute one instruction at a time. Used for debugging purposes.
IF, Interrupt Enable Flag: This bit is set or cleared to enable or disable only the external
interrupt requests.
DF, the Direction Flag: This bit is used to control the direction of the string operations.
OF, the Overflow Flag: This flag is set whenever the result of a signed number operation is too
 EEE3132: MICROPROCESSORS I
8086
Introduction to Assembly Language Programming
• Manipulating the Flag Register
• There are two instructions that can be used to use/change the content of the flag
register.
• PUSHF Instruction

PUSHF ; Copy the flag register into stack

* SP register is decremented by 2

Example: Copy the content of the flag register into register AX.

PUSHF ; copy the content of Flag register into the stack.

POP AX ; copy from the stack into AX
 EEE3132: MICROPROCESSORS I
8086
Introduction to Assembly Language Programming
• Manipulating the Flag Register
• There are two instructions that can be used to use/change the content of the flag
register.
• POPF Instruction

POPF ; Copy from the stack into the flag register

* SP register is incremented by 2

Example: Clear the flag bits. (Make the flag bits to be all 0)

MOV AX,0000H
PUSH AX ; now top of the stack contains 16-bit 0.
POPF ; copy the content of stack into flag register.
ALGORITHMS AND
FLOWCHARTS
 ALGORITHMS AND FLOWCHARTS
◼ A typical programming task can be divided into
two phases:
◼ Problem solving phase
 produce an ordered sequence of steps that describe
solution of problem
 this sequence of steps is called an algorithm

◼ Implementation phase
 implement the program in some programming
language
 Steps in Problem Solving
◼ First produce a general algorithm (one can use
pseudocode)
◼ Refine the algorithm successively to get step by
step detailed algorithm that is very close to a
computer language.
◼ Pseudocode is an artificial and informal
language that helps programmers develop
algorithms. Pseudocode is very similar to
everyday English.
 Pseudocode & Algorithm
◼ Example 1: Write an algorithm to
determine a student’s final grade and
indicate whether it is passing or failing.
The final grade is calculated as the
average of four marks.
 Pseudocode & Algorithm
Pseudocode:
◼ Input a set of 4 marks
◼ Calculate their average by summing and dividing
by 4
◼ if average is below 50
Print “FAIL”
else
Print “PASS”
 Pseudocode & Algorithm
◼ Detailed Algorithm
◼ Step 1: Input M1,M2,M3,M4
Step 2: GRADE  (M1+M2+M3+M4)/4
Step 3: if (GRADE < 50) then
Print “FAIL”
else
Print “PASS”
endif
 The Flowchart
◼ (Dictionary) A schematic representation of a sequence of
operations, as in a manufacturing process or computer
program.
◼ (Technical) A graphical representation of the sequence of
operations in an information system or program.
Information system flowcharts show how data flows from
source documents through the computer to final
distribution to users. Program flowcharts show the
sequence of instructions in a single program or
subroutine. Different symbols are used to draw each
type of flowchart.
 The Flowchart
A Flowchart
 shows logic of an algorithm
 emphasizes individual steps and their
interconnections
 e.g. control flow from one action to the next
 Flowchart Symbols
Basic
Name Symbol Use in Flowchart

Oval Denotes the beginning or end of the program

Parallelogram Denotes an input operation

Rectangle Denotes a process to be carried out

e.g. addition, subtraction, division etc.

Diamond Denotes a decision (or branch) to be made.

The program should continue along one of
two routes. (e.g. IF/THEN/ELSE)

Hybrid Denotes an output operation

Flow line Denotes the direction of logic flow in the program

 Example
START
Step 1: Input M1,M2,M3,M4
Step 2: GRADE  (M1+M2+M3+M4)/4
Input
M1,M2,M3,M4
Step 3: if (GRADE <50) then
Print “FAIL”
else
GRADE(M1+M2+M3+M4)/4 Print “PASS”
endif
N IS Y
GRADE<5
0

PRINT PRINT
“PASS” “FAIL”

STOP
 Example 2
◼ Write an algorithm and draw a flowchart to
convert the length in feet to centimeter.
Pseudocode:
◼ Input the length in feet (Lft)
◼ Calculate the length in cm (Lcm) by
multiplying LFT with 30
◼ Print length in cm (LCM)
 Example 2
Flowchart
Algorithm START

◼ Step 1: Input Lft

Input

◼ Step 2: Lcm  Lft x 30

Lft

◼ Step 3: Print Lcm Lcm  Lft x 30

Print
Lcm

STOP
 Example 3
Write an algorithm and draw a flowchart that
will read the two sides of a rectangle and
calculate its area.
Pseudocode
◼ Input the width (W) and Length (L) of a rectangle
◼ Calculate the area (A) by multiplying L with W
◼ Print A
Example 3
Algorithm START

◼ Step 1: Input W,L Input

W, L
◼ Step 2: A  L x W
◼ Step 3: Print A ALxW

Print
A

STOP
Example 4
◼ Write an algorithm and draw a flowchart that
will calculate the roots of a quadratic equation
ax 2 + bx + c = 0
◼ Hint: d = sqrt ( b 2 − 4ac ), and the roots are:
x1 = (–b + d)/2a and x2 = (–b – d)/2a
Example 4
Pseudocode:
◼ Input the coefficients (a, b, c) of the
quadratic equation
◼ Calculate d
◼ Calculate x1
◼ Calculate x2
◼ Print x1 and x2
 Example 4
START

◼ Algorithm:
Input
◼ Step 1: Input a, b, c a, b, c
◼ Step 2: d  sqrt ( b  b − 4  a  c )
◼ Step 3: x1  (–b + d) / (2 x a) d  sqrt(b x b – 4 x a x c)

◼ Step 4: x2  (–b – d) / (2 x a)
x1 (–b + d) / (2 x a)
◼ Step 5: Print x1, x2
X2  (–b – d) / (2 x a)

Print
x1 ,x2

STOP
 DECISION STRUCTURES
◼ The expression A>B is a logical expression
◼ it describes a condition we want to test
◼ if A>B is true (if A is greater than B) we take
the action on left
◼ print the value of A
◼ if A>B is false (if A is not greater than B) we
take the action on right
◼ print the value of B
DECISION STRUCTURES

Y N
is
A>B

Print Print
A B
IF–THEN–ELSE STRUCTURE
◼ The structure is as follows
If condition then
true alternative
else
false alternative
endif
IF–THEN–ELSE STRUCTURE
◼ The algorithm for the flowchart is as
follows:
If A>B then
Y N
print A is
A>B
else
print B Print
A
Print
B
endif
Relational Operators

Relational Operators
Operator Description
> Greater than
< Less than
= Equal to
 Greater than or equal to
 Less than or equal to
 Not equal to
Example 5
◼ Write an algorithm that reads two values, determines the
largest value and prints the largest value with an
identifying message.
ALGORITHM
Step 1: Input VALUE1, VALUE2
Step 2: if (VALUE1 > VALUE2) then
MAX  VALUE1
else
MAX  VALUE2
endif
Step 3: Print “The largest value is”, MAX
Example 5
START

Input
VALUE1,VALUE2

Y is
N
VALUE1>VALUE2

MAX  VALUE1 MAX  VALUE2

Print
“The largest value is”,
MAX

STOP
 NESTED IFS
◼ One of the alternatives within an IF–
THEN–ELSE statement
 may involve further IF–THEN–ELSE
statement
 Example 6
◼ Write an algorithm that reads three
numbers and prints the value of the largest
number.
 Example 6
Step 1: Input N1, N2, N3
Step 2: if (N1>N2) then
if (N1>N3) then
MAX  N1 [N1>N2, N1>N3]
else
MAX  N3 [N3>N1>N2]
endif
else
if (N2>N3) then
MAX  N2 [N2>N1, N2>N3]
else
MAX  N3 [N3>N2>N1]
endif
endif
Step 3: Print “The largest number is”, MAX
 Example 6
◼ Flowchart: Draw the flowchart of the
above Algorithm.
 Example 7
◼ Write and algorithm and draw a flowchart
to
a) read an employee name (NAME),
overtime hours worked (OVERTIME),
hours absent (ABSENT) and
b) determine the bonus payment
(PAYMENT).
 Example 7
Bonus Schedule
OVERTIME – (2/3)*ABSENT Bonus Paid

>40 hours $50

>30 but  40 hours $40
>20 but  30 hours $30
>10 but  20 hours $20
 10 hours $10
Step 1: Input NAME,OVERTIME,ABSENT
Step 2: if (OVERTIME–(2/3)*ABSENT > 40) then
PAYMENT  50
else if (OVERTIME–(2/3)*ABSENT > 30) then
PAYMENT  40
else if (OVERTIME–(2/3)*ABSENT > 20) then
PAYMENT  30
else if (OVERTIME–(2/3)*ABSENT > 10) then
PAYMENT 20
else
PAYMENT  10
endif
Step 3: Print “Bonus for”, NAME “is $”, PAYMENT
 Example 7
◼ Flowchart: Draw the flowchart of the
above algorithm?