Manufacturing by S. J.

Holmes
P. H. Mitchell
M. C. Hakey
with DUV
lithography

Deep-UV (DUV) lithography has been Figure 1, for lithography at the diffraction limit, a shorter
developed to scale minimum feature sizes of wavelength provides more depth of focus at a particular
devices on semiconductor chips to sub-half- resolution value because the shorter wavelength allows a
micron dimensions. This paper reviews early lower-NA photolithography tool to achieve equivalent
manufacturing experiences at the IBM resolution.
Microelectronics Division with deep ultraviolet The IBM Microelectronics Division has been active in
(DUV) lithography at a 248-nm wavelength. the evolution of lithography throughout the development
Critical steps in the processing of 1Mb DRAM, of the semiconductor industry (Figure 2). DRAM
16Mb DRAM, and logic gate conductors in production of 64Kb devices utiHzed scanning exposure
devices are discussed. The evolution of DUV equipment operating at a G-line wavelength of 436 nm.
lithography tools is also briefly reviewed. These tools were capable of operating at several different
exposure wavelengths, including 436 nm, 313 nm, and
245 nm [1]. IBM used these tools for 256Kb DRAM chips
Introduction: Lithographic scaling by formulating a resist, TNS, which was functional at the
Lithographic scaling has historically been accomplished by 313-nm exposure region [2], allowing the critical feature
optimizing the parameters in the Rayleigh model for size to be scaled from 2 nm to 1.4 ^m. This approach was
image resolution: In this model, image resolution = repeated for 1Mb DRAM chips, and a 245-nm exposure
k^klNA, and depth of focus (DOF) = k,k/NA^, where region was used to obtain the l-fim critical features with
A = exposure wavelength and NA = numerical aperture the same tool set, which required the development of the
{k^, kj = constants for a specific lithographic process). To first production deep-UV (DUV) chemically amplified,
pattern devices with decreasing feature sizes, photoresist negative-tone resist [3]. At this time, G-llne steppers were
exposure wavelengths were reduced and numerical introduced at a NA of 0.35, and the process for the
apertures were increased. production of 1Mb DRAM reverted to G-line lithography.
During the last ten years, image resolution was For the 4Mb DRAM generation, stepper technology was
sufficiently increased to scale minimum dimensions from extended by scaling the wavelength to the I-line (A =
1-ju.m feature sizes for the 1Mb DRAM devices to 0.25-iim 365 nm). High-NA (0.42-0.45) G-line steppers were used
features for the 256Mb DRAM. The depth of focus is to manufacture 4Mb pilot line products at 0.8-/im ground
proportional to the inverse of the square of the numerical rules, while lower-NA (0.35) I-line steppers were used for
aperture; thus, if resolution is enhanced by increasing NA, final qualification of products with 0.6-0.7-jLtm critical
the depth of focus becomes very small. If the resolution is features. For the 16Mb generation, DUV in the 245-nm
enhanced by decreasing the wavelength, the corresponding exposure region was utilized for development and initial
decrease in depth of focus is less severe. As shown in production, while very high NA (0.5-0.6) I-line (365 nm)
^Copyright 1997 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each
reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions,
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0018-8646/97^.00 © 1997 IBM

fflM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY.MARCH 1997 S. J. HOLMES, P. H. MrrCHELL, AND M. C. HAKEY
 I-line resists were composed of modified G-line materials,
4.0
the DUV resists operated by a different mechanism. The
DUV region of the mercury arc lamp is of relatively low
intensity compared to the I-line and G-line regions. To
.VO --
E
D Dl.'Vi)i = 248nm) compensate for low DUV exposure intensities, a chemical
0 l-line(\ = .%5nm)
3.
A G-lini; fX = 436 nm) /
amplification method [4, 5] was used to enhance the speed
•i 7(1 - - of the DUV resist. This catalytic amplification process,
combined with new resins that were less absorbing at
A = 245 nm than the traditional novolak materials,
1.(1 introduced significantly different resist processing
requirements for DUV lithography. These unique process
requirements were characterized and included as part of
_. « r T _ i .!_. 1 1
0.2
1 1 1
the process of implementing DUV lithography in product
0.4 0.6 0.8
Unewidth (jitni) applications.

DUV processing for product applications

Depth of focus as a function of image resolution, as calculated with • 1Mb DRAM: 1985-1986
the Rayleigh model. Numerical aperture is variable, and increases as DUV resist was used at A = 245 nm to print the first level
resolution increases. For this calculation, k, = k., = 0.7. of the 1Mb DRAM, which was recessed oxide (Rox)
isolation [5]. This level required the printing of a l-jam
resist spacing between features on a 100-nm silicon nitride
film. The image was transferred into the nitride film with
an RIE process. DUV was used on this level because the
initial G-line steppers were limited to a resolution of
2.0 E 3 G-line 313 nm 1.2 i^m, and insufficient wafer stage control was available
(436 nm)
to establish a uniform grid at the first mask level. The
I-line ^ DUV scanning exposure tools, which were commonly available
|i.5
(365 nm) (248 nm)
in manufacturing areas at that time, were capable of l-ju,m
feature resolution at DUV exposure wavelengths (A =
1.0
240-250 nm). Since these tools were full-wafer scanners,
the first level was printed as a regular grid, with the
0.5

m
relative positioning of each chip predominantly established
by the reticle fabrication tool. Product overlay could be
ymm achieved within the required tolerance by using this
64Kb 256Kb 1Mb 4Mb 16Mb 64Mb
regular and repeatable first level as a reference point for
DRAM generation
the alignment of subsequent mask levels.
The initial DUV resist formulation was a negative-tone
material with a new resin, solubility inhibitor, photoactive
DRAM critical dimension (CD) scaling experience at IBM, detailing compound, and developer solution compared to the
minimum-feature-size ground rules and lithographic exposure previously utilized mid-UV resists. The resin was a para-
technology for each DRAM generation. The 16Mb DRAM hydroxy-styrene polymer (PHOST) modified with a
development and early production used DUV (\ = 248 nm)
lithography; exposure at X. = 365 nm (I-line) was used for large-
tertiary-butoxy-carbonyl (tBOC) functionality to impart
volume production. insolubility in polar solvents and aqueous-base solutions.
A sulfonium salt was used as a photo-acid generator, and
a post-exposure bake was used to cause a catalytic
cleavage of the tBOC group from the exposed resist
(Figure 3) [4, 6]. Development in anisole of the exposed
was used for volume production at 0A-0.5-fim image and baked resist selectively removed the unexposed
sizes. The 64Mb and 256Mb DRAM generations use high- material, providing a negative-tone image.
NA (0.5-0.6) DUV tools at X = 248 nm for images at This resist was very sensitive, requiring a 1-5-mJ/cm^
0.25-0.35-/im resolution. exposure dose, depending on the formulation and process
During this scaling process, several DUV resist conditions. Contrast was high, with a y value of 8-10,
materials were developed and utilized by IBM. While and the l-fj,m resolution requirement of this product

S. S. HOLMES, P. H. MITCHELL, AND M. C. HAKEY IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997
application was easily achieved. With this system,
throughput levels of 100 wafers per hour could be
achieved with existing scanning exposure equipment.
However, a number of difficulties with this system soon - /CH3
rj+cHj-c^ +CO2
became apparent as product application work progressed.
CH-i
While resist adhesion was acceptable on silicon wafers,
poor adhesion was obtained on the silicon nitride product
film. The hexamethyldisilazane (HMDS) adhesion priming
operation, which was effective for conventional w (b)

development of resists in aqueous solutions, was

ineffective for the hydrophobic solvent used in this DUV
Mill»:3
develop process. Thermal oxidation at the nitride surface Caiemical ainplification mechanism for early embodiments of DUV
to form a silicon oxynitride surface improved resist resist The unexposed resin (a) dissolves in nonpolar solvents, while
adhesion sufficiently to warrant further product the exposed and baked resist (b) dissolves in polar solvents. As
development. shown in the chemical reaction, acid, wMch is generated (from a
photoactive sulfonium salt) during exposure, catalytically cleaves
Metallic oxide residues were identified in the resist the solubility inhibitor from the resin (a) during a post-exposure
stripping baths and traced to the photosensitizer materials bake (PEB) process.
used in the DUV resist. These residues were reduced by
specifying smaller wafer batches between bath changes
and, ultimately, by replacing the metallic components in
the resist formulation with organic materials.
Attention also focused on control of the post-exposure
bake process, because this parameter became more
important for linewidth control than exposure dose levels
in the photolithography tool (Figure 4). The catalytic
chemical amplification reaction which produced the high
resist sensitivity needed for operation at the low light
intensities available in DUV was exponentially dependent
on the bake temperature used to induce the catalysis.
As a result, resist sensitivity also became exponentially
dependent on the bake temperature [7].
Not only was the catalytic amplification process of this
resist dependent on the bake conditions, but it could also 55 60 65 70 75 80 85 90
be affected by the presence of contaminants from P(Mi-exposure bake temperature (°C)
chemicals in the manufacturing environment. It was
observed that freshly coated wafers, when placed in a
cassette on the photolithography tool and exposed in ^:«iiiire^*-:
sequence, often displayed a continuous shift in linewidth Change in resist sensitivity with post-exposure bake temperature for
from wafer to wafer across the cassette. The resist steadily an early version of DUV resist, using tBOC resin.
became one to three times less sensitive as the delay time
from application of resist to its exposure increased. After
two to three hours, the resist stabilized at a lower sensitivity
value (Figure 5). This behavior was caused by the observed for each subsequent batch of product wafers.
absorption of chemical bases, such as N-methylpyrolidone This required "send-ahead" wafers to control image size
(NMP), into the resist at part-per-billion levels, for each lot, thereby significantly reducing throughput
which interrupted the catalytic image formation from the DUV sector (Figure 6).
process [8] and caused a large change in resist sensitivity. While these difficulties rendered the process
Initially, wafers were deliberately allowed to stand in the cumbersome, the development cycle of the 1Mb DRAM
manufacturing environment and absorb the chemical proceeded on schedule, and initial product demand was
contaminants. The resist sensitivity became relatively supplied. Several million fully functional 1Mb DRAM
stable and then could be processed with acceptable chips were produced with DUV (245-nm) technology.
linewidth control after the contaminants were absorbed. In the laboratory, the negative-tone resist used on the
Because of variations in the manufacturing environment, 1Mb DRAM was shown to act as a positive-tone material
however, signiicant shifts in resist sensitivity were if an appropriate polar developer was used [4]. In practice,

mM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997 S. J. HOLMES, P. H. MITCHELL, AND M. C. HAKEY
 contamination inadvertently poisoning the resist, and that
a suitable positive-tone image could be formed if the
effect of this contamination process was reduced or
eliminated. When the resist was formulated to provide a
higher dissolution rate of unexposed resist, the surface
layer of contaminated resist could be removed in the
development process, and a resist image with an
acceptable profile was obtained.
As work on the 1Mb DRAM production shifted to more
100 m --_/-' ado 250 advanced G-line steppers (0.35 NA), the DUV effort was
Delaytinw{fsm) refocused on the 16Mb DRAM and the development of a
positive-tone material which would overcome the
limitations of this first-generation negative-tone DUV
Figure 5
resist.
Plot of DUV resist sensitivity as a function of the delay time
between baking of resist and resist exposure, with the wafers
resting in a cassette on the photolithographic tool input station. • 16Mb DRAM: Positive-tone DUV resist, 1987-1992
Negative resist on wafers for 1Mb DRAM which have been The experience gained from the 1Mb DRAM DUV
"equilibrated" with contaminated fabrication facility air for a
development effort was used as a foundation for 16Mb
period of 2-3 hours became relatively stable to fiitther change
(Curve A), but required high doses (5 mJ/cm^) for image exposure. DUV applications. When the 16Mb work began in 1987
Wafers which had been processed through the resist application- at 500-nm resolution, conjecture centered on whether
bake steps immediately prior to processing in the photolithography conventional optical lithography with single-layer resist
tool (Curve B) were more sensitive (1.5 mJ/cm*) to exposure dose
than the equilibrated wafers, but displayed rapid changes In
processing would be attainable at the reduced depth-
sensitivity as they were allowed to interact with air in the of-focus margins, or whether bilayer and top-surface
fabrication facility. imaging resists would be required [9]. At this time, I-line
steppers were barely achieving the O.T-jim resolution
requirements of the 4Mb DRAM, A new DUV
photolithography tool with a NA of 0.36 (discussed
below in the section on photolithography tools) was
developed which was suitable for 0.5-/xm lithography.
This tool was used for the 16Mb DRAM development
program.
The 16Mb DRAM had six critical mask levels with
resolution requirements of 0.5-0.6 /nm and an overlay
tolerance of 0.2 ju,m. Several of these levels contained
critical features which were small openings (0.5-0.6 jam)
printed in a field of resist. A positive-tone resist was
desirable for these levels because of an enhanced focus
window compared to negative-tone imaging and reduced
^ hWootletawBliet reticle defects. (The positive-tone reticle was primarily a
chrome area, which would mask particulates on the reticle
surface, whereas a negative-tone reticle would have been
mostly clear, allowing particles on the reticle to print as
Exposure dose at X = 248 nm as a fiinction of product lot for defects.) The negative-tone resist formulation used for the
negative DUV resist on a 1Mb DRAM Rox isolation mask level. 1Mb DRAM was modified to create a positive-tone resist
Large chatiges in exposure dose between product lots were
required to compensate for variations in the level of airborne
that overcame many of the initial DUV process control
contamination of each lot. Each lot was equilibrated with problems. The resin composition was modified to reduce
fabrication facility air for 2-3 hours prior to exposure. loss of mass by decreasing the concentration of solubility
inhibitor (which provided increased etch resistance and
reduced image distortion) and to reduce the resist
contrast. Reduced contrast allowed the resist to be more
the positive-tone image was distorted by an insoluble film robust to chemical contamination by an airborne organic
at the surface of the exposed resist (Figure 7). After the base. This, in turn, allowed aqueous-base developers to be
experience with the negative-tone resist, it was realized used without adverse effects on the positive-tone resist
10 that this inhibition effect was caused by chemical profile. Resist chemical amplification was reduced by using

S. J. HOLMES, p. H. MITCHELL, AND M. C. HAKEY IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997
lower post-exposure bake temperatures and adding acid-
quenching materials to the resist during formulation.
While resist sensitivity was reduced by these changes,
process latitude with respect to profile and sensitivity
variations caused by unintended interruption of the
chemical amplification process was increased. The use of
aqueous-base developer allowed conventional HMDS
surface treatments to be used for the enhancement of
resist adhesion, thereby avoiding problems with lifting and
cracking resist. Resin molecular weight was sharply
reduced, which enhanced depth of focus and resulted in
an absence of resist residuals after development.
Nonmetallic photosensitizers were implemented, which
further reduced residuals after resist-stripping processes.
In addition, bottom antireflective coatings (ARC) and
topcoat materials were developed to provide barriers to
chemical contamination from both the wafer substrate and Cross section of resist for a contact hole imaged in a prototype
version of DUV resist and developed with isopropyl alcohol. An
the processing atmosphere. As a result, the chemical insoluble layer present at the resist surface is caused by airborne
amplification process in the resist could proceed without chemicals in the processing area that interrupt the chemical
unintended interruption. These enhancements provided amplification process near the resist surface.
sufficient process stability for development and fabrication
of the 16Mb critical mask levels. Since resist stability was
sufficient, exposure dose could be controlled with
statistical process control (SPC) charts rather than with
send-ahead test wafers (Figure 8) [10]. The exposure dose 0.65
was modified only if the average image size for a lot was
outside the indicated control limits, or if seven lots in Upper contiol liinit
0.6 -
succession were above or below a target image size. The
process steps for the first-generation positive-tone DUV Average
resists are as follows:

• Adhesion prime or ARC apply/bake. Lower control limit

•S 0.45
• Apply resist.
• Bake.
0.4
• Apply topcoat. 0 to 20 30 40 50 Ml
• Bake. Product lot number
• Expose.
• Post-exposure bake.
• Develop in aqueous base.
Statistical process control chart for the isolation trench (IT) feature
of a 16Mb DRAM. Resist sensitivity and, consequently, image size
SEM cross sections of selected features from the 16Mb are tightly controlled through the use of a resist topcoat material
DRAM critical mask levels are shown in Figures 9 and 10. that prevents disruption of the catalytic image-formation process
The deep-trench storage capacitor (Figure 9) was printed by contaminant chemicals in the fabrication facility air.
with a resist opening 0.7 jum wide with a 0.5-fj,m
separation between adjacent trenches. The isolation trench
contained 0.5-p,m resist lines with 0.6-(xm spaces in the
DRAM support structures. The surface strap, an electrical While the formulation changes for the 16Mb application
connection between the trench capacitor and the diffusion of DUV resist relieved many of the initial problems, a
area, was printed as an 0.8-/xm resist island with a 0.4-p-m continuing concern was the dependence of sensitivity on
separation between adjacent straps. The straps were the post-exposure bake temperature (Figure 11). When
printed over the gate conductor topography, which was more than one resist bake plate was used in a "clustered
0.8 fxm in depth. The gate conductor (Figure 10) was a process," maintaining the temperature matching of the
serpentine 0.6-iim line/space combination in the memory plates was often difficult. In a clustered process, the bake
array, with 0.5-/xm lines in the memory support features. station is physically attached to the photolithography tool. 11

IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997 S. J. HOLMES, P. H. MITCHELL, AND M. C. HAKEY
 1.1 "Am I iii» , 111 iipiii jT^piin^tfl ntf^^»))il iii»nuiifi)Vi|

as t i i i - i i • iijiii
81,1 • .83 I
iihHi,iiiiriiM(.ii'ih;ii.i»iiii.i4..
;;-85'-i;i ;;»;"'
.ii.)ii. .wi-.i.i
1,89
litinii...
91

urell
The width of spaces between positive-tone DUV resist images as a
function of post-exposure bake (PEB) temperature for exposures at
19 mJ/cm^ (Curve Al and 11 mJ/cm^ (Cur%-e B). Control of the
post-exposure bake temperature was among the most critical
parameters for control of image size.
^Biy«;i;^
SEM cross section of deep-trench storage nodes in a 16Mb
DRAM. Two polysilicon straps are shown, each connecting a
diffusion to a deep-trench storage node. The trenches, 0.7 fua wide
and 8-9 fim deep, are located between the vertical oxide collars.
The structures were patterned with DUV resist at X = 245 nm.
from the photolithography tool. Gradual drift in bake-
plate temperature could cause variation in wafer-to-wafer
or lot-to-lot linewidth. Defects at the resist bake step,
either from particles lodged between the wafer and
the surface of the bake plate, or from failure of the
and it is desirable to use a sufficient number of bake positioning pins on the hot plate, could cause linewidth
plates to match the throughput capability of the variation within a wafer. Prototype linewidth monitoring
photolithography tool. In this arrangement, different bake equipment was developed to monitor the image formation
plates are often used for successive wafers as they emerge on a bake plate, both as a potential means of controlling

111,'

SEM cross sections of 16Mb DRAM gate conductor resist images with 0.6-iU.m linewidths, patterned with positive-tone DUV resist: (a) Cross
section; (b) view of serpentine pattern.

12

S. J. HOLMES, P. H. MITCHELL, AND M. C. HAKEY IBM J, RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997
 100

^ 80-

60

40

40 60 20 ' Leakage
PEB time (s)
Yield limitation -

0.25 0.28 0.35 0.42 0.45

Example of an endpoint trace from an in situ monitor of the Channel length (/im)
contact-via pattern image-formation process during the post-
exposure bake. Intensities of diffraction patterns from the positive-
tone DUV resist images were measured as a function of PEB time
to derive a PEB endpoinl. :ifigUIINft13'
Schematic diagram of chip yield dependence on gate conductor
channel length control. Channel length deviations to smaller
feature sizes cause chip fails due to leakage, while excursions to
larger feature sizes cause fails due to poor performance.
(Reproduced from [13b], with permission.)
the photolithographic-image size and as a means of
detecting excursions in the bake process (Figure 12) [11],
but are not implemented in manufacturing at present. The
second-generation positive-tone DUV resist materials
which are currently appearing in the marketplace provide
more stability in the post-exposure bake process, as well as
stability to airborne chemical contamination [12].

I"
- Polymer-fonning - — Polymer-free initiation — •
initiation •;
• Logic gate conductor: 1992-1994
During the characterization of the DUV positive-tone I 0.08
resist process, systematic within-chip differences in
printing were observed. At the memory gate conductor I
level, in particular, isolated lines in the support areas were 1 "•*"*
consistently wider than corresponding nested lines in a I OK •• , • ••• •
memory array. Because of the timing circuits which are • • •
present in the gate conductor features, this systematic -0.04
to 15 20 25 30 35
difference caused yield reductions due to a loss in chip Wafer lots
performance (Figure 13) [13(a)]. For the memory product,
this linewidth deviation can be caused by both systematic
etch and photolithography causes (Figures 14 and 15) Figure 14
[13(b)]. Polymer by-products of an etch plasma deposit Within-chip image size deviations are caused by polymer-forming
more rapidly on the isolated features than the nested processes during gate conductor RIE image transfer. Lowering the
levels of polymer formation by adjusting the etching process
features, thereby causing the isolated lines to become
improved linewidth control and, consequently, resulted in higher
wider than the nested lines [14]. The diffraction effects of chip yield.
the positive-tone aerial image caused the resist to print
with a similar systematic bias, with isolated lines printing 13

IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997 S. J. HOLMES, P. H. MITCHELL, AND M. C. HAKEY
 0.36 0,44
I jnewidth (nm) t-incwidih (.fivn)
fa) (b)

Wilhin-chip 0.35-ju,ni-linewidth image size deviations caused by diffraction effects in the aerial image using a 0.50-NA step-and-scan tool: (a)
High-contrast, positive-tone resist exposed with diffraction-limited optics prodwces isolated lines which are systematically larger than nested
lines, as illustrated by the two distinct measured linewidth distributions for this process, (b) Negative-tone patterning provides a narrower
image size distribution for isolated and nested lines. (Reproduced from [13bl, with permission.)

approximately 8% larger than nested lines. For the base, providing the good adhesion characteristics
memory product, it was possible to optimize the reticle obtainable with such systems. Cross-linking in this resist is
image size compensations to reduce this effect by using very eficient, providing high-speed resist materials. As a
manual image inspection and compensation procedures. result, chemical additives can be used to stabilize the
For logic applications, however, the irregular nature of the resist to chemical ampliication poisons without degrading
circuit pattern was too complex for manual alteration, and the resist sensitivity or reducing wafer throughput. This
the features could not be automatically compensated with negative-tone resist does not require a topcoat for process
the available software technology. stability.
The aerial image of negative-tone lines contains a The cross-linking mechanism also provides a low-
minimal offset between nested and isolated lines [15]. In activation-energy image-formation process during the post-
fact, the isolated lines print slightly smaller than the exposure bake. This results in a smaller variation of image
nested lines for negative-tone resist (Figure 15). This aids size with post-exposure bake temperature, thereby further
in compensating for the etch effect, which can be modiied enhancing the manufacturability of DUV processes.
with etch chemistry and process, but which generally Developer process latitude is also enhanced, since the
causes isolated lines to increase in width compared to image size for negative-tone resist is considerably more
nested lines for polysilicon etch processes (Figure 14). stable to develop time than for positive-tone resists.
A second-generation negative-tone resist was formulated The use of this resist, combined with enhanced etch
to further enhance the DUV process capability [16]. This processes and reticle uniformity, led to improvements in
resist was used with a 0.5-NA step-and-scan exposure tool across-chip linewidth control for CMOS logic gate
to achieve 0.35-;Ltm gate conductor lithography. The conductor programs. This enhanced linewidth control
mechanism of this resist is different from the initial DUV provides higher performance and yield values, which are
material in that the resin Is cross-linked to impart the primary components for process manufacturing costs
insolubility to the exposed area. The previous resist had (Figure 16) [12, 13].
used a polarity change of the resin to impart insolubility While the photoresists described were largely developed
to the exposed area. This new approach allowed a resist to at IBM, an essential component in chip fabrication for
14 be formulated which could be developed with an aqueous device applications is the exposure tool used to image the

S. 1. HOLMES, p. H. MITCHELL, AND M. C. HAKEY IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997
 0.12

Illuminated arc
0.10 1 3 Positive resist Spherical
primary Start of scan
L\1 Negative resist
0.08 Spherical
secondary I Scan direction / F/3.0 cone
? A /
5
a 0.06

1J
y 0.04

0.02 ;^
Near-concentric
objective
0 i^ EST
-0.01
Etch Photo Optics Reticle Process
I-N I-N
Schematic diagram of the projecdon opdcs for the first DUV scanning
exposure tool, the PE-500, manufactured by the Perkin-Elmer
iiWi^?^ Corporation. (With permission, SVG Lithography Systems, Inc.,
Wilton, CT.)
Across-chip linewidth variation (ACLV) of photolithographic and
etch components: Curve A, positive-tone process (dotted columns)
exposed with a 0.42-NA DUV step-and repeat system; Curve B,
negative-tone resist (shaded colunms) exposed with a 0.50-NA
DUV step-and-scan system. The positive-tone resist exposed with

I
diffraction-limited optics produces isolated (I) lines which are
systematically larger than nested (N) lines, as illustrated by the two Start ^'-yf^-
distinct measured linewidth distributions for this process. scan
Negative-tone patterning provides a narrower image size T
distribution for isolated and nested lines. While reticle fabrication
continues to improve, it is a significant source of within-chip
•A \
/ N

4
T „

-I
linewidth variation.
^
T
— .^ .J

\
'1
V
semiconductor patterns into the resist. During this
application activity, IBM interacted closely with equipment
suppliers to ensure that both the resist process and tool
T

">
J
1..-
- >^-^- ^- -
capabilities were commensurate with product
requirements.
J

Evolution of DUV photolithography tool

diiiWis
• Vrior to 1985 A stepping diagram for a step-and-scan exposure system. (With
The first tool used for DUV manufacturing was a Perkin- permission, [18].)
Elmer full-wafer scanner (Table 1) with a curved-arc
capillary mercury arc lamp source and reflective ring field
projection optics (Figure 17). The reticle and wafer are
mounted together on an air-bearing carriage which is for 1Mb DRAM manufacturing could be achieved. This
scanned to image the entire wafer in a single pass. The scanner was used in the 1Mb DRAM application
tool achieves high wafer throughput in manufacturing described earlier.
because of the single scan per wafer. The use of this tool at resolutions below 1 ixm was not
The tool is adapted to DUV exposures using a filter in pursued because astigmatism was not fully corrected in
the illuminator/condenser. Since the illumination source some systems, and vertical and horizontal lines could
is broadband and the reflective projection optics are differ by as much as 0.2 fim for a nominal 1.0-p,m
corrected to less than 240 nm, resolutions of 1 fim needed feature. Also, exposure uniformity was difficult to 15

IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997 S. J. HOLMES, P. H. MITCHELL, AND M. C. HAKEY
 Table 1 comparison of attributes for a progression of DUV tools.

Equipment principle Full wafer scanner Step and scan Step and repeat Step and scan
Supplier Perkin-Elmer Perkin-Elmer/ Nikon SVG Lithography
SVG Lithography
Exposure source Mercury arc Mercury-xenon arc BCrF excimer Mercury-xenon arc
capillary lamp lamp laser lamp
Lamp power (kW) 1 2.4 2.4
Laser power 3 W/200 Hz
Bandwidth (nm) 235-285 240-260 3 pm @ 248 244-252
Uniformity (%) ±3 ±2 — ±1
Projection optics
Type Reflective Catadioptric Refractive Catadioptric
NA 0.167 0.35 0.42 0.5
Scanned field
Shape Arc Arc Circle Rectangle
Height (mm) 125 20.3 22
Radius (mm) 115 20
Width (mm) 4 1 5
Printed field 125-mm wafer 20 mm X 32.5 mm 15 mm X 15 mm 22 mm X 32.5 mm
Stage
Bearings Air Air Needle Air
Wafer (mm) 125 200 200 200
Alignment TTL TTL Off-axis TTL
Illumination Dark field Reverse dark field Dark field Reverse dark field
Distortion (nm) ±250 (98%) ±70 ±120 ±35
(Dist & Mag)
Overlay
Tool to tool (nm) 350 (98%) 150 (98%) 150 {x + 3o-) 90 {x + 3o-)
Ideal throughput 100/hr 50/hr 24/hr 50/hr

achieve because the DUV illumination was not centered alignment can be adjusted during the scan of each field to
in the scanned slit. match the topography and previous level pattern. With a
bright illumination source, high throughput can be
• 1985 to 1992 achieved because the stage can be scanned at high speeds.
As the 16Mb DRAM development program was initiated, The first step-and-scan tool from the Silicon Valley
there was a need for resolutions of 0.5 jum, the Group [18] required a 2.4-kW lamp and an arcuate light
introduction of larger product chips, and the use of tunnel to provide a high-intensity uniform exposure dose
200-mm wafers. This led IBM to acquire a tool from at full scan speed. The 0.35-NA projection optics are of
Perkin-Elmer designed specifically for DUV. This was the the reflective ring-field type with 4X magnification
first tool (Table 1) based on the step-and-scan principle capability added (Figure 19). In practical implementation,
[17]. In tools of this type, the wafer is stepped to a new lenses are added for aberration correction. The alignment
field, which is then scanned; this continues until all fields of the projection optics required a specially developed
have been scanned (Figure 18). DUV interferometer to reach diffraction-limited
Tools of the step-and-scan type are attractive for performance.
microlithography because they are able to print large A novel permanent magnet planar motor system and
fields at high wafer throughputs. Good resolution and low air-bearing wafer stage were developed to step and scan
distortion can be obtained because the scanned field is the wafer at velocities of 50 to 65 mm/s. The reticle and
small compared to the printed field and can be well wafer stage were synchronized by master-slave servo
corrected optically at higher NA values. Good linewidth control to 1:40 nm. Through-the-lens viewing was
16 control and overlay can be obtained because focus and implemented at the 488-nm and 512-nm argon laser lines

S. J. HOLMES, p. H. MITCHELL, AND M. C. HAKEY IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997
to provideflexibilityagainst thin-film interference effects.
Active vibration isolation and temperature-controlled, Concave minx)r
chemically filtered air were provided to limit Object
environmental influences on the projection optics and '' ^^^
^ Convex ^'"^ _^
wafer. \.^rror ' ^ ^
This tool achieved a DOF greater than ±0.75 p,m at a Optical axis ^~~^-~xc^'^cfn •'^^~^^<i^
resolution of 0.5 txm. Full-field distortion was measured
at s70 nm, and overlay capability on oxide wafers of —-7^^^^^^ Intermediate
/^^^ image Concave
150 nm (98%) was achieved by using six-field global fine mint>r
alignment. Product overlay performance for manufacturing
tools of this type was 120 nm to 200 nm depending on the Concave maot
level. In production, the step-and-scan tool was capable of
several hundred wafers per day and achieved reliability in
excess of 200 hr mean time between fails (MTBF).
A 0.42-NA DUV Nikon stepper (Table 1) was also used Schematic diagram for the projection optics of a 0.36-NA DUV
step-and-scan exposure system.
for applications with ground rules of 0.5 /j,m or less. The
all-quartz refractive lens of this tool required a <3-pm-
bandwidth excimer laser illumination source because of
the single-material optical design. An advanced Cymer
laser source was required for pulse-to-pulse stability and
dose accuracy. The condenser optics relied on a fly's-eye
lens and a vibrating mirror to achieve dose uniformity and
low speckle. The condenser optics were pressurized Reticle
slightly to prevent the accumulation of airborne
contaminants on the lens surfaces.
This tool achieved a DOF of approximately 1.0 /j,m at a
resolution of 0.45 /xm and an overlay of <150 nm on
product. The DUV stepper, which provided reliable
production capacity, has a throughput of approximately
two hundred wafers per day.

• 1993 to 1995
A 0.5-NA DUV step-and-scan tool (Table 1) was
developed for resolutions of 0.35 /xm and smaller [19].
The optics and development of the optional off-axis
broadband viewing system represent significant changes wmm^
from the original step-and-scan tool. Afly's-eyelens and S Schematic diagram for the projection optics of a 0.5-NA DUV
light polarization are used to more than double the uniform J step-and-scan exposure system. (With permission, [18].)
exposure power to 20 mJ/cm\ The 5-mm-by-22-mm
rectangular scanned field is produced using a compact
beam-splitter cube design [19] (Figure 20). Through-the-
lens viewing was improved and an off-axis viewing system
added to provide viewing at higher NA with broadband
A high-repetition-rate excimer laser exposure source for
illumination.
these tools will provide enough power to expose less
This tool achieves a DOF of ±0.40 ^m at a resolution
sensitive resists at higher stage speeds. The 0.6 NA will
of 0.35 /xm and a full-field distortion that is significantly
provide 0.25-/xm images, but with a very small (0.4-/xm)
lower at £35 nm. Global fine alignment achieves an
depth of focus. The use of off-axis illumination and
overlay of 90 nm on oxide films and a product overlay of
variable a should partially alleviate the depth-of-focus
90 to 150 nm depending on the level.
limitations. Overlay will be improved because optical
distortions become smaller, and better viewing and stage
• Beyond 1996 capabilities will be available. Wafer throughputs and
Step-and-scan tools equipped with a 0.6-NA lens for productivity will improve because the stages are being
0.25-/xm resolution will soon be the standard DUV tool. driven faster. 17

IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997 S. J. HOLMES, P. H. MITCHELL, AND M. C. HAKEY
 Lithography outlook: 1996-2000 9. D. E. Seeger, D. C. La Tulipe, Jr., R. R. Kunz, C. M.
Optical lithography continues to push beyond the Garza, and M. A. Hanratty, "Thin-Film Imaging: Past,
Present, Prognosis," IBM J. Res. Develop. 41, 105-118
anticipated limits, as state-of-the-art I-line production (1997, this issue).
approaches 0.35-^ni features and as high-NA D U V 10. (a) S. Holmes, R. Levy, A. Bergendahl, K. Holland, J.
tools achieve sub-0.25-/j,m capability [20]. D U V resist Maltabes, S. Knight, K. C. Norris, and D. Poley, "Deep
Ultraviolet Lithography for 500-nm Devices," Proc. SPIE
performance will continue to improve as diffusion effects 1264, 61 (1990). (b) S. Holmes, A. Bergendahl, D. Dunn,
related to the chemical amplification process are M. Hakey, K. Holland, D. Humphrey, S. Knight, D. Poley,
minimized and resin dissolution characteristics are P. Rabidoux, K. C. Norris, J. Sturtevant, and D. Writer,
"Deep UV Lithography for the Manufacture of 16-Mb
enhanced. Circuit designs compatible with off-axis DRAM Devices," Proc. SPIE 1671, 57 (1992). (c) J.
illumination, combined with the availability of phase-shift Sturtevant and S. Holmes, "Deep-UV Lithography in 16-
reticle inspection and repair equipment, will further Mbit DRAM Manufacturing," Microlithography World, pp.
17-22 (August 1993).
extend the capability of optical lithography. Scaling the
11. J. Sturtevant, S. Holmes, T. Van Kessel, P. Hobbs, J.
exposure wavelength an additional 20% with 193-nm Shaw, and R. Jackson, "Post Exposure Bake as a Process
systems [21], combined with these other techniques, Control Parameter for Chemically Amplified Photoresist,"
Proc. SPIE 1926 (1993).
should provide a path to a sub-0.15-^m lithography
12. W.-S. Huang, R. Kwong, A. Katnani, M. Khojasteh, and
capability. K. Lee, "An Environmentally Robust Positive Tone
Chemically Amplified Resist—KRS," Proceedings of the
Acknowledgments 10th International Conference on Photopolymers, Mid-
Hudson Section, Society of Plastics Engineers, 1994, pp.
The authors gratefully acknowledge Grant Willson, 96-106.
Hiroshi Ito, Nick Clecak, Russ Wendt, Clint Snyder, Bill 13. (a) S. Holmes, D. Sundling, J. Adkisson, J. Sturtevant, M.
Brunsvold, Will Conley, R o b Wood, George Hefferon, Hakey, D. Horak, W. Conley, and A. Katnani, "Gate
Conductor Lithography for 350-nm Devices," Proceedings
Karey Holland, Al Bergendahl, John Sturtevant, Paul of the 10th International Conference on Photopolymers,
Rabidoux, Denis Foley, K. C. Norris, Steve Lapine, Mid-Hudson Section, Society of Plastics Engineers, 1994,
Curt R u d e , Roger Barr, Bob Cogley, Bob Batterson, pp. 396-405. (b) S. Holmes, M. Hakey, J. Sturtevant, and
D. Dunn, "Overview of DUV Lithography for 350-nm
Mike Charney, and Hal Linde. CMOS Device Fabrication," Proceedings, Semicon/Kansai-
Kyoto '93 Technology Seminar, 1993, pp. 85-96.
References 14. D. G. Chesebro, J. W. Adkisson, L. R. Clark, S. N.
Eslinger, M. A. Faucher, S. J. Holmes, R. P. Mallette,
1. J. D. Buckley, "Expanding the Horizons of Optical E. J. Nowak, E. W. Sengle, S. H. Voldman, and T. W.
Projection Lithography," Solid State Technol. 25, 77-82 Weeks, "Overview of Gate Linewidth Control in the
(May 1982).
Manufacture of CMOS Logic Chips," IBM J. Res. Develop.
2. M. Hakey and W. Straub, "Advanced IX Projection 39, 189-200 (1995).
Lithography,"/. Electron. Mater. 11, 813-830 (1982). 15. C. A. Mack and J. E. Connors, "Fundamental Differences
3. (a) H. Ito and C. G. Willson, Polym. Eng. Set. 23, Between Positive and Negative Tone Imaging," Proc. SPIE
1012-1018 (1983). (b) H. Ito and C. G. Willson, in 1674, 328 (1992).
Polymers and Electronics, ACS Symposium Series, 16. (a) W. Conley, R. Sooriyakumaran, J. Gelorme, S.
No. 242, T. Davidson, Ed., American Chemical Society, Holmes, M. Petryniak, R. Ferguson, R. Martino, P.
Washington, DC, 1984, pp. 11-23. (c) H. Ito, J. Frechet, Rabidoux, and J. Sturtevant, "Negative Tone Deep-UV
and C. G. Willson, "Positive- and Negative-Working Resist for 16-Mb DRAM Production and Future
Resist Compositions with Acid Generating Photoinitiator Generations," Proc. SPIE 1925, 11 (1993). (b) W. R.
and Polymer with Acid Labile Groups Pendant from Brunsvold, W. E. Conley, J. D. Gelorme, R. Nunes, R.
Polymer Backbone," U.S. Patent 4,491,628, 1985. Sooriyakumaran, S. J. Holmes, and J. L. Sturtevant,
4. H. Ito, "Chemical Amplification Resists: History and "Further Improvements in CGR Formulation and
Development Within IBM," IBM J. Res. Develop. 41, Process," Proc. SPIE 2195, 329-340 (1994).
69-80 (1997, this issue). 17. D. A. Markle, "The Future and Potential of Optical
5. J. Maltabes, S. Holmes, J. Morrow, R. Barr, M. Hakey, G. Scanning Systems," Solid State Technol. 27, 165 (1984).
Reynolds, W. Brunsvold, C. G. Willson, N. Clecak, S. 18. C. Karatzas and J. D. Buckley, "Step-and-Scan: A Systems
MacDonald, and H. Ito, "IX Deep UV Lithography with Overview of a New Lithography Tool," Proc. SPIE 1088,
Chemical Amplification for 1-Mbit DRAM Production," 424-433 (1989).
Proc. SPIE 1262, 2-7 (1990). 19. H. Sewell, "Step-and-Scan: The Maturing Technology,"
6. H. Ito, "Chemically Amplified Resists—History and Proc. SPIE 2440, 49-60 (1995).
Recent Progress," Proceedings of the 10th International 20. M. D. Levenson, P. J. Silverman, R. George, S.
Conference on Photopolymers, Mid-Hudson Section, Wittekoek, P. Ware, C. Sparkes, L. Thompson, P.
Society of Plastics Engineers, 1994, pp. 1-11. Bischoff, A. Dickinson, and J. Shamaly, "Welcome to
7. J. Sturtevant, S. Holmes, and P. Rabidoux, "Post- the D U V Revolution," Solid State Technol. 38, 81-98
Exposure Bake Characteristics of a Chemically Amplified (1995).
Deep-Ultraviolet Resist," Proc. SPIE 1672, 114-124 21. M. Hibbs, R. Kunz, and M. Rothschild, "193-nm
(1992). Lithography at MIT Lincoln Lab," Solid State Technol. 38,
8. S. MacDonald, N. Clecak, R. Wendt, C. G. Willson, C. 69-78 (1995).
Snyder, C. Knors, N. Deyoe, J. Maltabes, J. Morrow, A.
McGuire, and S. Holmes, "Airborne Chemical
Contamination of a Chemically Amplified Resist," Proc. Received February 9, 1996; accepted for publication
18 SPIE 1466, 2-12 (1991). December 2, 1996

S. J. HOLMES, P. H. MITCHELL, AND M. C. HAKEY IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997
 S t e v e n J. H o l m e s IBM Microelectronics Division, Burlington
facility, Essex Junction, Vermont 05452 (SHOLMES at
BTVLABVM, [email protected]). Dr. Holmes is a
photolithography development engineer in the Emerging
Technologies Department. He received a B.S. in chemistry
from Yale University in 1979, and a Ph.D. in chemistry from
M.I.T. in 1983. After postdoctoral studies at Purdue in
organic chemical synthesis, he joined IBM at its Essex
Junction, Vermont, semiconductor development facility.
Dr. Holmes has worked on DUV resist and applications
development since that time, with projects including 1Mb and
16Mb DRAM development, logic gate conductor and logic
local interconnect lithography. He is currently working on
lithography development for sub-quarter-micron logic and
memory applications.

P e t e r H. Mitchell IBM Microelectronics Division, Burlington

facility, Essex Junction, Vermont 05452 (PMITCHEL at
BTVMANVM, [email protected]). Mr. Mitchell joined
IBM in 1968 at the Microelectronics Division semiconductor
manufacturing facility in Essex Junction, Vermont. He holds
B.S. and M.S. degrees in electrical engineering from Cornell
University and a professional degree in electrical engineering
from Massachusetts Institute of Technology (MIT). Mr.
Mitchell has worked with DUV exposure equipment for the
past ten years. Prior to that he worked with hot process
equipment and computer monitoring and control of
semiconductor manufacturing equipment.

Mark C. H a k e y IBM Microelectronics Division, Burlington

facility, Essex Junction, Vermont 05452 ([email protected]).
Mr. Hakey received his undergraduate degree in chemistry
from St. Michael's College in Winooski, Vermont, in 1972 and
attended graduate school at the University of Vermont, also
in chemistry, from 1972 to 1974. Subsequently, he joined
Union Carbide Corporation, where he worked for five years
on electroplating and injection molding processes. In 1978
Mr. Hakey joined IBM, where he was originally involved in
lithography process development for G-line systems. He
subsequently worked in I-line and DUV systems and tools,
later managing lithography and etching groups. In the mid-
1980s, he worked on teams qualifying 1Mb DRAM chips for
IBM, and in the late 1980s and early 1990s managed the
technology development team for 16Mb era memory and
logic products. Technology innovation implemented into
manufacturing included DUV lithography on step-and-scan
systems, positive and negative DUV resist systems, shallow
trench isolation, and ultrahigh-aspect-ratio DRAM storage
node trenches. Since 1994, Mr. Hakey has managed the
Emerging Technologies Department based in the Advanced
Semiconductor Research Center and in Burlington, Vermont.

19

IBM J. RES. DEVELOP. VOL. 41 NO. 1/2 JANUARY/MARCH 1997 S. J. HOLMES, P. H. MITCHELL, AND M. C. HAKEY