Latch-up in FinFET technologies

Krzysztof Domanski
Intel Deutschland GmbH, 85579 Neubiberg, Germany; e-mail: [email protected]

Abstract—Low-power FinFET technologies pose new The summary and a brief outlook are given in Section VI.
challenges for latch-up safe design. Downscaling of the feature
size causes significant drop of the trigger current and holding II. LATCH-UP PARAMETERS IN TECHNOLOGY
voltage in the latch-up (LU) victims (standard-cell logic). It is
A commonly accepted measure to describe the sensitivity
accompanied by an increase of resistance in the wells and tap-
connections. The increase of well resistance causes a drop in the
of the manufacturing process to latch-up is the assessment of
efficiency of latch-up guard-rings around aggressors (diffusion at amplification factors ß=Icollector/Ibase in parasitic npn and pnp
IO). Weak victims and inefficient guard-rings boost the latch-up transistors [1,6]. ß can be used for comparison with other
hazard in FinFET, compared to a planar process. New strategies technology nodes, or for modeling of parasitic effects in
for latch-up safe design are described. equivalent circuits. The parasitic bipolar transistors form the
parasitic thyristor in various victims [4,5], as well as help to
Keywords—latch-up, LP-CMOS, FinFET, guard-ring shunt the latch-up current from bulk [2,3,4], if formed to
efficiency, parasitic SCR, thyristor, blast zone guard-ring at aggressor. The amplification factors ß depend on
several properties of silicon.
I. INTRODUCTION Because of increasing operating frequency of circuits in
The low-power (LP) mobile technologies have evolved new technology generations, the substrate resistivity was
over several process generations to provide cheaper products, increased from 1 - 2 ȍ·cm to 10 - 20 ȍ·cm (high-resistivity
smaller area, lower leakage, and more performance in terms of substrate). The diffusion length of carriers in p-bulk increases
speed and computation power. The new process parameters with reducing doping concentration [1,6], and thus affects the ß
and device geometries make latch-up safe design an of long-base-npn/pnp between injector and victim (Fig. 1). The
increasingly challenging task. larger the diffusion length of the carriers in bulk [1], the more
The size of the transistors and spacing between them is current is collected by the victims. Thus, in high-resistivity
constantly reducing in every new technology node. To substrates, a larger area of the chip is affected by substrate
maintain downscaling, the leading-edge modern technologies current injected from devices at input-output cell (IO).
use 3D FinFET geometry of NMOS and PMOS transistors. As The doping concentration of the n-well and p-well impacts
in planar processes, the source and drain of FinFET transistors both the ß of guard-rings around the aggressor (Fig. 1) and the
are processed with n and p diffusions in p or n-well. Thus, as is ß within the parasitic thyristors of the victim. In general, the
well known from planar technologies, parasitic thyristors [1] well doping concentration drops in every technology
accompany the logic inverters in FinFET. In consequence of generation for performance reasons, e.g., well isolation. The
downscaling and the FinFET process, the holding voltage and accompanying increase of n or p-well sheet-resistance across
trigger current of a thyristor involved in the logic can drop. technology generations is shown in Fig. 2. The increase of the
There exist several LP-CMOS/FinFET processes on bulk in well-resistance is caused not only by reduced doping
industry. This work is an overview of main trends observed concentration, but overwhelmingly by the shrinking depth of
across the foundry landscape. The example data presented is the wells and constantly reducing width of the wells in e.g.
representative of these technologies in general rather than standard-cells-tracks. The design rules in modern CMOS
specific to a certain foundry. processes allow the worst-case dimensions of the well to be
In Section II the impact of the silicon properties in new more than 100 squares (see example in Fig. 3). This assumes a
technology generations is discussed. worst case well size 0.5 μm × 50 μm. It should be noted that
The spacing between diffusions tends to shrink with the resistance of n-well or p-well in modern FinFET processes
technology downscaling. In Section III the impact of reduced can be >1 kȍ/square.
spacing in FinFET and changed geometry of latch-up victim
n-diffusion at IO PAD
(core logic) will be discussed. VSS VDD
Also, the latch-up injectors (diffusions at IO) in FinFETs VDDvictim VSSvictim

have different properties, compared to similar designs made in P+ P+ P+ N+ N+ P+

N+ P+ N+ N+ N+
planar technology. In Section IV, the protection of latch-up STI

injectors by guard-rings will be evaluated. n-well p-well R n-well Spacing

parasitic npn in
<200um
An increased latch-up-sensitivity of victims and aggressors parasitic npn to - R p-bulk
- victim
guard-ring
requires the development of new latch-up rules in FinFETs. parasitic pnp
R p-well

These rules typically add more complexity to the design and an p-bulk
long-base parasitic npn in victim
to victim
additional area overhead. In Section V the necessary
modifications of the latch-up concepts will be discussed. Fig. 1. The latch-up injection to n-diffusion at PAD. The relevant
parasitic transistors and resistances are indicated.

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 1.2 taps maximal tap to tap spacing (2 x tap to diffusion spacing) taps

Normed maximal resistance of the well (a.u.)

1 Well-sheet-resistance
between MOS and most
remoted tap at exemplary
0.8 tap-spacing= 40 ʅm
p-diode p-guard-ring
aggressor

0.6 n-diode
aggressor n-guard-ring

n +/p -well
0.4 n +/n -well (n -tap)
p +/p -well (p- tap)
p +/n -well

0.2 a) large LU victim (~100 μm x 100 μm) resistance in squares between

most remoted PMOS and n-tap
~40 μm n-tap to p-diffusion spacing n-tap
n-well ….
0 width
PMOS fins of well
100 150 200 0 50
250
Technology node (nm) ~40 μm n-tap to p-diffusion spacing
b) small LU victim (~40 μm x 10μm)
Fig. 2. The well resistance between diffusion and tap in one track of worst
case standard-cell layout (see example in Fig. 3a) across LP-CMOS/FinFET Fig. 3. Sketch of latch-up victim: a) the large victim made of several well-
technology generations. tracks, b) the classical small victim (two well tracks); the cross-section and
connections are referred in Fig. 1.
The wells are connected to supply by taps (Fig. 1). The
increase of well resistance can be compensated by reduction of and modern sub-0.1μm planar processes the holding voltage
the tap-spacing in the logic. It is, however, not preferred reaches about 1 V. That shift is already observed for some non-
because of the area overhead. The maximal tap-spacing tends worst-case arrangements of classical 4-layer SCR victims,
to be similar in FinFET and planar process. shown in Fig. 3b. For large FinFET victims with new geometry
The n-tap and p-tap area shrinks with reducing feature-size. (Fig. 3a) the holding voltage drops even below 0.85 V. The
That causes an additional increase of resistance in the well typical VDD in core can be in the range of 0.5 to 1.2 V.
connection. The FinFET process itself might provide higher In the planar technologies the LU fails in large arrays of
resistance per area of tap. However, even if single tap would core-logic are, so far, reported only in very few special cases
reach the resistance in range of several kilo-ohms, it might be [7]. Whereas, in FinFET the large areas of standard-cells can
still only a fraction of the total well resistance in the standard- latch in standard applications, and are sensitive to latch-up
cell layout with worst-case geometry of the wells (Fig. 3a). because of ~40 ʅm tap-spacing rules for core. The ~40 ʅm tap-
spacing results in essentially floating wells for the parasitic
III. LATCH-UP IN VICTIM SCR. The resistance of the well can be as high as ~100 kȍ.
A. Holding voltage in standard-cell victims To increase the holding-voltage, the tap-spacing should be
In both planar and FinFET processes the holding voltage is reduced. The rules for tighter logic tap-spacing around the
strongly dependent on the geometry of the victim. For planar injector (referred to as a “blast zone”) must apply for all
technologies the holding voltage is usually measured on simple voltage classes in FinFET processes.
4-layer silicon-controlled-rectifier (SCR) test structures with B. Internal LU trigger current in standard-cell victims
worst-case spacing [1]. The worst-case anode-cathode spacing The trigger current of parasitic thyristors in the core logic is
is minimum. a function of the voltage drop in the base of the parasitic npn
The anode/cathode spacing to n/p-tap is usually at and pnp. The resistance in the base of the npn/pnp is given in
maximum value allowed by design rules. For core device squares of n-well or iso-p-well in triple-well process (in dual-
foundries usually offer tap-spacing in the range of ~40 μm. In well p-substrate contributes to resistance).
literature it is also assumed that the larger is the victim’s area In Fig. 4 the latch-up trigger currents in the classical victim
the lower is the holding voltage [1]. in FinFET versus planar processes are presented. The
Because of small size of the transistor source/drain (S/D) comparison of trigger currents clearly shows that the FinFET
diffusions and narrow metallization, the traditional worst-case victim is much more sensitive. Both structures are made using
LU detectors (Fig. 3b) might not necessarily reflect real worst- worst-case minimum anode to cathode spacing in both
case layouts. In Fig. 3a, a new type of latch-up detector for technologies. Of course, the anode-cathode spacing is smaller
FinFETs is shown. The victim and aggressor are arranged as in in FinFET than in planar.
an area-array IO layout. The large area of the victim provides The large LU-victim with standard-cell tracks of well (Fig.
more realistic holding voltages. The connection of the victim is 3a) indicates higher internal LU trigger current due to larger
shown in Fig. 1. perimeter of parasitics. However, it represents a realistic layout
In general, the holding voltage for core device in older case, and the worst case for the holding-voltage. It shows also a
planar technologies is assumed to be above the supply voltage realistic trigger current during the IO-latch-up injection to the
for most of victim’s geometries. As shown in Fig. 4, in FinFET aggressors (see p-diode or n-diode in Fig. 3a).

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2C.4-2
 Internal LU small planar 1
ß of n+/p-well/n-well
victim
Internal LU trigger current (a.u.)
Internal LU in large 0.9 npn in planar injector
FInFET victim (dual well)
Internal LU small FinFET 0.8 ß of n+/p-well/n-well

Current gain (Ic/Ib)

victim npn in FinFET injector
0.7 (dual well)
0.6
0.5
0.4
0.3
0.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6
Internal LU trigger voltage (V) Voltage Emitter-Collector (V)
Fig. 4. Measurement of internal LU in victim under positive injection to Fig. 5. Comparison of FinFET to planar: the measurement of the
anode: large FinFET victim (see Fig. 3a), small victim planar/FinFET (see amplification factor of parasitic npn to n-guard-ring around typical ESD
Fig. 3b). diode at PAD (see cross-section in Fig. 1, layout in Fig. 3a).

IV. LU GUARD-RING IN FINFET TECHNOLOGIES escapes to from injector area and can be collected by the wells
The latch-up aggressors (diffusions at IO PAD) are either of victim.
ESD devices or multiple logic drivers. In a latch-up event the A. Positive injection versus negative injection at IO
diffusions at IO can inject current to the substrate via body- The measurements of latch-up trigger currents in the test
diodes [2,3,4]. The latch-up guard-rings are used to collect the structures indicate that in the FinFET technologies the injection
carriers injected into the substrate (Fig. 1). The n-well-guard- of positive current (holes) can cause latch-up in victim at the
ring forms a parasitic npn to the n-diffusion at PAD; the same or even lower levels of IO-current than the injection of
parasitic pnp is formed between p-diffusion at PAD and p- negative current (electrons). Latch-up is much more frequently
well-guard-ring. The parasitic transistor activates during the reported as a result of negative current injection pertaining to
LU injection; carriers flow to its collector and are shunted to planar technologies [3,4]. Also, the guard-rings in planar
supply. technologies are much larger for n-injectors [3,4].
As discussed earlier, wells are becoming more and more
resistive. This makes them less efficient as guard ring B. Aggressor in dual well versus triple well.
collectors. The collection efficiency of the guard-rings made in The use of triple-well to enclose the injector is a standard
a FinFET process is significantly smaller, as shown in the technique used in industry [2] to minimize the current injected
measurements of amplification factor ß in Fig. 5. The smaller ß to substrate and, thus, keep it below the trigger value at the LU
of the npn transistor to n-guard-ring is, the more current is victim.
transported by the long-base-npn to diffusions to victims. The In FinFET aggressor, the ß of parasitic npn to triple-well-n-
ß deterioration is observed also for p-aggressor surrounded by guard-ring is higher than in dual-well. It results in a drop of the
p-guard-rings in FinFET versus planar. current escaping from triple-well-n-guard-rings to p-bulk.
More current at diode of aggressor in triple-well is needed to
V. LATCH-UP IN VICTIMS CAUSED BY IO INJECTION reach critical current density in the p-bulk beneath the victim.
According to the JEDEC JESD78E LU test, the latch-up Since more current is needed at triple-well aggressor to trigger
robustness of an IO PAD is tested by injection of ±100mA victim, the IO LU robustness increases in triple-well FinFET.
current. At that current the IO pin should not provoke any The FinFET process is likely not impacting the n-band
permanent current increase at supply (latch-up of parasitic resistivity.
thyristor). Compared to planar technologies, the trigger C. The latch-up blast zones around of the aggressor
currents at IOs in FinFET are likely to be lower because of two To protect the logic from latch-up, the tap-spacing must be
mechanism which increase the current density in substrate and modified in large logic areas around of the aggressor. Up to
increase the sensitivity of the victim: spacing from aggressor even several blast zones with different
• The amplification factor ß of parasitic npn and pnp in constrains for tap-spacing must be defined. In example in Fig.
the victim increases, the victim latches at a lower 6 the blast zone “A” imposes constraints on guard-rings around
current collected from substrate. of logic to separate NMOS from PMOS. The blast zone “B”
• The amplification factor ß of guard-ring decreases. puts constrains on the tap-spacing and can extend as far as
The guard-rings are less effective. More current ~200 ȝm from the injector.

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2C.4-3
 Redesign needed for IP in blast zone A, transition of the process to sub-0.1 μm process on 300 mm
B, placed in vicinity of injector. wafer material (>10 ȍ·cm resistivity and epitaxial layer
beneath the p-well).
part of layout
affected by In sub-0.1 μm planar CMOS technologies utilizing high-
blast zones A, B resistivity substrates (>10 ȍ·cm), blast zones in the range of
200 μm were reported [5]. These were required for parasitic
blast zone A: special arrangement
of taps/guard-ring required thyristors involving floating n-well and grounded n-well in
blast zones A
complex overvoltage analog designs used in power
PMOS p diffusion at IO blast zones B management integrated circuits (PMIC). In sub-0.1 μm CMOS
n diffusion at IO
n-tap technologies the blast zones were not required for the standard-
p-tap aggressors
cell logic in base-band ICs.
IP boundary
NMOS With introduction of the FinFET on 10 ȍ·cm epitaxial
wafers, the high-resistive bulk material is accompanied by
reduced
tap spacing high-resistive wells in standard-cell logic and guard-rings. The
blast zone B: reduced
tap spacing required
resistance of the wells in FinFET increases because of changes
of doping concentration and reducing size of the wells. In
addition, downscaling of spacing in inverters has driven the
Fig. 6. Blas zones for macros with logic-devices around of latch-up-aggressor holding-voltage in latch-up victims deep below the core-
in FinFET process. supply. Dangerous parasitic thyristors in core logic located in
high-ohmic well tracks are likely to trigger in FinFET.
Unlike in a planar process, in FinFET the injectors All those technology changes accumulated in FinFET
originating from both n and p diffusion require large blast process result in a massive increase in the blast zone size by as
zones. In planar process the n-injector is regarded as more much as 10× around IO-aggressors for victims at any supply
critical. (including core voltage). In FinFET the LU blast zones apply
The complexity of latch-up design rules increases further to logic at IO and core voltage, as well as to overvoltage
due to blast zones for core-devices, which can latch in FinFET. tolerant analog designs.
In low-power CMOS designs there are many blocks running at The FinFET core-logic is also more prone to latch-up in the
core-voltage. These can be mixed with e.g., IO cells, JEDEC JESD78E LU-overvoltage test. During the supply test
containing aggressors inside. The latch-up in blast zones the increased leakage of the core devices possibly can cause
around of IO cells can trigger rework of macros or top-level- voltage drops and trigger the parasitic thyristors at supply
design. under stress.
Needless to say, top-level design rework can severely affect Further downscaling of the FinFET technologies might
project schedule and increase cost in terms of area and work. result in increased sheet resistance of the wells, increased
Concurrent engineering is mandatory to mitigate the latch-up sensitivity of logic to latchup, and weaker guard-rings.
risk in chips designed in FinFET. The macros have to be
developed knowing in advance their placement on die, or 160
tighten tap-spacing rules have to be used for whole macros if blast zone around of
reuse of IP is assumed. 140 injector in LP CMOS /FinFET
Blast zone around of injector (ʅm)

process generations
VI. SUMMARY
120
With the ongoing technology downscaling there is a strong
demand to increase circuit speed. In the first generations of change from planar to FinFET
100 300 mm EPI wafers,
LP-CMOS (for mobile applications) the speed was in range of bulk resistivity: 10 ȍcm
1 GHz. With the introduction of 3G, and 4G the speed 80
5G planar process, change from
requirements grew to 6 GHz. In modern 5G applications even 200mm to 300 mm EPI wafers,
70 GHz is required. To improve the high-frequency bulk resistivity: 10 ȍcm
60
performance of various components (e.g., coils) the doping 4G
concentration of substrate is reduced, resulting in change of planar process on 200 mm
40 wafer, bulk resistivity: 1 ȍcm
resistivity from ~1 ȍ·cm to >10 ȍ·cm. As demonstrated in
3G
this paper, that change contributes to larger size of blast zones 2G 1G
for logic in latch-up concepts for low-power ICs. 20
The complexity of latch-up rules can be depicted by the
range of the blast zone in technology node (Fig. 7). 0
In the >0.1 μm planar CMOS process the blast zones were 0 50 100 150 200 250
restricted to guard-ring systems around the injectors. Technology node (nm)
As shown in Fig. 7, the first noticeable increase of the blast Fig. 7. Blast zone for logic around injectors for various low-power technology
zones for the logic in the designs was required after the nodes. Rough correlation between communication standard and technology is
indicated.

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2C.4-4
 Significantly larger guard-rings or special implants for guard- Russ, Christian & Alvarez, Daniela. (2006). Investigation of External
Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk
rings might be necessary to provide protection against IO CMOS Technology. IEEE International Reliability Physics Symposium
current injection. Proceedings. 145 - 150. 10.1109/RELPHY.2006.251207. 6
The technology downscaling is accompanied by the [3] Domanski, Krzysztof & Heer, Michael & Esmark, Kai & Pogany,
reduction of core-supply voltage. It would be beneficial for Dionyz & Stadler, Wolfgang & Gornik, Erich. (2007). External
latch-up development in future FinFET technologies if the (transient) latchup phenomenon investigated by optical mapping (TIM)
technique. 6A.3-1 . 10.1109/EOSESD.2007.4401773.
resulting holding voltage of parasitic thyristors shifts above
[4] Domanski, Krzysztof & Gossner, Harald. (2015). Soft fails due to LU
core-supply, or tap-spacing in core reduces. stress of virtual power domains. 1-8. 10.1109/EOSESD.2015.7314795.
[5] K. Domanski, J. Schneider, and A. Jungmann, “Method of SCR
VII. ACKNOWLEDGMENT detection in layout,” USPTO Pub. No.: US 2013/0019222 A1.
The author would like to express his gratitude to Nathan [6] F. Farbiz and E. Rosenbaum, "Modeling of majority and minority carrier
Jack, Michael Khazhinsky, Wolfgang Stadler and Harald triggered external latchup," 2008 IEEE International Reliability Physics
Symposium, Phoenix, AZ, 2008, pp. 270-277.
Gossner for assistance and valuable feedback during the work doi: 10.1109/RELPHY.2008.4558897
on this paper. [7] K. Domanski, S. Bargstadt-Franke, W. Stadler, M. Streibl, G. Steckert
and W. Bala, "Transient-LU failure analysis of the ICs, methods of
VIII. REFERENCES investigation and computer aided simulations," 2004 IEEE International
[1] Troutman R.R., “Latch-up in CMOS Technology,” Kluwer Academic, Reliability Physics Symposium. Proceedings, 2004, pp. 370-374.
New York, 1986 doi: 10.1109/RELPHY.2004.1315354
[2] Kontos, Dimitris & Domanski, Krzysztof & Gauthier, R & Chatty,
Kiran & Muhammad, Marinah & Seguin, Claire & Halbach, Ralph &

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