International Journal of Soft Computing and Engineering (IJSCE)
ISSN: 2231-2307, Volume-5 Issue-4, September 2015
Design of Area and Speed Efficient Square Root
Carry Select Adder Using Fast Adders Sanjeev. K, Sivananda Hariprasth, Saranya. M, Sandhya. G
Abstract: Area and speed are the most important design The results show a greater improvement in terms of delay objectives in integrated circuits. As addition is the basic operation and number of logic levels is reduced. The square-root carry of all computer arithmetic, adders are one of the widely used select adder is constructed by equalizing the delay through components in digital integrated circuit design. Since propagation of carry is of major concern in designing efficient two carry chains and the block multiplexer signal from adders, this paper presents different fast adders and their previous stage[.3] It is also called as non-linear carry select performance analysis. Among all the adders discussed Square adder. The existing modified SQRT CSLA uses Binary to root Carry Select Adder (SQCSA) provides a good compromise Excess-1Converter (BEC) instead of RCA with Cin-=1 to between cost and performance. As, Conventional SQCSA is still achieve lower delay and less area[2]. The RCA with Cin=0 area consuming due to dual Ripple Carry Adder(RCA)structures, is also replaced with fast adders like CLA CSKA and CSA modifications are done at gate level to reduce area. Modified SQCSA is designed using fast adders like Carry Skip Adder and analysis is done in terms of logic levels and delay. (CSA) and Carry Look-Ahead Adder (CLA) to increase the speed of operation. II. PREVIOUS TECHNIQUES Keyword: - (SQCSA), (CLA), (CSA), Conventional, designed, A. Carry select Adder (CSA): Carry, Adder, concern, adders, Among, Modified Carry select Adder (CSA) is one of the fastest adders used in I. INTRODUCTION many data processors to perform fast arithmetic functions. The carry select adder partitions the adder into several In rapidly growing electronic industry, faster units are not groups, each of which performs two additions in parallel only of concern for design but also smaller area and less using dual RCA‟s[4]. One copy evaluates the carry chain power become major concerns for design of VLSI circuits. assuming the block carry-inis „0‟, while the other assumes it So a VLSI designer has to optimize area delay and power to be „1‟. Once the carrysignals are finally computed, the constraints for increasing portability and battery life of correct sum and carry-out portable devices[1]. As we know millions of instructions per signals will be simply selected by a set of multiplexers [4] second are performed in micro processors speed of An example for carry select addition with carry input „0‟ operation is the most important constraint to be considered and Carry -in „1‟ is shown below while designing multipliers. These constraints are difficult 1010 1010 1011 1111 to achieve so depending on application compromise between 0000 0011 1111 1010 (Cin=0) constraints has to be made. There are many ways to design ---------------------------- adder [2]. The Ripple carry Adder (RCA) exhibits the most (sum): 1010 1110 1011 1001 compact design but slowest in speed because for an N-bit Cout=‟0‟ RCA, the delay is linearly proportional to N[2]. Thus for 1010 1010 1011 1111 large values of N the Ripple Carry Adder gives greater delay 0000 0011 1111 1010 (Cin =1) of all adders. An N-Carry Look-ahead Adder (CLA) gives --------------------------------- fast results when compared to RCA for N ≤ 4, but for large Sum: 1010 1110 1011 1111 values of N its delay increases. The structure of Carry Select -------------------------------- Adder is built using dual Ripple Carry Adders which Cout=‟0‟ increase area. In order to reduce the area and power Modified Carry Select Adder(MCSA) is implemented B. Modified carry Select Adder (MCSA) whereone ripple carry adder at each stage of addition is In Carry Select Adder more area is occupied because of dual replaced with BEC (Binary to Excess-1 Converter)[1].To Ripple Carry Adders (RCA) and also carry-out at every further increase the performance of MCSA the other RCA‟s stage must ripple[4].So in order minimize delay caused by are replaced with still faster adders like Carry Skip Adder one of the RC Awhose carry input is „1‟ and to optimize and Carry Look-ahead Adders long. area one RCA isreplaced with Binary to Excess-1 Converter (BEC), by which gate count will be reduced by a very large amount and computational time is optimized when compared to restof the adders as discussed above. Revised Version Manuscript Received on September 05, 2015. Depending upon the carry out bit of the previous stage Sanjeev. K, 3rd year Department of Electrical Communication thesum is selected either from RCA or BEC with the help Engineering, SNS College of Technology, Coimbatore (Tamil Nadu) India. Sivananda Hariprasth. N, 3rd year, Department of Electrical of2x1 multiplexer‟s at each stage.[5] An example of MCS Communication Engineering, SNS College of Technology, Coimbatore Operation is shown below by randomly considering input bit (Tamil Nadu) India. stream. Saranya .M, 3rd year, Department of Electrical Communication Engineering, SNS College of technology, Coimbatore (Tamil Nadu) India. 1010 1010 1011 1111 Sandhya. G, 3rd year, Department of Electrical Communication 0000 0011 1111 1010 Engineering, SNS College of Technology, Coimbatore (Tamil Nadu) India. (Cin=0)
-------------------------------------- Fig 2: 16-bit MCSA with CSA
Sum: 1010 1110 1011 1001 E. Regular SQRT CSLA 1010 1110 1011 1111 (BEC) The basic square-root Carry Select adder has a dual ripple 1 1 1 1010 (cin=‟0‟) carry adder with 2:1 multiplexer, themain disadvantage of --------------------------------------- regular CSLA is the large area due tothe multiple pairs of Sum: 1011 1111 1010 1111 ripple carry adder[5]. The regular 16-bitSQRT Carry select From the above example we observe that even adder is shown below afterreplacing RCA‟s with carry input „1‟ with BEC there is nochange in carry output and sum. C. MCSA with CLA This architecture is similar to 16-bit Modified Carry Select Adder, the only change is that we replace Ripple Carry Adder with Carry Look-ahead Adder with Cin=1 along with BEC [5]. As the delay of 4-bit Carry Look-ahead Adder is more when compared to 4-bit Carry Skip Adder.
Fig 3: 16-bit SQRT with CSLA
III. Regular SQRT CSLA with BEC
The modified 16-bit SQRT CSLA using BEC is shown in Figure below. The structure is again divided into five groupswith different sizes of Ripple carry adder and BEC Theparallel Ripple carry adder with Cin=1 is replaced with BEC[6].One input to the multiplexer goes from the RCA with Cin=0and other input from BEC. Comparing the individual groupsof both regular and modified SQRT CSLA, it is clear that theBEC structure reduces delay[6]. Fig 1: 16-bit MCSA with CLA But it is clear that ripple carryadders still result in carry D. MCSA with CSA propagation delay. As the delay in 4-bit Carry Look-ahead Adder is more whencompared to 4-bit Carry Skip Adder because of that reasonwe are replacing 4-bit Carry Look-ahead Adder with 4-bitCarry Skip Adder in order to reduce the delay and powerconsumption with minimum speed penalty.
Fig 4: 16-bit Modified SQRT with BEC
IV. WORK DONE
For designing more area and speed efficient adder the Ripple Carry Adder in Modified Square root Carry Select Adder is replaced with fast adders. In order to know the efficient adder that can possibly replaced with RCA an analysis done on
Modified SQRT CSLA by replacing RCA with CLA, It is observed that delay and number of logic levels for CSKA, Carry save adder[8]. The results are shown for all evaluation of final carry output are still reduced when fast adders. First in MCSA the RCA is replaced with CLA replaced with CSKA compared with CLA[[7]8]. For getting and the waveforms are shown below. And from the further optimized results CSKA is replaced with Carry Save synthesis report it is observed that area delay and log levels Adder and the waveforms are shown below. are reduced.
Fig 7: waveform of 16-bit SQRT MCSA with Carry save
Adder. It is inferred that SQRT MCSA with carry save adder gives better result. Fig 5: Output waveforms of 16-bit SQRT MCSA with BEC V. CONCLUSIONS In this paper three new architectures are presented for SQRT MCSA (Modified Carry Select Adder). Comparisons are made between different adders in terms of logic levels and delay. The proposed full adders show good performance and among the proposed SQRT MCSA‟s, MCSA with carry save adder show much optimized results.
REFERENCES 1. Kuldeep rawat, Tarek Darwish, and Magdy Bayoumi, “Alow power and reduced area Carry Select Adder”,45th Midwest Symposium and circuits and systems,vol.1,PP.467-470, March 2002. 2. O.J. Bedrij, “Carry-Select Adder”, IRE transactions on Electronics computers, vol.EC-11, pp.340-346, June 1962. 3. B. Ramkumar, Harish M Kittur and P. Mahesh Kannan, “ASIC implementation of Modified Faster Carry SaveAdder”, European journal of scientific research,vol.42,pp.53-58, 2010. 4. M.Moris Mano, “Digital Design”, Pearson Education, 3 rdedition 2002. 5. Singh, R.P.P.; Kumar, P.; Singh, B., “Performance Analysis of Fast Adders Using VHDL”, Advances inRecent Technologies in Communication and Computing, 2009. 6. A Tyagi. “A reduced area scheme for carry selectadders“, IEEE Trans. On computer, vol.42, pp.1163-1170,1993. 7. J.M. Rabaey, “Digital Integrated Circuits-A Design Perspective”, New Jersey, Prentice-Hall, 2001. 8. Abu-Shama and M. Bayoumi, “A New cell for low power adders,” in Proc. Int
BIBILIOGRAPHY Sanjeev. K, is pursuing 3rdyearB.E Electronics Fig 6: Output waveforms of 16-bit SQRT MCSA with and CSKA
communication engineering at SNS college of Technology, Coimbatore.
His area of interests are embedded system and electronic circuits. He hasattended a national level conference held at Tamilnadu College of Engineering, Coimbatore.
Saranya. M, is pursuing 3rd year B.E
Electronics and communication engineering at SNS college of technology, Coimbatore. Her area of interest are digital circuits, electronic circuits,VLSI design. She has attended a national level conference held at Tamilnadu College Of Engineering, Coimbatore.
Sivananda Hariprasath.N is pursuing 3rdyear
B.E Electronics and communication engineering at SNS College of technology, Coimbatore. His area of interest is embedded systems and digital electronics.
Sandhya.G, is pursuing 3rdyearB.E Electronics
and communication engineering at SNS college of technology, Coimbatore. Her area of interest are digital circuits and systems, embedded systems, VLSI design. She has attended a national level conference held at Tamilnadu College Of Engineering, Coimbatore.
