A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.

18μm CMOS
Chun-Cheng Liu1+, Soon-Jyh Chang1, Guan-Ying Huang1, Ying-Zu Lin1, Chung-Ming Huang2
1
Department of EE, National Cheng Kung University, Tainan, Taiwan (Email+: [email protected])
2
Himax Technologies, Inc., Tainan, Taiwan
Abstract
This paper presents a 10-bit SAR ADC using a variable
window function to reduce the unnecessary switching in DAC
network. At 10-MS/s and 1-V supply, the ADC consumes only
98 μW and achieves an SNDR of 60.97 dB, resulting in an
FOM of 11 fJ/Conversion-step. The prototype is fabricated in a
0.18μm CMOS technology.
Introduction
The DAC switching network in [1] saves 81% switching
energy and 50% total capacitance as compared to the
conventional one. However, the signal-dependent comparator
offset caused by the input common-mode voltage variation Fig. 2: The proposed SAR ADC.
degrades the ADC performance. Hence, this paper presents a
same time, the bottom plates of capacitors C1a~C4a are reset to
splitting monotonic switching procedure to maintain the
ground, and the others (C1b~C4b and C5~C9) are reset to Vref.
common-mode voltage during bit cycling.
Next, the comparators do the first comparison. The capacitor
Besides, the conventional SAR ADCs apply a binary search
C1b on the higher voltage potential side is pulled down to
algorithm to approach the closest digital code to match the
ground. On the lower voltage potential side, the capacitor C1a
input signal. In a typical conversion, the reference DAC is
is pulled up to Vref. Therefore, the common-mode voltage does
added or subtracted a binary-weighted voltage according to the
not change. To avoid complicated control logic and layout
comparator output in each bit cycles. In the last cycle, the
routing, the splitting monotonic switching method is only
difference between input signal and reference is less than one
applied to the first 4 MSB capacitors. The remaining
LSB. However, during the conversion, the difference increases
operations still use the switching method in [1]. The
when adds a large voltage to a small difference, that results in
common-mode voltage variation is diminished to only 1/16 of
unnecessary energy wasted. Fig. 1 shows the concept of our
that in [1]. The comparator dynamic offset problem becomes
idea. When the difference is small, this ADC does not add or
negligible in this 10-bit case.
subtract any voltages until the remaining bit cycling operations
Fig. 3 shows how to reduce the unnecessary switching in
could not reduce the difference to less one LSB. A variable
DAC network. Take the Phase 1 as an example. When the
window function is presented to ensure the difference does not
voltage difference of input signal and reference is located in
increase during the conversion. The multi-comparator SAR
the “No Switching” region, even no capacitors switched in this
ADCs [2-3] are able to reduce the risk of metastability and
cycle, the remaining bit cycling operations could reduce the
power consumption in comparators. This work uses the
difference to less than one LSB. Hence, this ADC does not
multi-comparator concept to perform the variable window
switch any capacitors in this bit cycle. On the contrary, when
function to reduce the unnecessary switching in DAC network.
the voltage difference is located in the “Switching” region, this
The method saves the power consumption in comparators,
ADC switches the relative capacitors according to the
capacitor networks and switch buffers at the expense of little
comparison. Otherwise the remaining bit cycling operations
hardware overhead.
could not reduce the difference to less than one LSB.
Circuit Description Two coarse comparators and a sub-DAC are added to
perform the function as shown in Fig. 3. In order to achieve a
Fig. 2 shows the schematic of the proposed SAR ADC.
variable window function in different bit cycles, the reference
Similar to the split capacitor array [4], the first 4 MSB
voltage Vr must be variable. Fig. 4 shows the variable window
capacitors in the capacitor array are all split into two equal
sub-capacitors to perform the splitting monotonic switching
method. At the sampling phase, the top plates of all capacitors
capture the input signal via the bootstrapped switches. At the

Fig. 1: The approximations of conventional and proposed methods. Fig. 3: The graph of proposed switching procedure.

978-1-4244-7641-1/10/$26.00 ©2010 IEEE 2010 Symposium on VLSI Circuits/Technical Digest of Technical Papers 241
function and Vr. A 6-bit sub-DAC generates the variable Vr.
The real Vr in this ADC is large than the ideal value about 8
LSB, the real window size is a little smaller than the ideal one.
Therefore, this ADC has about 8-LSB margin to tolerance the
sub-DAC and coarse comparator offset errors. For best
efficiency, the mechanism only used in first 4 MSB capacitors.
Even includes the overhead of the 6-bit sub-DAC, this method
saves 40~45% power dissipation in the capacitor network and Fig. 4: Variable window function.
switch buffers compared to [1]. Fig. 5 shows the digital error
correction logic, which consists of only 4 full-adders.
This ADC uses a dynamic comparator with a p-type input
pair. The dynamic comparator does not consume static current
and hence is suitable for an energy efficient design. Internal
control logic triggered by the global clock and comparator Fig. 5: Digital error correction logic.
output asynchronously generates internal control clocks,
which avoids a high frequency clock generator and makes the
sampling rate equal to the clock rate. This ADC uses
metal-oxide-metal (MOM) capacitors to construct the
capacitor array. The unit capacitor is about 5 fF, composed of 5
metal layers in a 4×4.8 μm2 area. The total input capacitance is
2.5 pF each terminal. According to simulation result, this ADC
saves about 17.6 % power consumption than the architecture in
[1]. Besides, with less capacitors switched, the DNL and INL
performance was improved especially around the middle of Fig. 6: Chip micrograph.
output codes. Hence, the linearity of ADC is enhanced.
0.4
Experimental Result 0.2
DNL [LSB]

The prototype is fabricated in a 0.18-μm CMOS technology. 0

The micrograph is shown in Fig. 6. The active core area is only -0.2
330×260 μm2. At 10-MS/s, 1-V supply and 1-MHz input -0.4
0 200 400 600 800 1000
stimulus, the measured static performances are plotted in Fig. 7. Output Code
The peak DNL and INL are +0.28/-0.34 LSB and +0.23/-0.38 0.4

LSB, respectively. The measured SNDR and SFDR are 60.97 0.2
INL [LSB]

and 79.4 dB, respectively. The resultant ENOB is 9.83 bit. Fig. 0
8 plots the measured SFDR and SNDR versus input frequency -0.2
and FFT spectrum with input frequency closes to Nyquist
-0.4
frequency. The analog circuit, including the S/H circuit and 0 200 400 600 800 1000
Output Code
comparators, consumes 32 μW, and the digital control circuit Fig. 7: Measured DNL and INL.
draws 50 μW. The capacitor networks and Sub-DAC consume
SNDR & SFDR (dB)

80
16 μW. The total power consumption of the ADC is 98 μW. SFDR
The prototype achieves an FOM of only 11 fJ/conversion-step. 70 SNDR

Table I summarizes the comparison to state-of-the-art ADCs. 60

Acknowledgement 50
1 2 5 10 20
The authors would like to thank the Chip Implementation Center, Input Frequency(MHz)@10MS/s
0
Taiwan, for supporting the chip implementation and measurements.
Power (dBFS)

Fin = 4.98MHz@10MS/s
SNDR = 60.29dB
References -50
SFDR = 68.92dB

[1] C. C. Liu, S. J. Chang, G. Y. Huang and Y. Z. Lin, “A 0.92mW -100

10-bit 50-MS/s SAR ADC in 0.13μm CMOS process,” IEEE
0 1 2 3 4 5
Symposium on VLSI Circuits, Jun. 2009, pp. 236-237. Frequency (MHz)
[2] J. J. Kang and M. P. Flynn, “A 12b 11MS/s successive Fig. 8: Measured dynamic performance
approximation ADC with two comparators in 0.13μm CMOS,”
IEEE Symposium on VLSI Circuits, Jun. 2009, pp. 240-241. Table I. Comparison to state-of-the-art works
[3] W. Y. Pang, C. S. Wang, Y. K. Chang, N. K. Chou and C. K. Specification (Unit) [1] [2] [3] This work
Wang, "A 10-bit 500-KS/s Low Power SAR ADC with Splitting Technology 0.13μm 0.13μm 0.18μm 0.18μm
Comparator for Bio-Medical Applications," IEEE Asian Supply Voltage (V) 1.2 1 1 1
Solid-State Circuits Conference, pp. 149-152, Nov. 2009. Resolution (bit) 10 12 10 10
[4] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in Sampling rate (MHz) 50 11 0.5 10
65-nm CMOS with split capacitor array DAC,” IEEE J. ENOB (bit) 8.48 10.1 9.4 9.83
Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007. Power (μW) 920 3570 42 98
FOM (fJ/Conv.-Step) 52 311 124 11
Active area (mm2) 0.075 0.7 0.24 0.086

978-1-4244-7641-1/10/$26.00 ©2010 IEEE 2010 Symposium on VLSI Circuits/Technical Digest of Technical Papers 242