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Pipeline Ex.1

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21 views1 page

Pipeline Ex.1

Uploaded by

hadeerrady2003
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Problem No.

6 (14 points)

(a) (6 points) Consider the following sequence of instructions being processed on the pipelined 5-
stage RISC processor discussed in class:

Add R4, R2, R3


Store R2, #100(R6)
Load R5, #200(R4)
Subtract R5, R8, R6

Identify all the data dependencies in the above instruction sequence. For each dependency,
indicate the dependency type (RAW, WAR or WAW), the two instructions and the register that
causes the dependency.

Solution:

1. RAW hazard between Add and Load instructions for register R4


2. WAW hazard between Load and Subtract instructions for register R5

(b) (8 points) Consider a non-pipelined processor using the 5-stage datapath with 2 GHz clock
speed. Assume that due to clock skew and pipeline registers, pipelining the processor lengthens
the clock cycle period by 10%. Also, assume that the processor uses a unified single-ported
cache for data and instruction accesses, resulting in a structural hazard between IF and MEM
stages. Suppose that data references represent 30% of the instructions executed and that the
ideal CPI of the pipelined processor, ignoring the structural hazard is 1. How much speedup can
we gain from pipelining? Assume a balanced pipeline and ignore the pipeline fill and drain
overheads.

Solution:

Speedup from pipelining =


Without pipelining:
Clock period = 1 / 2 GHz = 0.5 ns
CPI = 5

With pipelining:
Clock period is lengthened by 10%. Therefore:
Clock period = 0.5 + (10% * 0.5) = 0.55 ns
30% of instructions access memory during the MEM stage. Each of these instructions results in a
structural hazard with a stall penalty of 1 cycle. Therefore:
CPI = Ideal CPI + Stall CPI = 1 + (0.3)(1) = 1.3

Speedup from pipelining = (0.5 ns * 5) / (0.55 ns * 1.3) = 3.5

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