What is Synthesis?

 Synthesis converts RTL code into optimized gate-level netlist using

technology libraries. It involves translation, optimization (for
performance, power, & area) and technology mapping.
 It is the process of converting a higher level of abstraction (RTL) to
an implementable lower level of abstraction (Netlist).
Goals of synthesis
 The goals of synthesis in VLSI are to:
 Obtain a gate-level netlist
 Improve logic
 Add timer gates
 Add DFT logic
 Preserve RTL and netlist logic equality
 Improve performance, power, & area
 DC INPUTS & OUTPUTS

LIBRARY
TIMING
TF
RTL FLOORPLAN TLU+ BLOCK_SETUP CONSTRAINT
HARD
S
MACROS

DCT/DE

VERIOG
UPF REPORTS
SPEF
 DC Variations
3 different Versions of Design Compile(DC
-DC,DC-topographical and Design Explorer)
Metric DC DCT DE

Floorplan support No Yes Yes

IC model Wire load Tlu+ WLM or tlu+

UPF support Yes Yes No

Dirty RTL Handling No* No* No*

Auto Over constrained Handling No No Yes

Auto Under constrained Handling No No Yes

QOR versus runtime priority QoR QoR Runtime

RDT Flow Syn Syn Syn_de

 Types of synthesis

Logical aware synthesis Physical aware synthesis

 .v  .v
 .lib  .lib
 .sdc  .sdc
 .upf  .upf
 .def
 Logic aware synthesis:
the process of converting a program into a circuit, it’s a critical step in a chip design
translate design into generic design.
Synthesis is the transformation of RTL (Synthesizable Verilog
It entails nets, sequential, and technology-specific gate-level netlist. combinatorial cells and connectivity.

 Physical Aware synthesis:

the process of creating a physical layout of a design from a gate level netlist
Synthesis Requires Additional Floorplan DEF As An Input.
 Inputs for Synthesis
 Tech related:
 .tf : Technology related information.
 .lib : timing information of standard cell & macros.
 Design related:
 .v : RTL code
 .sdc : Timing constraints
 .upf : power intent of the design
 Scan configuration(DFT): scan chain length, scan IO, which flipflops to be considered in scan chain.
 Physical aware:
 .tlu+ : RC coefficient files.
 LEF/FRAM : abstract view of cell.
 .def: location of IO ports and macros.
SYNTHESIS FLOW

 READING DESIGN INTO DC

 TIMING/DESIGN CONSTRAINTS FLOW
 CLOCK GATING FLOW
 SAIF –DYNAMIC POWER OPTIMIZATION THROUGH SAIF
 MULTI –VT THRESHOLD POWER OPTIMIZATION
 DC TOPOGRAPHICAL FLOW
 DC SPG –PHYSCIAL GUIDANCE MODE
 BOTTOM -UP SYNTHESIS FLOW
 UPF FLOW –MULTI POWER DOMAIN DESIGN
 SCAN -INSERTION
 STRATEGIES FOR TIMING/LOGIC OPTIMIZATIONS
 USEFUL REPORT
 AVAILABLE REPORT
 SYNTHESIS SIGN OFF CHECKLIST
SYNTHESIS FLOW
DEVELOP HDL SPECIFY DEFINE DESIGN
Button Button READ
Button
DESIGN Button
FILES LIBRARIES ENVIRONMENT

ANALYZE AND
OPTIMIZE THE SELECT COMIPLE SET DESIGN
RESOLVE
Button
DESIGN Button Button Button
DESIGN STRATEGY CONSTRAINTS
PROBLEMS

SAVE THE DESIGN

Button
DATABASE
 DEVELOP HDL
Button
FILES

Design Compiler can read both RTL designs and gate-

level netlists. Design Compiler uses HDL Compiler to
read Verilog and VHDL RTL designs and Verilog and
VHDL gate-level netlists. You can also read gate-level
netlists in .ddc format.
 SPECIFY
Button
LIBRARIES

 Specify the link, target, symbol, synthetic, and

physical libraries.
 LOAD TECH LIBRARIES INTO DATA BASE
Main steps of Library Objects:
 link_library
 target_library
 symbol_library
 synthetic_library
 READ
Button
DESIGN

 Read, Design, & Elaborate design

 Design Compiler can read both RTL designs and gate-level netlists.
Design Compiler uses HDL Compiler to read Verilog and VHDL RTL
designs and Verilog and VHDL gate-level netlists. You can also read
gate-level netlists in .ddc format.
 DEFINE DESIGN
Button
ENVIRONMENT

 The design environment must be modeled, including operating conditions, such as process, temperature,
and voltage, loads, drives, and fanouts. These models affect synthesis and optimization results. In the case
of a non-topographical mode, specify wire load models to estimate the impact of wire length on
performance.
Parameters :
 Set_operating_conditions
 set_wire_load_model
 Set_drive
 Set_driving_cell
 Set_load
 Set_fanout_load
 Set_min_library
Design rule constraints: Design optimization constraints:
 Set_max_transition  Create_clock
 Set_max_fanout  Set_clock_latency
 Set_max_capacitanc  Set_propagated_clock
e  Set_clock_uncertainty
 Set_clock_transition
 Set_input_delay
 Set_output_delay
 Set_max_area
 Compile & Optimize design
 Use the compile command in DC Expert or compile_ultra in
DC Ultra or DC Graphical to compile a design. Options
customize optimization. Design Compiler reads HDL source
code and optimizes the resulting design. It combines library
cells meeting the design requirements for functionality,
speed, and area using heuristics. It finds a balance between
the constraints imposed by timing and area while producing
the smallest circuit possible with the given timing
requirements.
 Top down
 Bottom up
 Compile or compile_ultra
 Perform logic and gate-level synthesis and optimization on the design
and subdesigns. With each transformation incremental status reports
appear in the console log showing elapsed time area, worst negative
slack total negative slack, and so forth, and all designs, including
endpoint of this.
To control the optimization process, you can
 Set the relative design mapping and area recovery efforts
 Set compile options
 Set design rule options
contd…

 compile_ultra command or the compile command optimizes the design

 Design Compiler performs the following levels of optimization in the
following order:
1. Architectural Optimization
2. Logic-Level Optimization
3. 3. Gate-Level Optimization
 Gate-Level Optimization works on the generic netlist created by logic
synthesis to produce a technology-specific netlist
1. Mapping
2. Delay optimization
3. Design rule fixing
4. Area optimization
contd…

 Optimization works based on compile cost function

 Design Compiler prioritizes costs in the following order:
1. Design rule costs
a. Connection class
b. Multiple port nets
c. Maximum transition time
d. Maximum fanout
e. Maximum capacitance
f. Cell degradation
 2. Optimization costs
a. Maximum delay
b. Minimum delay
c. Maximum power
d. Maximum area
 priority of the maximum design rule costs and the delay costs can be changes
by using the set_cost_priority command
 disable evaluation of the design rule cost function by using the -
no_design_rule
option or the optimization cost function by using the -only_design_rule
 MAPPING
Button
AND
OPTIMIZATION

➤ compile or compile_ultra commands does mapping and optimizations.

➤ Gtech design is mapped to technology specific gates and gets optimized
(PPA).
➤ compile_ultra command features
Automatic ungrouping
Automatic boundary optimization
Automatic datapath extraction and optimization
Register retiming
Topographical technology
 Generate netlist and reports
 Different synthesis results are reported by Design Compiler such as
area, constraint and timing. Report helps in analyzing and debugging
the design issues or enhancement in the synthesis process. A
synthesized design can be validated through check_design command.
Check other commands of the same genre as well.
 HTML Timing Report, categorizing, using create_qor_snapshot and
query_qor_snapshot This report includes critical paths as large fanouts
or transition degradation. You can vary the constraints and produce a
new report for the changed circumstances.
 Check_design
 Report_area
 Report_constraints
 Report_timing
 Use the write_file command to save the synthesized design.
Since Design Compiler does not save the design before it exits
automatically. Save in.ddc,.milkyway, or .Verilog format. You
also have the possibility of saving synthesis attributes and
constraints within a script file-pretty helpful in case you make
later modifications. Refer to "Using Tcl With Synopsys Tools".
Outputs of Synthesis

• Optimized Netlist
• Timing Reports
• QOR Reports
• Area Reports
• UPF (Unified Power Format)