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Analog to Digital Converter

An analog-to-digital converter, also known as ADC, is a digital circuit used to convert
analog signals into digital format.

The conversion of analog signals into digital format is crucial for their processing with the
help of digital systems like microprocessors, microcontrollers, digital signal processors
(DSPs), etc. Therefore, ADCs are important components in several digital systems like
computers and other digital devices.

In this chapter, we will explain in detail the concept, components, types, and applications
of analog to digital converters.

What is an Analog to Digital Converter?

An analog to digital converter is a digital circuit designed to perform conversion of analog
signals into digital data format. It is also known ADC. Analog to digital converters are
essential components in digital systems like computers, data processors, digital
communication systems, etc.

The following figure depicts the block diagram of an analog to digital converter −

From this figure, it is clear that the input to an analog to digital converter is an analog or
natural signal and the output is a digital or discrete time signal.

In practical systems, the analog to digital converter serves as an interface between

external environment and a digital system.

Working of Analog to Digital Converter

The working of an analog to digital converter involves the processes explained below −

Inputting Analog Signal

An analog to digital converter takes an analog signal as input. The analog signal could be
a voltage, current, temperature, pressure, or any other physical quantity that changes

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continuously with time.

Sampling
At this stage, the analog to digital converter samples the input analog signal at regular
intervals of time. These time intervals are defined in terms of sampling rate.

In the sampling process, the analog signal that varies continuously over time is
measured at discrete instants of time to collect discrete values of the signal.

Quantization
Quantization is a process of assigning a digital or discrete value to each sampled value of
the analog signal. In the process of quantization, the range of all possible analog values
is divided into a finite number of discrete digital values.

Encoding
Encoding is a process of converting the quantized digital values into their equivalent
binary numbers. These encoded binary numbers represent the sampled analog values in
the digital format.

The resolution, accuracy, and precision of the analog to digital converter is determined
by the number of bits used for encoding.

Outputting Digital Signal

At the end, the analog to digital converter produces a digital signal as output. This
output digital signal can be processed, stored, or transmitted by digital systems.

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Performance Factors of Analog to Digital Converters

The performance of an analog to digital converter can be evaluated using several
different factors. The following two are the most important −

Signal-to-Noise Ratio (SNR) of ADC

The Signal-to-Noise Ratio (SNR) of an analog to digital converter is defined as the
measure of ability of the converter to differentiate between the desired signal and
unwanted noise signal.

Mathematically, the SNR of an analog to digital converter is expressed as the ratio of the
power of the electrical signal (that represents the useful information) to the power of the

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noise signal (that represents the unwanted disturbances).

In practice, the SNR is expressed in decibels (dB) and the formula for calculating the
SNR of an ADC is given below,

Electrical Signal Power

SNR of ADC = 10 × log( )
Noise Signal Power

From this expression, it is clear that a higher SNR represents better performance of the
analog to digital converter. In other words, an analog to digital converter having a high
SNR distinguishes the electrical signal from the noise signal more clearly. Therefore, it is
desirable that the analog to digital converter have a high SNR so that it can accurately
capture and digitalize smaller analog signals even in the presence of noise signals.

Bandwidth of Analog to Digital Converter

The bandwidth of an analog to digital converter is nothing but the range of frequencies
that it can sample and digitalize accurately. The sampling rate of the analog to digital
converter determines its bandwidth. Where, the sampling rate is defined as the number
of samples of the analog signal taken per second.

According to the Nyquist-Shannon sampling theorem, the maximum sampling rate of an

analog to digital converter should be at least double of the maximum frequency
component present in the input analog signal. It is an important factor to avoid
misidentification of the signal that can introduce distortion or error in sampling.

Let us take an example to understand this, consider an analog to digital converter having
a maximum sampling rate of 150 kHz, then its bandwidth should be limited to
frequencies less than 75 kHz to prevent distortion.

Hence, it is important that the analog to digital converter should have a sufficient
bandwidth to capture the high-frequency analog signals accurately.

Types of Analog-to-Digital Converters

In digital electronics, different types of analog-to-digital converters (ADCs) are designed
to fulfil the requirements of different applications.Some of common types of analog-to-
digital converters include the following −

Flash ADC

Semi-Flash ADC
Successive Approximation Register ADC

Sigma-Delta ADC
Pipelined ADC

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Flash ADC
Flash ADC, also known as Direct ADC, is the fastest ADC available. This type of ADC
has sampling rates of the order of gigahertz. The flash ADCs offer such high speeds
because they use a bank of comparators that can operate in parallel, each for a certain
voltage range.

However, the flash ADCs are relatively larger in size and costlier than other types of
ADCs. Also, they consume relatively more power. In the case of a flash ADC, if "n bits" is
resolution of the ADC, then it requires (2n – 1) comparators in its bank. For example, a
flash ADC having 8-bit resolution requires (28 – 1 = 255) comparators.

The flash analog-to-digital converters are mainly used in digitization of video signals or
fast signals in optical storage.

Semi-Flash ADC
The Semi-Flash ADC is a type of analog-to-digital converter that combines the fast speed
of a flash ADC with a reduced number of comparators. These two features together make
the semi-flash ADC compact in size and cost effective as compared to a flash ADC.

In a semi-flash analog to digital converter, two separate flash converters are used that
operate in parallel. Each converter has a resolution that is half the number of bits of the
whole semi-flash ADC. One converter handles the most significant bits (MSBs) and the
other converter handles the least significant bits (LSBs) of the signal.

After processing, the outputs produced by the two converters are combined to generate
the final digital output of the semi-flash ADC.

The most significant advantage of the semi-flash analog to digital converter is that it
requires a lesser number of comparators than an ordinary flash ADC with maintaining
the high-speed operation. This results in smaller size, reduced complexity and cost.
However, it takes more time to complete the conversion process because it requires
some additional time to combine the partial results of the two separate converters.

The semi-flash analog-to-digital converters are widely used in applications that require a
balance between speed, resolution, and cost.

Successive Approximation Register ADC

The Successive Approximation Register Analog to Digital Converter, abbreviated as SAR
ADC, is a type of analog to digital converter that uses a series of comparisons to
determine each bit of the digital output.

The SAR ADC starts working by initializing its internal approximation registers. Then, it
takes a sample of the input analog signal and stores it steady until the conversion

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process completes.

After that a binary search algorithm is utilized to perform approximation of the input
signal. This process starts by setting the most significant bit (MSB) of the output digital
signal to the highest value and compares this value with the sampled input analog signal.

In the next step, the SAR ADC compares the sampled input analog signal with the output
of an internal digital-to-analog converter that produces a signal proportional to the
current approximation of the input signal.

Depending on results of the comparison, the SAR ADC successively changes the value of
each bit in the digital output until the desired output is obtained. Once all bits of the
digital output have been determined, the SAR converter completes the conversion
process. The digital output obtained represents the digital approximation of the sampled
input analog signal.

The SAR analog-to-digital converters are commonly used in various applications, such as
consumer electronics, medical instruments, data acquisition systems, etc.

Sigma-Delta ADC
The Sigma-Delta Analog-to-Digital Converter, also represented as ΣΔ ADC, is a type of
analog to digital converter that provides a high resolution and is used in applications that
require precise measurement and signal processing like in audio recording, high-quality
audio systems, sensor-based systems, precise instruments, etc.

The working of a sigma-delta ADC involves the following processes −

First, it samples the analog input signal at a frequency significantly higher than the
Nyquist rate to capture more information about the input signal. This process is called
oversampling.

Then, delta modulation is used to convert the oversampled analog signal into a series of
digital pulses. In the process of delta modulation, the difference or delta between
successive samples of the analog input signal is quantized and converted into digital
form.

Now, the sigma-delta modulation is performed, in which a sigma-delta modulator is used

to modulate the difference between the actual analog signal and its digital form. In this
modulation, the quantization noise is pushed away from the desired frequency band and
towards the higher frequencies.

After sigma-delta modulation, the digital signal is passed through a low-pass filter that
removes the high-frequency noise that can be introduced during oversampling and
sigma-delta modulation. This low-pass filter produces a high-resolution digital output by
extracting the low-frequency components.

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At the end of the conversion process, the digital signal is down-sampled (i.e., decimated)
to decrease its sample rate to the desired output rate.

Pipelined ADC
The Pipelined Analog to Digital Converter is a type of ADC which is similar to the SAR
ADC, but it performs a coarse and refined conversion. It provides a balance between
resolution and speed that make it suitable to use in communication systems, medical
test equipment, multimedia, industrial control systems, etc.

A pipelined ADC works in multiple stages, where each stage completes a specific part of
the analog-to-digital conversion. It is called pipelined ADC because all stages take place
in a pipeline manner, in which the output of one stage enters into the next stage.

In the pipelined ADC, the analog input signal is divided into multiple subranges and each
stage of the pipeline performs quantization of a subrange to convert the analog input
signal into digital form. It is important to note that all stages of the pipelined ADC
operate in parallel to provide a faster conversion rate.

The pipelined ADC uses various digital correction techniques such as digital calibration,
error correction algorithms, and digital filtering to remove errors that can be introduced
during the analog-to-digital conversion process. This improves the accuracy and
reliability of the digital output.

This is all about some commonly used types of analog to digital converters (ADCs) in
digital electronics.

Applications of Analog to Digital Converter

Analog-to-digital converters (ADCs) are used in various industries and fields where
analog signals have to be processed, analyzed, or transmitted using digital systems like
computers. Some common applications of analog to digital converters are listed below −

In the field of digital signal processing, ADCs are used for converting analog signals
obtained from sensors, microphones, or other analog devices into digital format for
processing them using digital processors.

In audio processing applications, ADCs are used to convert analog audio signals into
digital format for storage, manipulation, and transmission in digital systems.

ADCs are essential components in various data acquisition systems used in the
field of scientific research, industrial automation, and instrumentation.

In communication systems, ADCs are used to convert analog audio or video signals
into digital format for transmission over communication channels.

ADCs are used in radio receivers for digitization of received radio frequency (RF)
signals.

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ADCs play an important role in several medical equipment and healthcare

systems for converting various analog bio-signals and physiological parameters
like heart rate, blood pressure, oxygen saturation, EEG signals, etc. into digital
format to process them using digital systems.
In automotive electronics, ADCs are used to convert analog signals received
from sensors measuring parameters such as temperature, torque, speed, etc. into
digital format for driver assistance and vehicle diagnostics.

ADCs are also used in a wide range of consumer electronic devices such as
smartphones, tablets, laptops, entertainment equipment, etc.

These are a few examples of the applications of analog-to-digital converters (ADCs) in

various fields and industries.

Conclusion
In this chapter, we explained in detail about analog to digital converters, their types and
applications. In conclusion, an analog to digital converter is an electronic circuit that can
convert an analog input signal into a digital output signal.

ADCs are important components in several devices and systems used across various
industries. This is because, the signals received in real-time like voice signals, signals
from sensors, etc. are analog in nature and they cannot be processed using digital
systems like computers. ADCs help to overcome this interfacing issue. Basically, ADCs
act as an interface between an analog input device and a digital processing element.

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Arithmetic Logic Unit in Digital Electronics

The Arithmetic Logic Unit (ALU) is the fundamental component in a computing
system like a computer. It is basically the actual data processing element within the
central processing unit (CPU) in a computing system. It performs all the arithmetic and
logical operations and forms the backbone of modern computer technology.

In this chapter, we will explain the working of the arithmetic logic unit, along with its
main components, their functions, and the importance of the ALU in the field of digital
system designs.

What is Arithmetic Logic Unit?

Arithmetic Logic Unit abbreviated as ALU is considered as the engine or heart of every
central processing unit (CPU). ALU is basically a combination logic circuit that can
perform arithmetic and logical operation on digital data (data in binary format). It can
also execute instructions given to a computing system like a digital computer.

Within the complex architecture of a digital computing system, the arithmetic logic unit
or ALU plays an important role as it executes and processes all the instructions, performs
calculations, manipulates binary data, and performs various decision-making operations.

The development of arithmetic logic unit begins with the need for efficient, high speed,
and accurate data processing and computation. With the advancement in electronics
technologies, ALU has become a highly sophisticated digital data processing device that
can handle a large number of complex instructions and computational tasks.

Today’s ALU provides high accuracy, precision, and significantly fast processing speed in
computing operations.

Features of Arithmetic Logic Unit

Here are some key features of arithmetic logic unit −

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The ALU can perform all arithmetic and logic operations such as addition,
subtraction, multiplication, division, logical comparisons, etc.
It can also perform bitwise and mathematical operations on binary numbers.

It contains two segments namely, AU (arithmetic unit) and LU (logic unit) to

perform arithmetic operations and logical operations respectively.

It is the computational powerhouse within a central processing unit (CPU).

ALU is the part of every CPU where actual data processing takes place.

ALU is responsible for interpreting the code instructions based on which operations
to be performed on the input data.

Once the data processing is completed, the ALU sends the outcomes to the memory
unit or output unit.

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Main Components of Arithmetic Logic Unit

The arithmetic logic unit consists of various functional parts that are responsible for
performing specific operations like addition, subtraction, multiplication, division,
comparison, and more. Some of the key components of the arithmetic logic unit are
explained below −

Arithmetic Unit
The main components used in the arithmetic unit (AU) segment of the arithmetic logic
unit are as follows −

Adder
The adder or binary adder is one of the important components of the arithmetic logic
unit. It performs the addition of two or more binary numbers. To accomplish this
operation, it performs a series of logical and arithmetic operations. Some common types
of adders used in the arithmetic ogic unit are half-adder, full-adder, parallel adder, and
ripple carry adder. Each type of adder is designed and optimized to perform a specific
computing operation.

Subtractor
The subtractor is another digital combinational circuit designed to perform subtraction of
binary numbers. In most arithmetic logic unit, the subtractor uses 2’s complement
arithmetic to perform subtraction on binary numbers.

Multiplier and Divider

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In more complex and advanced arithmetic logic units, dedicated multiplier and divider
circuits are also implemented to perform multiplication and division on binary numbers.
These circuits use advanced processing techniques like iterative or parallel processing to
accomplish these operations.

Logic Unit
The logic unit (LU) of the ALU comprises the components responsible for performing
Boolean or comparison operations. The following are some main components of the logic
unit of an ALU −

Logic Gates
The logic gates like AND, OR, NOT, NAND, NOR, XOR, and XNOR are the key components
of logic unit. These are standard logic circuits that can manipulate input data based on
some predefined logical instructions and generate a desired output.

Each logic gate can perform a specific logical operation. However, different types of logic
gates can be connected together in a specific manner to perform complex logical
operations.

Type of Logic Gate

The brief overview of each type of logic gate is explained here −

AND Gate − It performs the Boolean multiplication on input binary data. Its output
is logic 1 or true, only when all its inputs are logic 1 or true.
OR Gate − The OR gate performs the Boolean addition of input binary data. It
generates a logic 1 or true output, if any of its inputs is logic 1 or true.

NOR Gate − The NOT gate performs the inversion operation. It gives a logic 1 or
true output when its input is logic 0 or false and vice-versa.
NAND Gate − The NAND gate performs the NOTed AND operation and produces a
logic 1 or true output when both inputs or any of the inputs is logic 0 or false.
NOR Gate − The NOR gate performs the NOTed OR operation and generates a logic
1 or true output when all its inputs are logic 0 or false.
XOR Gate − The XOR gate performs the exclusive OR operation and produces a
logic 1 or true output when its both inputs are dissimilar. Hence, it is used as
inequality detector.

XNOR Gate − The XNOR gate performs the exclusive NOR operation and gives a
logic 1 or true output when both its inputs are similar. Thus, it is used as an
equality detector.

This is all about structure and components of the arithmetic logic unit. Let us now
understand what functions an ALU can perform.

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Functions of Arithmetic Logic Unit

The arithmetic logic unit can perform a wide range of functions and operations in digital
computing systems. Some important functions that an arithmetic logic unit perform are
explained below −

Arithmetic Operations
The arithmetic operations are one of the primary functions that the arithmetic logic unit
performs. This category of operations includes addition, subtraction, multiplication, and
division of binary numbers. All these operations form the basis of mathematical
computations that the arithmetic logic unit can perform.

Logical Operations
The arithmetic logic unit can also perform various logical operations such as AND
operation, OR operation, NOT operation, etc. These logical operations form the basis of
decision making and data manipulation processes.

Comparison Operations
The arithmetic logic unit also facilitates to perform various comparison operations such
as equal to, not equal to, less than, greater than, etc. These comparison operations are
essential in decision making processes.

Shift Operations
The arithmetic logic unit can also perform shift operations on binary numbers such as left
shift and right shift. These operations are important in multiplication and division
operations. The shift operations can manipulate binary data at bit level and hence
optimize the arithmetic calculations.

Working of Arithmetic Logic Unit

The working of the arithmetic logic unit depends on a combination of input data and
control signals. In other words, the arithmetic logic unit receives the input data and
control signals and then interpret these data and signals to perform specific operations.

Let us understand the working of the arithmetic logic unit in detail by breaking it down in
sub-components.

Receiving Input Data and Control Signals

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The arithmetic logic unit receives the input data from the user and a set of control
signals that specifies the operation to be performed. The data is received through the
input data path while the control signals are received from the control unit.

Execution of Operation
Once the arithmetic logic unit received the input data and control signals, it selects an
appropriate functional component among arithmetic unit, logic unit, comparison unit, or
shift unit to perform the specific operation. Once the operation completes, the ALU sends
the results to the memory unit for storage or output unit.

Significance of Arithmetic Logic Unit

In the field of digital electronics and computing technology, the arithmetic logic unit plays
an important role because of the following reasons −

It can perform the arithmetic, logical, and comparison operations with very high
accuracy, precision, and efficiency.

It can also perform complex data processing and decision-making operations.

ALU can execute complex processing tasks at a very high speed that results in
better performance and higher efficiency.
ALU introduces versatility as it can execute a wide range of computational tasks.

Conclusion
This is all about arithmetic logic unit (ALU) which is an important combinational logic
circuit in digital electronics and modern computing systems. It acts as the heart of
central processing unit (CPU) and executes all kinds of operations including arithmetic,
logical, and comparison operations. In a digital computing system, the arithmetic logic
unit acts as a primary functional unit that processes the input data based on the
instructions. In this chapter, we have studied all the important concepts related to the
arithmetic logic unit.

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Binary Registers in Digital Electronics

In digital electronic devices and systems, binary registers are one of the crucial
components that play a vital role in data storage and manipulation. Binary registers are
the fundamental building blocks in memory unit of a digital system or device.

Here, we will explore basics of binary registers and binary register data. So, let’s
start with the basic introduction of binary registers.

What are Binary Registers?

In digital systems, a binary register is considered the base of a data storage unit. It is
a group of flip-flops connected together to store data and information in the form of 0s
and 1s. The storage capacity of a binary register depends upon the number of flip-flop
combined in the circuit. For example, a 4-bit binary register consists of a group of four
flip-flops connected together, and is capable of storing 4-bit information.

Types of Binary Registers

Depending on the input and output configurations and data manipulation, binary
registers are classified into the following four types −

Serial-In Serial-Out (SISO) Binary Register

The block diagram of a 4-bit serial-in serial-out (SISO) binary register is depicted in the
following figure −

Here, the output of the first flip-flop is connected to the next flip-flop. The binary input
data will enter the register through the input line Din. This entry will take place in a
serial manner, i.e. first, the LSB bit will enter the register, then the following bits.

Serial-In Parallel-Out (SIPO) Binary Register

The block diagram of a 4-bit serial-in parallel-out (SIPO) binary register is depicted in
the following figure.

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Here, the data is entered into the register serially, and the output is taken in parallel
form. In this type of binary register, while input data is being loaded, the output lines
remain disabled. Once the process of data loading is completed, the output lines will
become active to provide the output in parallel form.

Parallel-In Serial-Out (PISO) Binary Register

The block diagram of a 4-bit parallel-in serial-out (PISO) binary register is depicted in
the following figure −

This type of the binary register accepts data in parallel form and produces results
serially. Therefore, in PISO binary register, all bits of the input data are loaded into the
register at the same time. This register can operate in two modes namely, load mode
and shift mode.

In the load mode, the input circuit becomes active to load the input data bits into the
respective flip-flops of the register. In the shift mode, data bits are shifted from left to
right. This results in a parallel-in serial-out operation.

Parallel-In Parallel-Out (PIPO) Binary Register

The block diagram of a 4-bit parallel-in parallel-out binary register is shown in the
following figure.

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This type of binary register receives data in parallel form and produces output in parallel
form. Hence, in PIPO binary register, the input data bits are loaded into the respective
flip-flops at the same time and the output bits will also appear at the same time.

After getting an overview of binary register and their types, let us now understand the
concept of binary register data.

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What is Binary Register Data?

Binary register data is nothing but the data and information stored and represented in
binary form within a binary register.

In a digital system, the information is represented in the binary form, i.e. by using a
string of 0s and 1s. The binary register can store these binary information in a series of
flip-flops.

The sequence of input and output of the binary register data depends on the
configuration of input and output lines. The amount of binary register data stored in a
binary register depends on the storage capacity and number of flip-flops in the register.
For example, a 16-bit binary register can store 16 binary digits of binary information.

In a binary register, the stored binary register data can be manipulating through various
operations like writing, retrieving, etc. Binary registers and binary register data play an
important role in any digital electronic system, such as memory devices, processors,
data centers, communication systems, and more.

In digital systems like computers, calculators, etc., the binary register data are used to
perform various arithmetic and logical operations.

Significance of Binary Register Data

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Binary register data plays an important role in the functioning of a digit electronic
system. It serves as a fundamental unit for data representation in any digital system. It
makes the arithmetic and logical operations straightforward. Binary register data
provides faster data manipulation which increases the data processing speed of a device.

Overall, binary register and binary register data are fundamental components of a digital
system for performing operations like data storage, manipulation, retrieval, etc.

Conclusion
Binary registers provide faster and efficient storage and retrieval of binary data, making
them a better choice for digital devices. Binary register data plays an important role in
data storage and manipulation in digital systems. The binary register data are also used
in data conversion interfaces to transform analog data into digital form. They also allow
for reliable and efficient transfer of binary information between digital devices and
communication networks.

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Cache Memory Design

Cache memory is a very high-speed semiconductor memory which can speed up the
CPU. It acts as a buffer between the CPU and main memory. It is used to hold those
parts of data and program which are most frequently used by CPU. The parts of data and
programs are transferred from the disk to the cache memory by the operating system,
from where the CPU can access them.

In this chapter, we will explain in detail about cache memory along with its advantages
and disadvantages.

What is Cache Memory?

In digital systems like computers, the cache memory is a high-speed volatile
semiconductor memory used to store data and instructions frequently accessed by the
central processing unit of the system.

The cache memory acts as a buffer between the processing element and main/primary
memory, more specifically RAM (Random Access Memory). It is mainly used to provide a
faster access to the recent and most frequently used data and programs.

The cache memory is employed for improving the performance and efficiency of the
digital systems, as it reduces the time required for accessing the data.

Cache Memory Design

In this section of the article, we will discuss different concepts involved in the design of
cache memory −

Purpose of the Cache Memory

The main purpose of the cache memory is to store frequently used data and instructions.
This helps in reducing the access time.

Size of the Cache Memory

It is found that small size cache memory results in better performance improvement of
the system.

Cache Memory Hierarchy

Cache memory is generally organized in multiple hierarchy levels, where each level is
called a cache level or cache layer. A computer system typically has multiple cache
levels, most common of them are L1 (Level 1 Cache), L2 (Level 2 Cache), and L3 (Level

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3 Cache). Here, the cache memory L1 is the smallest, fastest and closest to the CPU of
the system, while the L2 and L3 cache memories are larger and slower than L1 cache.

Structure of Cache Memory

Cache memory is typically divided into blocks of a fixed size. Each block has a specific
data storage capacity. The structure of the cache memory is formed by grouping all
these blocks together into cache sets.

Mapping Techniques for Cache Memory

The mapping techniques are used to determine how the memory blocks are mapped to
cache blocks. The following three types of cache mapping techniques are commonly used
−

Direct Mapping − Direct mapping is a simple cache mapping technique in which

each memory block is mapped into a certain cache block. Although, this technique
can lead to a high rate of conflicts.

Fully Associative Mapping − In this mapping technique, each memory block can
be placed in any cache block, hence this technique has high flexibility. However, it
requires addition hardware.
Set Associative Mapping − This mapping technique is a combination of direct and
fully associative mappings. In this technique, the cache memory is divided into
cache sets, and each memory block can be placed in any cache block within its
corresponding cache set.

Cache Replacement Algorithms

When a memory block is required to be accessed into a cache block that is already
occupied, then a cache replacement algorithm is needed to determine which memory
block should be replaced to free up space in the cache memory for the new memory
block.

The following three are the common cache replacement algorithms −

First-In First-Out (FIFO) Algorithm − This algorithm replaces the memory block
that exists in the cache memory the longest.

Least Recently Used (LRU) Algorithm − This algorithm replaces the memory
block that has been fetched least recently.

Random Replacement (RR) Algorithm − This algorithm replaces any memory

block randomly.

Performance of Cache Memory

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The performance of the cache memory is generally measured in terms of its hit rate. The
hit rate specifies the percentage of memory accesses that result in cache memory hits. A
high hit rate indicates that a significant portion of the memory accesses is satisfied from
the cache memory. This provides enhanced system performance.

All these are the fundamental concepts of cache memory design. Now, let’s have look
into the advantages and disadvantages of cache memory design.

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Types of Cache Memory

Cache memory is classified on the basis of "levels". Where, each level describes its
accessibility and closeness to the processing element of the digital system.

The classification of cache memory is done in the following three levels −

L1 (Level 1) Cache Memory

It is also known as primary cache memory. The L1 cache memory is the fastest one. But
it is very small in size and mainly used in the processor chip in the form of CPU cache.

L2 (Level 2) Cache Memory

It is also called secondary cache memory. It has more capacity as compared to the L1
cache memory. It can be used in the processor chip as CPU cache or it can be a separate
chip.

L3 (Level 3) Cache Memory

This one is a specialized cache memory designed to enhance the performance of L1 and
L2 cache memories. However, the L3 cache memory is significantly slower than L1 or L2
cache memories.

Features of Cache Memory

The key features of cache memory are listed below −

Cache memory is faster than main memory.

It consumes less access time as compared to main memory.

It stores the program that can be executed within a short period of time.

It stores data for temporary use.

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Advantages of Cache Memory

In digital systems, the cache memory provides several advantages, as it improves the
overall performance and efficiency of the system. Some of the key benefits of the cache
memory are highlighted below −

Cache memory provides a faster data access speed and reduces the total access
time. This characteristic of the cache memory helps to speed up the execution of
tasks.
Cache memory helps to reduce the memory latency by storing recent and most
frequently used data and instructions. Also, it minimizes the dependency on slower
primary memory or RAM. This feature also results in improved system performance
and efficiency.
Cache memory operates at the same speed as the CPU. Hence, it can provide a
steady stream of input data and instructions that reduces the idle time of the CPU.
Therefore, it also improves the CPU utilization.

Cache memory bridges the gap between the high-speed, expensive cache memory
and the slow-speed, cheap main memory. It provides a balance between speed,
capacity, and cost.

Disadvantages of Cache Memory

However, the cache memory offers several advantages. But it also has some
disadvantages which are listed below −

Cache memory has a very smaller storage capacity. Thus, it cannot be used to hold
all the data and instructions required by the processing unit.
Cache memory is expensive to the design and manufacture. It also increases the
overall complexity of architecture of the digital system.
Sometimes, the cache pollution may occur when irrelevant data stored in the cache
memory and there is no enough space for useful data. This significantly degrades
system performance.

Conclusion
In conclusion, the cache memory is a high-speed semiconductor memory primarily used
in digital systems to improve their performance and efficiency. The use of cache memory
reduces the data access time and speeds up the task execution. However, being a quite
expensive memory, it can increase the overall cost of the system.

In this chapter, we covered all the important concepts related to cache memory such as
its purpose, features, advantages, and disadvantages.

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Conversion of JK Flip-Flop to T Flip-Flop

What is a JK Flip-Flop?
JK flip flop is also a 1-bit storage device having two inputs similar to SR flip flop, but it
has inputs denoted by J and K instead of S and R. It has two outputs viz. Q (normal
output) and Q' (inverted output). The clock signal is used for synchronization of the
circuit.

The block diagram of the JK flip flop is shown in Figure-1 below.

The operation of the JK flip flop can be understood with the help of its truth table which
is given below −

Inputs Output

J K Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 Toggle

The characteristic equation of the JK flip flop is given by,

′
′
Q n+1 = JQ n + K Q n

What is a T Flip-Flop?
T flip-flop, also called toggle flip flop, is a type of digital flip flop which has a single
input specified by the letter T. It has two outputs namely Q and Q', where Q is the
normal output and Q' is the complemented output.

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The block diagram of T flip flop is shown in Figure-2.

The truth table of the T flip flop is depicted below.

Present State of Output Next State of Output

Input (T)
(Qn) (Qn+1)

0 0 0

0 1 1

1 0 1

1 1 0

From the truth table of the T flip flop, it is clear that when the input T is equal to 0, there
is no change in the output of the flip flop. When T is equal to 1, the output of the T flip
flop toggles.

The characteristics equation of the T flip flop is given by,

′
′
Q n+1 = T Q n + TQ n

After discussing the basics of JK flip flop and T flip flop, let us now discuss the conversion
of JK flip flop into T flip flop.

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Conversion of Flip-Flop
We can convert a one type of flip-flop into another type of flip-flop. The conversion
process of flip-flops involves the following steps −

Step 1 − Write the excitation table of the flip flops.

Step 2 − Simplify the excitation table with the help of Karnaugh Map (K-map).

Step 3 − Draw the required logic circuit diagram.

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Now, let us convert the JK flip-flop into the T flip-flop.

Conversion of JK Flip-Flop into T Flip-Flop

The conversion of JK flip-flop into T flip-flop is done as per the following steps −

Step 1 − The excitation table for the conversion of JK flip flop to T flip flop is given
below.

Input Present State of Output Next State of Output Flip Flop Inputs

T Qn Qn+1 J K J K

0 0
0 0 0 0 X
0 1

0 0
0 1 1 X 0
1 0

1 0
1 0 1 1 X
1 1

0 1
1 1 0 X 1
1 1

Step 2 − The excitation table is simplified by using K-Map technique to obtain the
expression of inputs as follows −

The K-map simplification for the input J is,

J=T

The K-map simplification for the input K is,

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K=T

Step 3 − The logic diagram of the T flip-flop using JK flip flop is shown in Figure-3
below.

In this way, we can convert JK flip flop into T flip flop.

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Conversion of SR Flip-Flop to JK Flip-Flop

What is SR Flip-Flop?
SR flip-flop is a simple 1-bit storage element which has two inputs namely S and R, and
two outputs, i.e. Q and Q'. Where, S specifies Set input and R specifies Reset input. The
output Q is the normal output and the Q' is the complemented or inverted output. In
addition to SR inputs, the SR flip flop also has a clock input which is used for triggering
the circuit.

The block diagram of SR flip flop is shown in Figure-1 below.

The operation of the SR flip flop can be analyzed using its truth table, which is given
below.

Inputs Output

S R Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 Forbidden

Here, Qn+1 is the next state, and Qn is the present state of the output.

The characteristic equation of the SR flip flop is given by,

′
Q n+1 = S + R Qn

What is JK Flip-Flop?

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JK flip flop is also a 1-bit storage device having two inputs similar to SR flip flop, but it
has inputs denoted by J and K instead of S and R. It has two outputs viz. Q (normal
output) and Q' (inverted output). The clock signal is used for synchronization of the
circuit.

The block diagram of the JK flip flop is shown in Figure-2 below.

The operation of the JK flip flop can be understood with the help of its truth table which
is given below −

Inputs Output

J K Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 Toggle

The characteristic equation of the JK flip flop is given by,

′ ′
Q n+1 = JQ n + K Q n

After discussing about the basics of SR flip flop and JK flip flop. Let us now discuss the
conversion of SR flip flop into JK flip flop.

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Conversion of Flip-Flop
We can convert a one type of flip-flop into another type of flip-flop. The conversion
process of flip-flops involves the following steps −

Step 1 − Write the excitation table of the flip flops.

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Step 2 − Simplify the excitation table with the help of Karnaugh Map (K-map).

Step 3 − Draw the required logic circuit diagram.

Now, let us convert the SR flip-flop into the JK flip-flop.

Conversion of SR Flip-Flop into JK Flip-Flop

As per the steps of conversion of flip-flops, the conversion process of SR flip-flop into JK
flip-flop is described below.

Step 1 − The excitation table for the conversion of SR flip-flop into JK flip-flop is given
below −

Inputs Present State of Output Next State of Output Flip-Flop Inputs

J K Qn Qn+1 S R S R

0 0
0 0 0 0 0 X
0 1

0 0
0 0 1 1 X 0
1 0

0 0
0 1 0 0 0 X
0 1

0 1 1 0 0 1 0 1

1 0 0 1 1 0 1 0

0 0
1 0 1 1 X 0
1 0

1 1 0 1 1 0 1 0

1 1 1 0 0 1 0 1

Step 2 − Simplify the excitation for input expressions by using K-Map −

The K-Map simplification for S is,

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S = JQn'

The K-map simplification for R is,

R = KQn

Step 3 − Finally, draw the logic diagram of JK flip flop by using SR flip flop, which is
shown in figure-3 below.

In this way, we can convert the SR flip-flop into JK flip-flop.

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Design Full Adder Using Half Adder

In data processing, addition of operands is one of the most basic operations performed
by different electronic devices like computers, calculators, etc. The electronic circuit that
is designed to perform the addition of two or more numbers, more specifically binary
numbers, is known as adder. As we know, the logic circuits use binary number system
to perform the operations, hence the adder is also referred to as a binary adder.

Types of Adders
Depending on the number of binary digits that the adder circuit can add, adders (or
binary adders) are of two types −

Half Adder

Full Adder

Here, we will discuss the implementation of full adder using half adder. But before that
let’s have a look into the basics of half adder and full adder.

What is a Half Adder?

Half adder is a combinational logic circuit that is designed to add two binary digits. The
half adder provides the output along with a carry (if any). The half adder circuit can be
designed by connecting an XOR gate and one AND gate. It has two input terminals and
two output terminals for sum (S) and carry (C). The block diagram and circuit diagram of
a half adder are shown in Figure-1.

In the half adder, the output of the XOR gate is the sum of two bits and the output of the
AND gate is the carry bit. However, in the half-adder circuit, the carry obtained in one
addition will not be forwarded in the next addition.

The output equation of the half adder are,

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Sum, S = A ⊕ B

Carry, C = A ⋅ B

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What is a Full Adder?

Full adder is also a combinational logic circuit that can add two binary digits (bits) and a
carry bit, and produces a sum bit and a carry bit as output.

In other words, a combinational circuit which is designed to add three binary digits and
produces two outputs (sum and carry) is known as a full adder. Thus, a full adder circuit
adds three binary digits, where two are the inputs and one is the carry forwarded from
the previous addition. The block diagram and circuit diagram of the full adder are shown
in Figure-2.

It is clear that the logic circuit of a full adder consists of one XOR gate, three AND gates
and one OR gate, which are connected together as shown in Figure-2. Here, A and B are
the input bits, Cin is the carry from previous addition, S is the sum bit, and Cout is the
output carry bit.

The output equations of the full adder are,

Sum, S = A ⊕ B ⊕ C in

Carry, C out = Ab + AC in + BC in

Now, let us discuss the realization of the full adder using half adders

Implementation of Full Adder using Half Adder

The logic diagram of the full adder using two half adders is shown in Figure-3 −

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The block diagram of a full adder using two half adders is shown in Figure-4.

From the logic diagram of the full adder using half adders, it is clear that we require two
XOR gates, two AND gates and one OR gate for the implementation of a full adder circuit
using half-adders.

However, the implementation of full adder using half adder has a major disadvantage
that is the increased propagation delay. That means, the input bits must propagate
through several gates in succession that increases the total propagation delay of the full
adder circuit.

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Design of Synchronous Counter in Digital

Electronics
In digital electronics, a set of flip-flops that changes its states in response to pulses
applied at the input is called a digital counter. In the digital counter circuit, the flip
flops are connected in such a way that their combined state at any time is the binary
equivalent of the total number of pulses that have occurred up to that time. Therefore,
as its name implies, a counter is used to count pulses in a digital system.

Digital counters are classified into the following two types namely,

Asynchronous Counter − The type of counter in which the flip flops are
connected in such a way that they are not triggered simultaneously is known as
asynchronous counter. Asynchronous counter is also known as ripple counter.

Synchronous Counter − The type of counter in which all the flip flops are
clocked simultaneously is known as a synchronous counter.

After getting insights into the basics of counter, now let us discuss the design of
synchronous counter.

Design of Synchronous Counter

A synchronous counter is a type of counter in which all the flip flops are triggered
simultaneously by the same clock pulse. The systematic procedure of designing a
synchronous counter is explained below.

Step 1: Determine The Number of Flip-Flops Required

Firstly, analyze the problem description and determine the number of flip-flops required
to implement the synchronous counter. If n is the required number of flip flops, then the
smallest value of n is such that the number of states N is less than or equal to 2n.

Step 2: Draw The State Diagram

Secondly, draw the state diagram that shows all the possible states. The state diagram is
basically a graphical way of representing the sequence of states through which the
counter progresses. In the state diagram, we can also include the case in which the
counter goes to a particular state from the invalid states on the next clock pulse.

Step 3: Selection of Flip-Flops And Excitation Table

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In the third step, select a particular type of flip flop to be used to implement the counter
and draw its excitation table. The excitation table is one that gives the information about
the present states, next states, and required excitations of the flip flop.

Step 4: Obtain The Minimized Expression for Excitations

Now, obtain the minimal expressions for the excitations of the flip flops by using any
minimization technique such as K-maps.

Step 5: Draw The Logic Diagram

Finally, draw the logic circuit diagram according to the minimal expression obtained in
the step 4.

In this way, we can design a synchronous counter

Synchronous counter may suffer from the problem of lock-out, which means they may
not be self-starting. A self-starting counter is a type of synchronous counter that will
enter to its proper sequence of states regardless of its initial state. We can make a
counter self-starting by designing it so that it enters to a particular state whenever it
goes to an invalid state.

Now, let us take an example to understand the procedure of designing a synchronous

counter.

Example
Design a synchronous counter using D flip flops that goes through states 0, 1, 2, 4, 0.
The unused states must always go to zero on the next clock pulse.

Solution
This synchronous counter is designed as per the following steps −

Step 1 − Number of flip flops required −

This synchronous counter has four stable states, i.e. 0 (000), 1 (001), 2 (010), 4 (100).
But we require three flip flops because it counts 4 (100) as well. Since three flip-flops
can count eight states. Thus, the remaining four states, i.e. 3 (011), 5 (101), 6 (110),
and 7 (111) are unused states. As per the problem statement, the unused states must
go to 0 (000) after the next clock pulse. Therefore, there are no don’t care states.

Step 2 − Draw the state diagram −

The state diagram of the 0, 1, 2, 4, 0, … counter is drawn as shown in the following

figure.

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Step 3 − Chose the type of flip flop and write the excitation table −

The D flip flop is to be used and the excitation table of the counter using D flip flop is
written below.

Present State Next State Required Excitation

Q3 Q2 Q1 Q3 Q2 Q1 D3 D2 D1

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 0

0 1 0 1 0 0 1 0 0

0 1 1 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0

1 1 1 0 0 0 0 0 0

Step 4 − Derive the minimal expression −

From the excitation table, we can see that there is no minimization is possible. Hence,
the expressions for the excitations can be directly written from the excitation table itself
as follows −
′ ′ ′

D1 = Q Q Q
3 2 1

′ ′ ′

D2 = Q Q Q
3 2 1

′ ′ ′

D3 = Q Q Q
3 2 1

Step 5 − Draw the logic circuit diagram −

The logic circuit diagram of the counter 0, 1, 2, 4, 0,… as per the expressions is shown in
the figure below.

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This is all about how you can design a synchronous counter.

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Difference between Half Adder and Full Adder

An adder circuit is one of the important digital circuits used in computers, calculators,
digital processing units, etc. There are two types adder circuits named half-adder and
full-adder. Both the half adder and the full adder circuits are used to perform addition
and also widely used for performing various arithmetic functions in the digital circuits.

What is a Half Adder?

A combinational logic circuit which is designed to add two binary digits is known as half
adder. The half adder provides the output along with a carry value (if any). The half
adder circuit is designed by connecting an EX-OR gate and one AND gate. It has two
input terminals and two output terminals for sum and carry.

In case of half adder, the output of the EX-OR gate is the sum of two bits while the
output of the AND gate is the carry. However, the carry obtained is one addition will not
be forwarded in the next addition, so it is called half adder.

The output equations of the half adder are −

Sum, S = A ⊕ B

Carry, C = A ⋅ B

What is a Full Adder?

A combinational circuit which is designed to add three binary digits and produce two
outputs is known as full adder. The full adder circuit adds three binary digits, where two
are the inputs and one is the carry forwarded from the previous addition.

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The circuit of the full adder consists of two EX-OR gates, two AND gates and one OR
gate, which are connected together as shown in the full adder circuit.

The output equations of the full adder are −

Sum, S = A ⊕ B ⊕ C in

Carry, C = AB + BC in + AC in

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Difference Between Half Adder and Full Adder

The following table shows the main differences between half adder and full adder circuit.

Parameter Half Adder Full Adder

Half adder is a Full adder is a combinational digital circuit

combinational digital which can add three single-bit binary
Definition circuit which can add number, where two are the inputs and the
two 1-bit binary third is the carry forwarded from the
numbers. previous output.

The circuit of the half

Circuit adder consists of one The circuit of full adder consists of two EX-
components EX-OR gate and one OR gates, two AND gates and one OR gate.
AND gate.

The half adder does

not add the carry In case of full adder, the carry produced in
Addition of
generated in the the previous addition is added in the next
carry bit
previous addition to addition.
the next addition.

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Half adder circuit has

Number of
two input terminals Full adder circuit has three input terminals
input and
viz. A and B and two viz. A, B and Cin and two output terminals,
output
output terminals, viz. i.e., Sum and Carry.
terminals
Sum and Carry.

For half adder circuit,

For full adder circuit, the logical expressions
the logical expressions
Logical of the outputs are −
of the outputs are −
Expressions S = A ⊕ B ⊕ C in
S = A ⊕ B
C = AB + BC in + AC in
C = A ⋅ B

A half adder circuit

A full adder circuit can substitute a half
Substitution cannot be used as a
adder circuit.
full adder circuit.

The circuit of a half

The circuit of a full adder has relatively
Design adder is simple and
complex design.
easy to implement.

Alternate For half adder, there is

Full adder is also called ripple-carry adder.
Name no alternate name.

Half adder circuits are

used in computers,
calculators, and Full adders are mainly used for multiple bit
Applications
various digital addition, in digital processing devices, etc.
measuring
instruments.

Conclusion
From the above discussion, it is clear that there are several differences between a half-
adder circuit and a full-adder circuit. However, both half adder and full adder circuits
are the basic building blocks of many digital circuits that are used to perform arithmetic
operations such as calculators, computers, digital measuring devices, digital processors,
etc.

One of the main advantage of using half adders and full adders in the digital circuits is
that they are designed by using logic gates that process the input data very fast. The
typical processing speed of the logic gates is of the order of μs (microseconds). Hence,
for performing arithmetic operations at high speed, we use half adder and full adder
circuits.

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Difference between Multiplexer and

Demultiplexer
Both Multiplexer and Demultiplexer are types of combinational digital circuits widely
used in many large-scale digital systems. The major difference between the multiplexer
and demultiplexer is in their ability to accept multiple input signals and single input
signal respectively.

We will explain some other noticeable differences between multiplexer and demultiplexer,
but before that have a look on the basic description of multiplexer and demultiplexer
which is given in this article.

What is Multiplexer?
A digital logic circuit which is capable of accepting several inputs and generating a single
output is known as multiplexer or MUX. Thus, the multiplexer is a type of data
selector which takes many inputs and gives a selected output. In a multiplexer, there
are 2n input lines and 1 output line, where n is the number of select lines.

Therefore, a multiplexer is a combinational circuit which is designed to switch one of the

many input lines to a single output line by the use of a control signal. For this reason,
the multiplexer is also referred to as a many to one circuit. The block diagram of a
multiplexer is shown in Figure-1.

The multiplexer functions as a multi-position switch which is digitally controlled by a

control signal. In case of the multiplexer, the select lines determine that which input
signal will get switched to the output line among the many input signals.

What is Demultiplexer?
A digital combinational circuit which takes one input signal and generates multiple output
signals is known as demultiplexer or DEMUX. As it distributes a single input signal over
many output lines, hence it is also referred to as a type of data distributor.

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In a demultiplexer, there is only 1 input line and 2n output lines. Where, n denotes the
number of select lines. Therefore, it can be noted that a demultiplexer reverses the
operation of a multiplexer. The block diagram of a demultiplexer is shown in Figure-2.

Demultiplexers are used in applications where there is a necessity of connecting single

source to several destinations, such as in arithmetical and logic unit, in communication
system for data transmission, in wavelength routers, etc.

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Difference between Multiplexer and Demultiplexer

Both multiplexer and demultiplexer are types of combinational digital circuit that are
used in several large-scale digital systems. However, there are many differences between
a multiplexer and a demultiplexer, which are highlighted in the following table −

Difference Multiplexer Demultiplexer

A multiplexer is a combinational A demultiplexer is a

digital circuit that takes multiple combinational digital circuit that
Definition
data inputs and provides only takes single input and provides
single output. multiple outputs.

The abbreviation used to

Abbreviated The abbreviation used to
represent the demultiplexer is
name represent the multiplexer is MUX.
DEMUX.

Multiplexer has 2n input lines Demultiplexer has 1 input line

Input and
and 1 output line. Where, n is the and 2n output lines. Where, n is
output lines
number of select lines. the number of select lines.

Multiplexer is also known as a Demultiplexer is also known as

Also known as
"data selector". "data distributor".

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Operating The operating principle of the The operating principle of a

principle multiplexer is "many to one". demultiplexer is "ne to many".

Multiplexer acts as a digital Demultiplexer acts as a digital

Acts as
multi-position switch. circuit.

Conversion A multiplexer performs parallel to A demultiplexer performs serial

technique serial conversion. to parallel conversion.

In case of multiplexer, the In demultiplexer, the function of

Function of function of control signal is to control signal is to deliver the
control signal select a specific input that has to single input signal over the
be transmitted at the output. multiple output lines.

Some common demultiplexers

Examples of some common are −
multiplexers are −

1:2 Demultiplexer
Examples 8:1 Multiplexer
1:4 Demultiplexer
16:1 Multiplexer
1:8 Demultiplexer
32:1 Multiplexer
1:16 Demultiplexer

In practice, the multiplexer

In practice, the demultiplexer
increases the efficiency of the
Practical takes the output of a multiplexer
communication system by
importance and convert in its original form at
enabling the data transmission
the receiver end.
using a single line.

Usage in time- A multiplexer is used at the The demultiplexer is used at the

division transmitter end in the time- receiver end in the time-division
multiplexing division multiplexing (TDM). multiplexing.

The multiplexers are commonly The demultiplexers are used in

used in communication systems, communication systems,
Applications
telephone networks, computer reconstruction of parallel data,
memories, etc. ALU, etc.

Conclusion
Both multiplexers and demultiplexers are required in the communication system
because of its bidirectional nature. These two devices perform the exact opposite
operations of each other. A major difference between multiplexer and demultiplexer is

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based on their input and output lines, i.e., a multiplexer has many input lines and one
output line, whereas a demultiplexer has one input line and many output lines.

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Difference Between Synchronous and

Asynchronous Counter
In digital electronics, a counter is a sequential logic circuit that consists of a series of
flip-flops. As the name suggests, counters are used to count the number of occurrences
of an input in terms of negative or positive edge transitions.

Based on the way the flip-flops are triggered, counters can be grouped into two
categories: Synchronous counters and Asynchronous counters.

Here we will discuss how these two types of counters function and how they are different
from each other.

What is a Synchronous Counter?

If the clock pulses are applied to all the flip-flops in a counter simultaneously, then such
a counter is called as synchronous counter.

In a synchronous counter, all the constituting flip-flops are clocked with the same
clock input simultaneously. These are also known as parallel counters.

Basically, all the flip-flops in a synchronous counter are arranged in a cascade

connection and each flip-flop is individually connected to an external clock. It allows
the clocking of all the flip-flops at the same time instant with the same clock input.
It means the output of each flip-flop varies in synchronization with the clock input.

Due to this, the common clock signal causes the change in the state of each
individual flip-flop simultaneously. Resultantly it leads to no ripple effect, thus there
is no propagation delay in a synchronous counter.
Logic gates are used in synchronous counters to control the count sequence.

What is an Asynchronous Counter?

Asynchronous counters are also known as serial counters because the flip-flops that
constitute the counter are connected serially and the input clock pulse is provided to the
first flip-flop in the connection.

The output of the first flip-flop acts as the input of the next adjacent flip-flop in the
forward direction. In this manner, the clock input ripples through the counter.
Hence, these counters are also known as ripple counters.

Due to the ripple effect, the timing signal in an asynchronous counter gets delayed
by some amount on passing through each flip flop. Hence, it results in a
propagation delay.

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Difference Between Synchronous and Asynchronous Counters

The following table highlights the major differences between Synchronous and
Asynchronous Counters.

Key Synchronous Counter Asynchronous Counter

In case of Synchronous Counters, In case of Asynchronous

all the constituent flip-flops are Counters, there is triggering of
Trigger
triggered with same clock different flip-flops with different
simultaneously. clock.

The operation speed of an

Operation speed of a synchronous
Operation asynchronous counter is
counter is faster as compared to
Speed comparatively slower than a
that of an asynchronous counter.
synchronous counter.

Synchronous Counters are less

Asynchronous Counters are more
error-prone; they hardly produce
Error Prone error-prone and produce
any decoding errors because each
decoding errors in the system.
flip-flop is individually clocked.

All the flip-flops in a synchronous

In an asynchronous counter, the
counter coordinate with the clock,
output of one flip-flop acts as the
hence its design and
Complexity input of the next flip-flop, hence
implementation is complex as
its design and implementation is
compared to that of an
quite simple.
asynchronous counter.

A Synchronous counter can be

operated in any desired count An Asynchronous counter can
Sequence sequence, as it could get operate only in a fixed count
manipulated by changing the clock sequence, i.e., UP and DOWN.
sequence.

In case of asynchronous
There is no propagation delay
counters, there is a subsequent
Delay observed in case of Synchronous
propagation delay from one flip-
Counters.
flop to another.

Conclusion
All the flip-flops in a synchronous counter are clocked simultaneously with the same
clock input. In contrast, the constituent flip-flops of an asynchronous counter are clocked

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with different input signals at different instants of time.

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Digital Arithmetic Circuits

In this chapter, let us discuss about the basic arithmetic circuits like Binary adder and
Binary subtractor. These circuits can be operated with binary values 0 and 1.

Binary Adder
The most basic arithmetic operation is addition. The circuit, which performs the addition
of two binary numbers is known as Binary adder. First, let us implement an adder,
which performs the addition of two bits.

Half Adder
Half adder is a combinational circuit, which performs the addition of two binary numbers
A and B are of single bit. It produces two outputs sum, S & carry, C.

The Truth table of Half adder is shown below.

Inputs Outputs

A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

When we do the addition of two bits, the resultant sum can have the values ranging from
0 to 2 in decimal. We can represent the decimal digits 0 and 1 with single bit in binary.
But, we can’t represent decimal digit 2 with single bit in binary. So, we require two bits
for representing it in binary.

Let, sum, S is the Least significant bit and carry, C is the Most significant bit of the
resultant sum. For first three combinations of inputs, carry, C is zero and the value of S
will be either zero or one based on the number of ones present at the inputs. But, for
last combination of inputs, carry, C is one and sum, S is zero, since the resultant sum is
two.

From Truth table, we can directly write the Boolean functions for each output as

S = A ⊕ B

C = AB

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We can implement the above functions with 2-input Ex-OR gate & 2-input AND gate. The
circuit diagram of Half adder is shown in the following figure.

In the above circuit, a two input Ex-OR gate & two input AND gate produces sum, S &
carry, C respectively. Therefore, Half-adder performs the addition of two bits.

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Full Adder
Full adder is a combinational circuit, which performs the addition of three bits A, B and
Cin. Where, A & B are the two parallel significant bits and Cin is the carry bit, which is
generated from previous stage. This Full adder also produces two outputs sum, S &
carry, Cout, which are similar to Half adder.

The Truth table of Full adder is shown below.

Inputs Outputs

A B Cin Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

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When we do the addition of three bits, the resultant sum can have the values ranging
from 0 to 3 in decimal. We can represent the decimal digits 0 and 1 with single bit in
binary. But, we can’t represent the decimal digits 2 and 3 with single bit in binary. So, we
require two bits for representing those two decimal digits in binary.

Let, sum, S is the Least significant bit and carry, Cout is the Most significant bit of
resultant sum. It is easy to fill the values of outputs for all combinations of inputs in the
truth table. Just count the number of ones present at the inputs and write the
equivalent binary number at outputs. If Cin is equal to zero, then Full adder truth table is
same as that of Half adder truth table.

We will get the following Boolean functions for each output after simplification.

S = A ⊕ B ⊕ C in

cout = AB + (A ⊕ B) cin

The sum, S is equal to one, when odd number of ones present at the inputs. We know
that Ex-OR gate produces an output, which is an odd function. So, we can use either two
2input Ex-OR gates or one 3-input Ex-OR gate in order to produce sum, S. We can
implement carry, Cout using two 2-input AND gates & one OR gate. The circuit diagram
of Full adder is shown in the following figure.

This adder is called as Full adder because for implementing one Full adder, we require
two Half adders and one OR gate. If Cin is zero, then Full adder becomes Half adder. We
can verify it easily from the above circuit diagram or from the Boolean functions of
outputs of Full adder.

4-bit Binary Adder

The 4-bit binary adder performs the addition of two 4-bit numbers. Let the 4-bit
binary numbers, A = A3 A2 A1 A0 and B = B3 B2 B1 B0 . We can implement 4-bit
binary adder in one of the two following ways.

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Use one Half adder for doing the addition of two Least significant bits and three
Full adders for doing the addition of three higher significant bits.
Use four Full adders for uniformity. Since, initial carry Cin is zero, the Full adder
which is used for adding the least significant bits becomes Half adder.

For the time being, we considered second approach. The block diagram of 4-bit binary
adder is shown in the following figure.

Here, the 4 Full adders are cascaded. Each Full adder is getting the respective bits of two
parallel inputs A & B. The carry output of one Full adder will be the carry input of
subsequent higher order Full adder. This 4-bit binary adder produces the resultant sum
having at most 5 bits. So, carry out of last stage Full adder will be the MSB.

In this way, we can implement any higher order binary adder just by cascading the
required number of Full adders. This binary adder is also called as ripple carry (binary)
adder because the carry propagates (ripples) from one stage to the next stage.

Binary Subtractor
The circuit, which performs the subtraction of two binary numbers is known as Binary
subtractor. We can implement Binary subtractor in following two methods.

Cascade Full subtractors

2’s complement method

In first method, we will get an n-bit binary subtractor by cascading 'n' Full subtractors.
So, first you can implement Half subtractor and Full subtractor, similar to Half adder &
Full adder. Then, you can implement an n-bit binary subtractor, by cascading ‘n’ Full
subtractors. So, we will be having two separate circuits for binary addition and
subtraction of two binary numbers.

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In second method, we can use same binary adder for subtracting two binary numbers
just by doing some modifications in the second input. So, internally binary addition
operation takes place but, the output is resultant subtraction.

We know that the subtraction of two binary numbers A & B can be written as,

′
A − B = A + (2 s compliment of B)

′
⇒ A − B = A + (1 s compliment of B) + 1

4-bit Binary Subtractor

The 4-bit binary subtractor produces the subtraction of two 4-bit numbers. Let the
4bit binary numbers, A = A3 A2 A1 A0 and B = B3 B2 B1 B0 . Internally, the operation
of 4-bit Binary subtractor is similar to that of 4-bit Binary adder. If the normal bits of
binary number A, complemented bits of binary number B and initial carry (borrow), Cin
as one are applied to 4-bit Binary adder, then it becomes 4-bit Binary subtractor. The
block diagram of 4-bit binary subtractor is shown in the following figure.

This 4-bit binary subtractor produces an output, which is having at most 5 bits. If Binary
number A is greater than Binary number B, then MSB of the output is zero and the
remaining bits hold the magnitude of A-B. If Binary number A is less than Binary number
B, then MSB of the output is one. So, take the 2’s complement of output in order to get
the magnitude of A-B.

In this way, we can implement any higher order binary subtractor just by cascading the
required number of Full adders with necessary modifications.

Binary Adder / Subtractor

The circuit, which can be used to perform either addition or subtraction of two binary
numbers at any time is known as Binary Adder / subtractor. Both, Binary adder and
Binary subtractor contain a set of Full adders, which are cascaded. The input bits of
binary number A are directly applied in both Binary adder and Binary subtractor.

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There are two differences in the inputs of Full adders that are present in Binary adder
and Binary subtractor.

The input bits of binary number B are directly applied to Full adders in Binary
adder, whereas the complemented bits of binary number B are applied to Full
adders in Binary subtractor.

The initial carry, C0 = 0 is applied in 4-bit Binary adder, whereas the initial carry
(borrow), C0 = 1 is applied in 4-bit Binary subtractor.

We know that a 2-input Ex-OR gate produces an output, which is same as that of first
input when other input is zero. Similarly, it produces an output, which is complement of
first input when other input is one.

Therefore, we can apply the input bits of binary number B, to 2-input Ex-OR gates. The
other input to all these Ex-OR gates is C0. So, based on the value of C0, the Ex-OR gates
produce either the normal or complemented bits of binary number B.

4-bit Binary Adder / Subtractor

The 4-bit binary adder / subtractor produces either the addition or the subtraction of two
4-bit numbers based on the value of initial carry or borrow, 𝐶0. Let the 4-bit binary
numbers, A = A3 A2 A1 A0 and B = B3 B2 B1 B0 . The operation of 4-bit Binary adder /
subtractor is similar to that of 4-bit Binary adder and 4-bit Binary subtractor.

Apply the normal bits of binary numbers A and B & initial carry or borrow, C0 from
externally to a 4-bit binary adder. The block diagram of 4-bit binary adder / subtractor
is shown in the following figure.

If initial carry, 𝐶0 is zero, then each full adder gets the normal bits of binary numbers A
& B. So, the 4-bit binary adder / subtractor produces an output, which is the addition of
two binary numbers A & B.

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If initial borrow, 𝐶0 is one, then each full adder gets the normal bits of binary number A
& complemented bits of binary number B. So, the 4-bit binary adder / subtractor
produces an output, which is the subtraction of two binary numbers A & B.

Therefore, with the help of additional Ex-OR gates, the same circuit can be used for both
addition and subtraction of two binary numbers.

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Digital Electronics - Combinational Circuits

A combinational circuit, also called a combinational logic circuit, is a digital
electronic circuit whose output is determined by present inputs only.

The output of a combinational logic circuit does not depend on the history of the circuit
operation. In other words, a combinational circuit is a digital logic circuit whose output
depends only on the present input values and does not depend on any feedback or
previous input or output values.

In this chapter, we will explain the fundamentals of combinational circuits, and its block
diagram, types, and applications. So, let’s start with the basic definition of combinational
circuits.

What is a Combinational Circuit?

A combinational circuit is a type of digital logic circuit whose output depends on the
present input values only and does not depend on past input and output values.
Therefore, a combinational circuit is considered to not have a memory element in its
circuit that stores previous inputs and outputs. Instead, it consists of a certain number of
input lines to apply current input values and a certain number of output lines.

The most important characteristic of a combinational circuit is that it does not have any
feedback path between input and output. Therefore, the combinational circuits can be
categorized as open-loop systems.

Block Diagram of Combinational Circuit

The following figure depicts the block diagram of a combinational logic circuit.

Here, we can see that there are only three key elements in the circuit diagram of a
combinational circuit, they are −

Input Lines − The input lines are used to enter the input values into the
combinational circuit.

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Processing Unit − It is the main element that processes the input values
depending on the type of the circuit. For example, a full adder adds three binary
bits.

Output Lines − The output lines are used to take results generated by the circuit.

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Characteristics of Combinational Circuits

The following are the main characteristics of combinational circuits −

The output of a combinational circuit, at any instant of time, depends only on the
present input values at that instant of time.

Combinational circuits do not use any kind of memory element in their circuits.
Thus, the previous state of input and output values do not have any effect on the
present operation of the circuit.
The output of a combinational circuit can be entirely predicted using its logical
operation and input values.
Combinational circuits produce an instantaneous output in response to any
change in its input values.

Types of Combinational Circuits

In digital electronics, the combinational circuits are important components of digital
systems. Depending on the functions performed, there are various types of
combinational circuits. Some common types of combinational circuits and their functions
are explained below −

Binary Adders

Binary Subtractors
Multiplexers (MUX)

Demultiplexers (DEMUX)
Encoders

Decoders
Comparators

In the following sections of this chapter, we will discuss briefly about each of these
combinational circuits along with their functions.

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Binary Adders
A binary adder is a combinational circuit that performs the addition of binary digits or
bits. Depending on the design and configuration, there are two types of binary adders
namely, Half Adder and Full Adder.

Half Adder
The half adder is a combinational logic circuit with two inputs and two outputs. The half
adder circuit is designed to add two single-bit binary numbers A and B. It is the basic
building block for the addition of two single-bit numbers. This circuit has two outputs
namely, sum and carry.

Full Adder
The full adder is designed to overcome the drawback of a half adder which is the ability
to add only two bits. Therefore, the full adder is a three-input and two-output
combinational circuit. Where, the inputs are two one-bit numbers A and B, and a carry C
from the previous addition. The outputs are sum and carry output.

Binary Subtractors
A binary subtractor is a combinational logic circuit used to subtract one binary number
from another. Similar to binary adder, there are two types of binary subtractors namely,
half-subtractor and full-subtractor.

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Half Subtractor
A half subtractor is a combination circuit with two inputs (A and B) and two outputs
(difference and borrow). It produces the difference between the two binary bits at the
input and also produces an output (Borrow) to indicate if a 1 has been borrowed. In
binary subtraction (A-B), A is called a Minuend bit and B is called a Subtrahend bit.

Full Subtractor
The full subtractor is also a combinational circuit with three inputs A, B, and Bin, and
two outputs D and Bout.

Here, A is the minuend bit, B is the subtrahend bit, Bin is the previous borrow bit
produced by the previous stage, D is the difference output and Bout is the borrow
output.

Multiplexers (MUX)
A multiplexer is a special type of combinational logic circuit. It consists of n-data input
lines, one output, and m-select lines. For a multiplexer, n = 2m.

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A multiplexer is a digital circuit that selects one of the n data inputs and routes it to the
output line. The selection of one of the n data inputs is done by the select lines.
Depending on the digital code applied at the select lines, one out of "n" data inputs is
selected and transmitted to the output line.

In some multiplexers, there is also an enable input E which is useful in cascading of

multiple multiplexers.

Depending on the number of input lines, there can be several types of multiplexers.
Some common types of multiplexers include 2:1 Multiplexer, 4:1 Multiplexer, 16:1
Multiplexer, and 32:1 Multiplexer.

Demultiplexers (DEMUX)
A demultiplexer performs a distribution operation i.e., it receives one data input and
distributes it over several output lines.

A demultiplexer has only one input line, "n" output lines, and "m" select lines. At a time,
only one output line is selected by the digital code applied to the select lines and the
data input is transmitted to the selected output line.

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Demultiplexers can be classified into various types depending on the number of output
lines. Some commonly used types of demultiplexers include: 1:2 Demultiplexer, 1:4
Demultiplexer, 1:16 Demultiplexer, and 1:32 Demultiplexer.

Encoders
An encoder is a combinational circuit that is designed to convert a piece of information
into a binary code. An encoder has n number of input lines and m number of output
lines, where n = 2m.

An encoder generates an m-bit binary code corresponding to the digital input applied to
it. In other words, an encoder accepts an n-input digital word and converts it into an m-
bit another digital word.

Examples of encoder include 4-to-2 encoder, octal-to-binary encoder, hexadecimal-to-

binary encoder, priority encoder, etc.

Decoders
A decoder is a combinational circuit that converts a binary code into a normal word like a
decimal digit. A decoder typically consists of n input lines and m output lines, where the
m = 2 n.

Decoders are widely used in display drivers, data distribution systems, etc.

Some of the commonly used types of decoders are 2 to 4 decoder, 3 to 8 decoder, 4 to

16 decoder, BCD to seven segment decoder, etc.

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Comparators
A comparator is a combinational logic circuit developed to compare two binary numbers.
Comparators are mainly used in arithmetic and control circuits to perform comparison or
logical operations.

A comparator, as its name suggests, compares the input values and checks whether they
are equal or one input is greater/less than the other input.

Limitations of Combinational Circuits

Combinational circuits have several advantages such as fast operational speed, simpler
circuit, predictable operation, etc. However, they do have several limitations too, some of
which are listed below −

Combinational circuits do not have any memory element. They are incapable to
store history of circuit operation.

Combinational circuits cannot be used to implement certain highly complex logic

functions.

Combinational circuits do not have any feedback mechanism. That makes the
combinational circuits to have limited functionality.

At large scale, combinational circuits have several design complexities that can
result in poor performance and inefficient resource utilization.

Applications of Combinational Circuits

Combinational circuits are the fundamental building blocks in various digital devices and
systems. They are widely used in several digital devices in which combinational circuits
are used −

Microprocessors and Microcontrollers

Digital Computers

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Calculators

Digital Communication Systems

Keyboards

Smartphones and Digital Watches, etc

Conclusion
A combinational logic circuit is a key component in various digital devices and systems.
It can be defined as an interconnected system of digital components whose output
depends only on the present states of inputs and it does not depend on past input and
output values.

In this chapter, we explained the characteristics, limitations, and applications of

combinational circuits.

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Digital Electronics - Conversion of Flip-Flops

In previous chapter, we discussed the four flip-flops, namely SR flip-flop, D flip-flop, JK
flip-flop & T flip-flop. We can convert one flip-flop into the remaining three flip-flops by
including some additional logic. So, there will be total of twelve flip-flop conversions.

Follow these steps for converting one flip-flop to the other.

Consider the characteristic table of desired flip-flop.

Fill the excitation values (inputs) of given flip-flop for each combination of present
state and next state. The excitation table for all flip-flops is shown below.

Present Next SR Flip-Flop D flip-flop JK Flip-Flop T Flip-Flop

State State Inputs input Inputs Input

Q(t) Q(t+1) S R D J K T

0 0 0 x 0 0 x 0

0 1 1 0 1 1 x 1

1 0 0 1 0 x 1 1

1 1 x 0 1 x 0 0

Get the simplified expressions for each excitation input. If necessary, use Kmaps for
simplifying.

Draw the circuit diagram of desired flip-flop according to the simplified expressions
using given flip-flop and necessary logic gates.

Now, let us convert few flip-flops into other. Follow the same process for remaining
flipflop conversions.

SR Flip-Flop to other Flip-Flop Conversions

Following are the three possible conversions of SR flip-flop to other flip-flops.

SR Flip-Flop to D Flip-Flop

SR Flip-Flop to JK Flip-Flop
SR Flip-Flop to T Flip-Flop

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SR Flip-Flop to D Flip-Flop Conversion

Here, the given flip-flop is SR flip-flop and the desired flip-flop is D flip-flop. Therefore,
consider the following characteristic table of D flip-flop.

D Flip-Flop Input Present State Next State

D Q(t) Q(t + 1)

0 0 0

0 1 0

1 0 1

1 1 1

We know that SR flip-flop has two inputs S & R. So, write down the excitation values of
SR flip-flop for each combination of present state and next state values. The following
table shows the characteristic table of D flip-flop along with the excitation inputs of SR
flip-flop.

D Flip-Flop Input Present State Next State SR Flip-Flop Inputs

D Q(t) Q(t + 1) S R

0 0 0 0 x

0 1 0 0 1

1 0 1 1 0

1 1 1 x 0

From the above table, we can write the Boolean functions for each input as below.

S = m2 + d3

R = m1 + d0

We can use 2 variable K-Maps for getting simplified expressions for these inputs. The k-
Maps for S & R are shown below.

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So, we got S = D & R = D' after simplifying. The circuit diagram of D flip-flop is shown
in the following figure.

This circuit consists of SR flip-flop and an inverter. This inverter produces an output,
which is complement of input, D. So, the overall circuit has single input, D and two
outputs Q(t) & Q(t)'. Hence, it is a D flip-flop. Similarly, you can do other two
conversions.

D Flip-Flop to other Flip-Flop Conversions

Following are the three possible conversions of D flip-flop to other flip-flops.

D Flip-Flop to T Flip-Flop
D Flip-Flop to SR Flip-Flop

D Flip-Flop to JK Flip-Flop

D Flip-Flop to T Flip-Flop conversion

Here, the given flip-flop is D flip-flop and the desired flip-flop is T flip-flop. Therefore,
consider the following characteristic table of T flip-flop.

T Flip-Flop Input Present State Next State

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T Q(t) Q(t + 1)

0 0 0

0 1 1

1 0 1

1 1 0

We know that D flip-flop has single input D. So, write down the excitation values of D
flip-flop for each combination of present state and next state values. The following table
shows the characteristic table of T flip-flop along with the excitation input of D flip-flop.

T Flip-Flop Input Present State Next State D Flip-Flop Input

T Q(t) Q(t + 1) D

0 0 0 0

0 1 1 1

1 0 1 1

1 1 0 0

From the above table, we can directly write the Boolean function of D as below.

D = T ⊕ Q (t )

So, we require a two input Exclusive-OR gate along with D flip-flop. The circuit diagram
of T flip-flop is shown in the following figure.

This circuit consists of D flip-flop and an Exclusive-OR gate. This Exclusive-OR gate
produces an output, which is Ex-OR of T and Q(t). So, the overall circuit has single input,

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T and two outputs Q(t) & Q(t)’. Hence, it is a T flip-flop. Similarly, you can do other two
conversions.

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JK Flip-Flop to other Flip-Flop Conversions

Following are the three possible conversions of JK flip-flop to other flip-flops.

JK Flip-Flop to T Flip-Flop
JK Flip-Flop to D Flip-Flop

JK Flip-Flop to SR Flip-Flop

JK Flip-Flop to T Flip-Flop conversion

Here, the given flip-flop is JK flip-flop and the desired flip-flop is T flip-flop. Therefore,
consider the following characteristic table of T flip-flop.

T Flip-Flop Input Present State Next State

T Q(t) Q(t + 1)

0 0 0

0 1 1

1 0 1

1 1 0

We know that JK flip-flop has two inputs J & K. So, write down the excitation values of JK
flip-flop for each combination of present state and next state values. The following table
shows the characteristic table of T flip-flop along with the excitation inputs of JK
flipflop.

T Flip-Flop Input Present State Next State JK Flip-Flop Inputs

T Q(t) Q(t + 1) J K

0 0 0 0 x

0 1 1 x 0

1 0 1 1 x

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1 1 0 x 1

From the above table, we can write the Boolean functions for each input as below.

J = m2 + d1 + d3

K = m3 + d0 + d2

We can use 2 variable K-Maps for getting simplified expressions for these two inputs. The
k-Maps for J & K are shown below.

So, we got, J = T & K = T after simplifying. The circuit diagram of T flip-flop is shown
in the following figure.

This circuit consists of JK flip-flop only. It doesn’t require any other gates. Just connect
the same input T to both J & K. So, the overall circuit has single input, T and two outputs
Q(t) & Q(t)’. Hence, it is a T flip-flop. Similarly, you can do other two conversions.

T Flip-Flop to other Flip-Flop Conversions

Following are the three possible conversions of T flip-flop to other flip-flops.

T Flip-Flop to D Flip-Flop
T Flip-Flop to SR Flip-Flop

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T Flip-Flop to JK Flip-Flop

T Flip-Flop to D Flip-Flop conversion

Here, the given flip-flop is T flip-flop and the desired flip-flop is D flip-flop. Therefore,
consider the characteristic table of D flip-flop and write down the excitation values of T
flip-flop for each combination of present state and next state values. The following table
shows the characteristic table of D flip-flop along with the excitation input of T flip-
flop.

D Flip-Flop Input Present State Next State T Flip-Flop Input

D Q(t) Q(t + 1) T

0 0 0 0

0 1 0 1

1 0 1 1

1 1 1 0

From the above table, we can directly write the Boolean function of T as below.

T = D ⊕ Q (t)

So, we require a two input Exclusive-OR gate along with T flip-flop. The circuit diagram
of D flip-flop is shown in the following figure.

This circuit consists of T flip-flop and an Exclusive-OR gate. This Exclusive-OR gate
produces an output, which is Ex-OR of D and Q(t). So, the overall circuit has single input,

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D and two outputs Q(t) & Q(t)’. Hence, it is a D flip-flop. Similarly, you can do other two
conversions.

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Digital Electronics - Decoders

What is a Decoder?
In digital electronics, a combinational logic circuit that converts an N-bit binary input
code into M output channels in such a way that only one output channel is activated for
each one of the possible combinations of inputs is known as a decoder.

In other words, a combinational logic circuit which converts N input lines into a
maximum of 2N output lines is called a decoder.

Therefore, a decoder is a combination logic circuit that is capable of identifying or

detecting a particular code. The operation that a decoder performs is referred to as
decoding. A general block diagram of a decoder is shown in Figure-1.

Here, the decoder has N input lines and M (2N) output lines. In a decoder, each of the N
input lines can be a 0 or a 1, hence the number of possible input combinations or codes
be equal to 2N. For each of these input combinations, only one of the M output lines will
be active, and all other output lines will remain inactive.

Types of Decoders
There are several types of decoder present. But, based on the input and output lines
present, decoders may classified into the following three types −

2 to 4 Decoder
3 to 8 Decoder

4 to 16 Decoder

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Now, let us discuss each type of decoder in detail one by one.

2 to 4 Decoder

The 2 to 4 decoder is one that has 2 input lines and 4 (22) output lines. The functional
block diagram of the 2 to 4 decoder is shown in Figure-2.

When this decoder is enabled with the help of enable input E, then its one of the four
outputs will be active for each combination of inputs. The operation of this 2-line to 4-
line decoder can be analyzed with the help of its truth table which is given below.

Inputs Outputs

E A B Y3 Y2 Y1 Y0

0 X X 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

Using this truth table, we can derive the Boolean expression for each output as follows −

¯
Y0 = E ⋅ A ⋅ B̄

¯
Y1 = E ⋅ A ⋅ B

¯
Y2 = E ⋅ A ⋅ B

Y3 = E ⋅ A ⋅ B

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As each output term contains products of input variables that can be implemented with
the help of AND gates. Therefore, the logic circuit diagram of the 2 to 4 decoder is shown
in Figure-3.

Operation
The operation of logic circuit of the 2 to 4 decoder is described as follows −

When enable input (E) is inactive, i.e. set to 0, none of the AND gates will function.
When enable input (E) is made active by setting it to 1, then the circuit works as
explained below.
When A = 0 and B = 0, the AND gate 1 becomes active and produces output Y0.

When A = 0 and B = 1, the AND gate 2 becomes active and produces output Y1.

When A = 1 and B = 0, the AND gate 3 becomes active and produces output Y2.

When A = 1 and B = 1, the AND gate 4 becomes active and produces output Y3.

3 to 8 Decoder

The 3 to 8 decoder is one that has 3 input lines and 8 (23) output lines. The functional
block diagram of the 3 to 8 decoder is shown in Figure-4.

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When this decoder is enabled with the help of enable input E, then it's one of the eight
outputs will be active for each combination of inputs. The operation of this 3-line to 8-
line decoder can be analyzed with the help of its function table which is given below.

Inputs Outputs

E A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 0

1 0 1 0 0 0 0 0 0 1 0 0

1 0 1 1 0 0 0 0 1 0 0 0

1 1 0 0 0 0 0 1 0 0 0 0

1 1 0 1 0 0 1 0 0 0 0 0

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

Using this function table, we can derive the Boolean expression for each output as
follows −

¯ ¯ ¯
Y0 = E ABC

¯ ¯
Y1 = E ABC

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¯ ¯
Y2 = E AB C

¯
Y3 = E AB C

¯ ¯
Y4 = E A BC

Y5 = E A B̄ C

¯
Y6 = E A B C

Y7 = E A B C

As we can see, each output term contains products of input variables, hence they can be
implemented with the help of AND gates. Therefore, the logic circuit diagram of the 3 to
8 decoder is shown in Figure-5.

Operation

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The operation of logic circuit of the 3 to 8 decoder is described as follows −

When enable input (E) is inactive, i.e. set to 0, none of the AND gates will function.
When enable input (E) is made active by setting it to 1, then the circuit works as
described below.
When A = 0, B = 0, and C = 0, the AND gate 1 becomes active and produces
output Y0.

When A = 0, B = 0, and C = 1, the AND gate 2 becomes active and produces

output Y1.

When A = 0, B = 1, and C = 0, the AND gate 3 becomes active and produces

output Y2.

When A = 0, B = 1, and C = 1, the AND gate 4 becomes active and produces

output Y3.

When A = 1, B = 0, and C = 0, the AND gate 5 becomes active and produces

output Y4.

When A = 1, B = 0, and C = 1, the AND gate 6 becomes active and produces

output Y5.

When A = 1, B = 1, and C = 0, the AND gate 7 becomes active and produces

output Y6.

When A = 1, B = 1, and C = 1, the AND gate 8 becomes active and produces

output Y7.

4 to 16 Decoder

The 4 to 16 decoder is the type of decoder which has 4 input lines and 16 (214) output
lines. The functional block diagram of the 4 to 16 decoder is shown in Figure-6.

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When this decoder is enabled with the help of enable input E, it's one of the sixteen
outputs will be active for each combination of inputs. The operation of the 4-line to 16-
line decoder can be analyzed with the help of its function table which is given below.

Inputs
Output
E A B C D

0 X X X X 0

1 0 0 0 0 Y0

1 0 0 0 1 Y1

1 0 0 1 0 Y2

1 0 0 1 1 Y3

1 0 1 0 0 Y4

1 0 1 0 1 Y5

1 0 1 1 0 Y6

1 0 1 1 1 Y7

1 1 0 0 0 Y8

1 1 0 0 1 Y9

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1 1 0 1 0 Y10

1 1 0 1 1 Y11

1 1 1 0 0 Y12

1 1 1 0 1 Y13

1 1 1 1 0 Y14

1 1 1 1 1 Y15

From this function table, we can directly write the Boolean expression for each output as
follows −

¯ ¯ ¯ ¯
Y0 = E ABC D

¯ ¯ ¯
Y1 = E ABC D

¯
Y2 = E A B̄ C D̄

¯ ¯
Y3 = E ABC D

¯ ¯
Y4 = E A B C D̄

¯ ¯
Y5 = E AB C D

¯ ¯
Y6 = E AB C D

¯
Y7 = E AB C D

¯ ¯ ¯
Y8 = E A BC D

¯
Y9 = E A B̄ C D

¯ ¯
Y10 = E A BC D

Y11 = E A B̄ C D

¯ ¯
Y12 = E A B C D

¯
Y13 = E A B C D

= ¯
E A B C D
Y14

Y15 = E A B C D

We can implement these output expression in the same way as we done for the 2 to 4
decoder and 3 to 8 decoder.

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Now, let us discuss the applications of decoders.

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Applications of Decoders
Decoders are used in the cases where an output or a collection of outputs is to be
activated only on the occurrence of a particular combination of input codes. Some
important applications of decoders are listed below −

Decoders are used for code conversions.

Decoders are extensively used in memory systems of computers.

Decoders are also used for de-multiplexing or data distribution.

Decoders are also used in data routing applications where very short propagation
delay is required.

Decoder may also be used for timing or sequencing purposes.

Decoders are also utilized to turn on and off digital devices at a specific time.

This is all about decoder and its applications in digital electronic systems.

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Digital Electronics - Demultiplexers

What is a Demultiplexer?
A Demultiplexer is a combinational logic circuit that accepts a single input and
distributes it over several output lines. Demultiplexer is also termed as DEMUX in short.
As Demultiplexer is used to transmit the same data to different destinations, hence it is
also known as data distributor.

There is another combinational logic circuit named multiplexer which performs opposite
operation of the Demultiplexer, i.e. accepts several inputs and transmits one of them at
time to the output line.

From the definition, we can state that a Demultiplexer is a 1-to-2n device. The functional
block diagram of a typical 1×2n Demultiplexer is shown in Figure-1.

It can be seen that the Demultiplexer has only one data input line, 2n output lines, and n
select lines. The logic level applied to select lines of the Demultiplexer determines the
output channel to which the input data will be transmitted.

Demultiplexer circuit are the combinational logic circuit widely used in digital decoders
and Boolean function generator circuits.

Types of Demultiplexer

Based on the number of output lines (2n), Demultiplexers can be classified into several
types. Some commonly used types of Demultiplexers are −

1×2 Demultiplexer

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1×4 Demultiplexer

Now, let us briefly discuss each type of Demultiplexer.

1×2 Demultiplexer
The functional block diagram of a 1×2 Demultiplexer is shown in Figure-2.

The 1×2 Demultiplexer consists of 1 input line (I), 1 select line (S), and 2 output lines
(Y0 and Y1). The logic level applied at the select line determines the output line to which
the input data will be transmitted.

The operation of the 1×2 Demultiplexer can be analyzed with the help of its function
table given below.

Select Line Outputs

S Y1 Y0

0 0 I

1 I 0

From this function table of 1×2 Demultiplexer, we can directly derive the Boolean
expression for each output as follow.

¯
Y0 = SI

And,

Y1 = S I

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1×4 Demultiplexer
The functional block diagram of 1×4 Demultiplexer is shown in Figure-3.

The 1×4 Demultiplexer has 1 input line (I), 2 select line (S0 and S1), and 4 output lines
(Y0, Y1, Y2, and Y3). The logic level applied to the select lines determines the output line
to which the input data (I) will be transmitted.

The operation of the 1×4 Demultiplexer can be understood with the help of its function
table given below.

Select Line Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From this truth table of 1×4 Demultiplexer, we can directly write the Boolean expression
for each output as follow.

¯ ¯
Y0 = S1 S0 I

¯
Y1 = S1 S0 I

¯
Y2 = S1 S0 I

Y3 = S1 S0 I

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We can easily understand the operation of the above circuit. Similarly, you can
implement 1×8 Demultiplexer and 1×16 Demultiplexer by following the same procedure.

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Implementation of Higher-order Demultiplexer

Now, let us implement the following two higher-order Demultiplexers using lower-order
Demultiplexers.

1×8 Demultiplexer

1×16 Demultiplexer

1×8 Deultiplexer
In this section, let us implement 1×8 Demultiplexer using 1×4 Demultiplexers and 1×2
Demultiplexer. We know that 1×4 Demultiplexer has single input, two selection lines and
four outputs. Whereas, 1×8 Demultiplexer has single input, three selection lines and
eight outputs.

So, we require two 1×4 Demultiplexers in second stage in order to get the final eight
outputs. Since, the number of inputs in second stage is two, we require 1×2
Demultiplexer in first stage so that the outputs of first stage will be the inputs of
second stage. Input of this 1×2 Demultiplexer will be the overall input of 1×8
Demultiplexer.

Let the 1×8 Demultiplexer has one input I, three selection lines s2, s1 & s0 and outputs
Y7 to Y0. The Truth table of 1×8 Demultiplexer is shown below.

Selection Inputs Outputs

s2 s1 s0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 0 I 0

0 1 0 0 0 0 0 0 I 0 0

0 1 1 0 0 0 0 I 0 0 0

1 0 0 0 0 0 I 0 0 0 0

1 0 1 0 0 I 0 0 0 0 0

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1 1 0 0 I 0 0 0 0 0 0

1 1 1 I 0 0 0 0 0 0 0

We can implement 1×8 Demultiplexer using lower order Multiplexers easily by

considering the above Truth table. The block diagram of 1×8 Demultiplexer is shown in
the following figure.

The common selection lines, s1 & s0 are applied to both 1×4 Demultiplexers. The
outputs of upper 1×4 Demultiplexer are Y7 to Y4 and the outputs of lower 1×4
Demultiplexer are Y3 to Y0.

The other selection line, s2 is applied to 1×2 Demultiplexer. If s2 is zero, then one of
the four outputs of lower 1×4 Demultiplexer will be equal to input, I based on the values
of selection lines s1 & s0. Similarly, if s2 is one, then one of the four outputs of upper
1×4 Demultiplexer will be equal to input, I based on the values of selection lines s1 & s0.

1×16 Demultiplexer
In this section, let us implement 1×16 Demultiplexer using 1×8 Demultiplexers and 1×2
Demultiplexer. We know that 1×8 Demultiplexer has single input, three selection lines
and eight outputs. Whereas, 1×16 Demultiplexer has single input, four selection lines
and sixteen outputs.

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So, we require two 1×8 Demultiplexers in second stage in order to get the final
sixteen outputs. Since, the number of inputs in second stage is two, we require 1×2
Demultiplexer in first stage so that the outputs of first stage will be the inputs of
second stage. Input of this 1×2 Demultiplexer will be the overall input of 1×16
Demultiplexer.

Let the 1×16 Demultiplexer has one input I, four selection lines s3, s2, s1 & s0 and
outputs Y15 to Y0. The block diagram of 1×16 Demultiplexer using lower order
Multiplexers is shown in the following figure.

The common selection lines s2, s1 & s0 are applied to both 1×8 Demultiplexers. The
outputs of upper 1×8 Demultiplexer are Y15 to Y8 and the outputs of lower 1×8
Demultiplexer are Y7 to Y0.

The other selection line, s3 is applied to 1×2 Demultiplexer. If s3 is zero, then one of
the eight outputs of lower 1×8 Demultiplexer will be equal to input, I based on the
values of selection lines s2, s1 & s0. Similarly, if s3 is one, then one of the 8 outputs of
upper 1×8 Demultiplexer will be equal to input, I based on the values of selection lines
s 2 , s1 & s 0 .

Integrated Circuits (ICs) Working as Demultiplexer

Demultiplexer can also be built in the form of ICs. There are several types of ICs
available that work as Demultiplexer. Some common of them are listed below −

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74139 IC works as a 1×4 Demultiplexer

74237 IC works as a 1×8 Demultiplexer

74154 IC works as a 1×16 Demultiplexer

Advantages of Demultiplexer
The important advantages of Demultiplexer are given below −

By using Demultiplexers, we can increase the efficiency of the communication

systems.
Demultiplexer can separate different signals from a mixed signal stream.

Demultiplexer can decode the signals produced by a multiplexer.

Disadvantages of Demultiplexer
The major disadvantages of Demultiplexers are listed below −

The use of Demultiplexer can cause wastage of bandwidth.

The synchronization of signals can create a delay in the system.

Applications of Demultiplexer
Demultiplexer is a crucial combinational logic circuit which is used in a number of
applications. Some important uses of Demultiplexers are listed below −

Demultiplexer are used in several input and output devices for data routing.
Demultiplexer are used in digital control systems to select one signal from a mutual
stream of signals.
Demultiplexer are also employed for data transmission in synchronous systems.

Demultiplexer are also utilized in data acquisition systems.

Demultiplexer can be used for generating Boolean functions.

Demultiplexer can be used in serial to parallel converters.

Demultiplexer are used for broadcasting of ATM packets.

Demultiplexer can also be used to design automatic test equipment, etc.

This is all about Demultiplexer, its types, and applications.

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Digital Electronics - Encoders

An encoder is a combinational logic circuit that is used to convert a normal or familiar
information into a coded format. In other words, an encoder is a digital device that
coverts a piece of information represented in the form of decimal digits and alphabetic
characters into a coded form like binary representation. The operation that the encoder
performs is termed as encoding.

In this chapter, we will explain the basics of encoder and commonly used types of
encoders.

What is an Encoder?
An encoder is a digital combinational circuit that converts a human friendly information
into a coded format for processing using machines. In simple words, an encoder converts
a piece of information normal form to coded form. This process is called encoding.

Encoders are crucial components in various digital electronics applications such as data
transmission, controlling and automation, communication, signal processing, etc.

An encoder consists of a certain number of input and output lines. Where, an encoder
can have maximum of "2n" input lines whereas "n" output lines. Hence, an encoder
encodes information represented by "2n" input lines with "n" bits.

The block diagram of an encoder is shown in the following figure −

Let us now discuss different types of encoders commonly used in digital electronic
applications.

Types of Encoders
Some of the commonly used types of encoders in digital electronics −

4 to 2 Encoder

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8 to 3 Encoder (Octal Encoder)

Decimal to BCD Encoder

Let us now discuss these three types of most commonly used encoders in detail.

4 to 2 Encoder

A 4 to 2 Encoder is a type of encoder which has 4 (22) input lines and 2 output lines. It
produces an output code (i.e., convert input information in a 2-bit format) depending on
the combination of input lines.

The block diagram of a 4 to 2 Encoder is shown in the following figure.

The working of a 4 to 2 Encoder for different input combinations is described in the

following truth table −

Inputs Outputs

I3 I2 I1 I0 Y1 Y0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From this truth table, we can derive the Boolean expression for each output of the 4 to 2
Encoder as follows −

Y0 = I1 + I3

Y1 = I2 + I3

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It is clear that we can implement the logic circuit of the 4 to 2 Encoder using two OR
gates. The following figure depicts the logic diagram of the 4 to 2 Encoder.

Applications of 4 to 2 Encoder
The 4 to 2 Encoder is widely used in the following applications: Data multiplexing,
Generating digital control signals, Address decoding applications, Encoding data in digital
systems, etc.

Octal to Binary Encoder

The octal to binary encoder is a type of encoder that converts an octal code into binary
code. It accepts 8 input lines and produces a 3-bit output depending on the combination
of input lines. Therefore, it is also known as 8 to 3 Encoder.

The block diagram of an octal to binary encoder is shown in the following figure −

The following truth table describes the working of an octal to binary encoder −

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Inputs Outputs

I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From this truth table, we can write the Boolean expression for the outputs of the octal to
binary encoder as follows.

Y0 = I1 + I3 + I5 + I7

Y1 = I2 + I3 + I6 + I7

Y2 = I4 + I5 + I6 + I7

From these expressions, it is clear that the implementation of an octal to binary encoder
requires 3 OR gates.

The logic circuit diagram of the octal to binary encoder is shown in the following figure −

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Applications of Octal to Binary Encoder

The octal to binary encoder is used in the following applications −

Data conversion in digital systems.

Conversion of octal memory addresses into binary memory addresses.

In microprocessors and microcontrollers, to convert octal instructions into binary

format.

In communication systems, to encode octal data into binary form for

transmission, etc.

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Decimal to BCD Encoder

A type of encoder that can convert a decimal number or information represented using
decimal number into its equivalent binary-coded decimal (BCD) format is known as a
decimal to BCD encoder.

In the BCD encoding scheme, each decimal digit can be converted into a 4-bit binary
representation. The following table shows the BCD equivalents of decimal digital from 0
to 9.

Decimal Digit BCD Code

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

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The decimal to BCD encoder accepts 10 input lines and produces a 4-bit BCD output
depending on the combination of input lines. Therefore, sometimes it is also called a 10
to 4 encoder.

The following illustration depicts the block diagram of a decimal to BCD encoder.

The truth table describing the working of the decimal to BCD encoder is given blow −

Inputs Outputs

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 0 1 0 0 0 0 1

0 0 0 0 0 0 0 1 0 0 0 0 1 0

0 0 0 0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 0 1 0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0 0 0 0 1 0 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0

0 0 1 0 0 0 0 0 0 0 0 1 1 1

0 1 0 0 0 0 0 0 0 0 1 0 0 0

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1 0 0 0 0 0 0 0 0 0 1 0 0 1

From this truth table, we can write the Boolean expression of the decimal to BCD
encoder as follows.

Y0 = D1 + D3 + D5 + D7 + D9

Y1 = D2 + D3 + D6 + D7

Y2 = D4 + D5 + D6 + D7

Y3 = D8 + D9

The logic circuit of the decimal to BCD encoder can be implemented using four OR
gates which is shown in the following figure −

Applications of Decimal to BCD Encoder

Decimal to BCD encoders find their application in digital clocks and timers, data
processing devices and storage systems, calculators, measuring instruments, display
devices, microprocessors, microcontrollers, embedded systems, etc.

Conclusion
An encoder converts a piece of information in a certain coded format. Encoders are
essential elements in various digital systems such as automation and control systems,
communication systems and storage units, computing and calculating devices,
measuring instruments, data converters, and more.

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In this chapter, we covered the most widely used types of encoders, they are 4 to 2
Encoder, octal to binary encoder, and decimal to BCD encoder.

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Digital Electronics - Families

A logic family is defined as a set of electronic circuit designs that have similar
characteristics in terms of technical parameters such as logic levels, voltage levels,
switching speed, power consumption, noise immunity, etc. The logic families play an
important role in the field of digital electronics and allows to implement various logic
functions and operations.

Depending on the fabrication technology, the logic families can be classified into the
following two types −

Unipolar Logic Family

Bipolar Logic Family

A logic family that utilizes unipolar electronic devices like MOSFETs as their main element
is known as a unipolar logic family. Some examples of unipolar logic families include
PMOS, NMOS, and CMOS.

On the other hand, a bipolar logic family is one that utilizes bipolar electronic devices
such as transistors and diodes. The bipolar logic families can be further classified into the
following types −

Resistor-Transistor Logic (RTL)

Diode Transistor Logic (DTL)

Transistor-Transistor Logic (TTL)

Let us now discuss about each of these logic families in detail.

Resistor-Transistor Logic (RTL)

As the name implies, this logic family utilizes resistors and transistors as their key
elements. In the RTL family, the transistors operate in the cut-off or saturation regions
depending on the input voltage applied to them. The RTL family was one of the earliest
logic families used in the field of digital electronic design.

In short, in the RTL family, the logic circuits are designed using resistors and transistors
only.

For example, the circuit of a two-input resistor-transistor logic NOR gate is shown in the
following figure. Here, A and B are the inputs and Y is the output of the gate.

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The operation of this RTL NOR gate for different input combinations is highlighted in the
following table −

Input A Input B Transistor T1 Transistor T2 Output Y

0 0 Off Off 1

0 1 Off On 0

1 0 On Off 0

1 1 On On 0

Similarly, we can also implement other types of logic gates as well.

Advantages of RTL Family

The following are some key advantages of resistor-transistor logic family −

Electronic circuits designed using RTL logic family are simple in design, as they
consist of a minimum number of resistors and transistors.

Circuits manufactured in RTL family are less expensive. These circuits consume
less amount of power than circuits implemented in other logic families.

Disadvantages of RTL Family

The following are some major drawbacks of resistor-transistor logic families −

RTL circuits have low noise margin. This limitation makes them susceptible to
noise and interference.
These circuits have poor fan-out.

RTL circuits are slower in operation due to high propagation delay.

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RTL family is not suitable for designing complex circuits due to some practical
limitations in terms of design scalability and performance.

Applications of RTL Family

Resistor-Transistor Logic (RTL) family finds some limited applications in the field of digital
electronics. Some common applications of RTL family are listed below −

RTL family is cost-effective and easy to understand and design. For this reason, it is
widely used for educational purposes in labs and classrooms to demonstrate digital
electronic concepts to students.

RTL family is also used to design circuits for low-frequency control applications. Due
to simplicity and ease of implementation, RTL family can be used for prototyping
and experimental purposes.

Diode Transistor Logic (DTL)

In diode-transistor logic (DTL) family, the diodes and transistors are the key elements
combinedly used to implement digital logic functions.

The following example circuit demonstrates the electronic circuit design in DTL family.

It is a two-input NAND gate. Where, A and B are inputs of the NAND gate and Y is the
output of the gate.

The operation of this two-input NAND gate is explained in the following truth table −

Input A Input B Diode D1 Diode D2 Transistor T Output Y

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0 0 Forward biased Forward biased Off 1

0 1 Forward biased Reverse biased Off 1

1 0 Reverse biased Forward biased Off 1

1 1 Reverse biased Reverse biased On 0

We can also implement other types of logic circuits using the diode-transistor logic
family.

Advantages of DTL Family

The following are some key advantages of diode-transistor logic family −

DTL circuits are easy and simple to design and implement, as they consist of
only diodes, transistors, and resistors.
DTL circuits are cost-effective as they use basic electronic components like diodes
and transistors which are generally cheap.
DTL circuits have good noise immunity. Hence, these circuits are relatively less
susceptible to noise and interference than some other types of logic families.
DTL circuits have high fan-out. The power dissipation in DTL circuits is
comparatively low.

Limitations of DTL Family

Apart from the advantages given above, the DTL circuits also have some disadvantages
which are listed below −

DTL family circuits require higher amount of power as compared to other logic
families.
DTL circuits consist of a greater number of elements than other types of logic
families.
DTL circuits have a moderate speed of operation. This is due to high propagation
delay.
DTL circuits are not suitable to design more complex digital circuits due to
increased complexity and size of the circuit.

Applications of DTL Family

The following are some common applications of diode-transistor logic family −

DTL family was popular in early digital computers and other digital systems.

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These days, DTL circuits are mainly used for educational purposes to explain the
implementation of digital logic designs to students.
DTL circuits are used to design custom electronic projects.

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Transistor-Transistor Logic (TTL)

Transistor-Transistor Logic (TTL) is one of the most popular logic family in the field of
digital electronics. In this logic family, the transistor is the key functional element which
is operated as a switch to perform the logical operations.

Let us now understand how we can design a logic circuit in TTL family. The following
figure shows a two-input NAND gate −

Here, A and B are the input terminals and Y is the output terminal. The operation of this
circuit is summarized in the following table.

Input Input Emitter Junction Emitter Junction Transistor T2 Output

A B of Transistor T1 of Transistor T2 and T3 Y

0 0 Forward biased Forward biased Off 1

0 1 Forward biased Reverse biased Off 1

1 0 Reverse biased Forward biased Off 1

1 1 Reverse biased Reverse biased On 0

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In the same manner, we can also design other logic gates in the transistor-transistor
logic (TTL) family.

Advantages of TTL Family

Here are some of the key advantages of TTL family −

TTL circuits have high speeds of operation and hence well-suited to use in high-
speed digital systems.

TTL circuits are standardized to make them compatible with a variety of digital
circuits and systems.

TTL circuits have good noise immunity. Thus, they are suitable to use in noisy
environments.

Disadvantages of TTL Family

Although, TTL circuits have several advantages as listed above. But they also have some
disadvantages which are given below −

TTL circuits consume more power than other types of logic families. This
limitation makes the TTL circuits less energy efficient.

TTL circuits generate significant heat during operation and this is due to high
power consumption. Thus, a proper heat management system is required.

TTL logic levels are relatively strict, requiring specific voltage levels for proper
operation. This can sometimes lead to compatibility issues with other logic families.

TTL circuits have a significant propagation delay that limit their use in certain
high-speed systems.

Applications of TTL Family

Transistor-Transistor Logic (TTL) family are widely used in various applications in the field
of digital electronics. Some of the common applications of TTL family are listed below −

TTL circuits are widely used in digital computers, memory units, CPUs, etc.
TTL circuits are also used in embedded systems for different purposes such as
interfacing with sensors, processing data in real-time applications, and more.
In communication systems, TTL circuits are for signal conditioning, protocol
handling, data processing, etc. TTL circuits are commonly used in a variety of
testing and measuring instruments.

Conclusion

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In conclusion, a logic family is a set of digital circuits that share same technical
parameters such as logic levels, voltage levels, processing speed, etc. In this chapter, we
explained the most commonly used digital logic families viz. RTL, DTL, and TTL, along
with their advantages, disadvantages, and applications.

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Digital Electronics - Flip-Flops

A flip-flop is a sequential digital electronic circuit having two stable states that can be
used to store one bit of binary data. Flip-flops are the fundamental building blocks of all
memory devices.

Types of Flip-Flops

S-R Flip-Flop

J-K Flip-Flop

D Flip-Flop

T Flip-Flop

S-R Flip-Flop
This is the simplest flip-flop circuit. It has a set input (S) and a reset input (R). When in
this circuit when S is set as active, the output Q would be high and the Q' will be low. If
R is set to active then the output Q is low and the Q' is high. Once the outputs are
established, the results of the circuit are maintained until S or R get changed, or the
power is turned off.

Truth Table of S-R Flip-Flop

S R Q State

0 0 0 No Change

0 1 0 Reset

1 0 1 Set

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1 1 X

Characteristics Table of S-R Flip-Flop

S R Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 X

1 1 1 X

Characteristics Equation of S-R Flip-Flop

′
Q(t + 1) = S + R Q(t)

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J-K Flip-Flop
Because of the invalid state corresponding to S=R=1 in the SR flip-flop, there is a need
of another flip-flop. The JK flip-flop operates with only positive or negative clock
transitions. The operation of the JK flip-flop is similar to the SR flip-flop. When the input
J and K are different then the output Q takes the value of J at the next clock edge.

When J and K both are low then NO change occurs at the output. If both J and K are
high, then at the clock edge, the output will toggle from one state to the other.

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Truth Table of JK Flip-Flop

J K Q State

0 0 0 No Change

0 1 0 Reset

1 0 1 Set

1 1 Toggles Toggle

Characteristics Table of JK Flip-Flop

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Characteristics Equation of JK Flip-Flop

′ ′
Q(t + 1) = j k Q(t) + K Q(t)

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D Flip-Flop
In a D flip-flop, the output can only be changed at positive or negative clock transitions,
and when the inputs changed at other times, the output will remain unaffected. The D
flip-flops are generally used for shift-registers and counters. The change in output state
of D flip-flop depends upon the active transition of clock. The output (Q) is same as input
and changes only at active transition of clock

Truth Table of D Flip-Flop

D Q

0 0

1 1

Characteristics Equation of D Flip-Flops

Q(t + 1) = D

T Flip-Flop
A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The T flop is obtained
by connecting the J and K inputs together. The flip-flop has one input terminal and clock
input. These flip-flops are said to be T flip-flops because of their ability to toggle the
input state. Toggle flip-flops are mostly used in counters.

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Truth Table of T Flip-Flop

T Q(t) Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

Characteristics Equation of T Flip-Flop

′ ′
Q(t + 1) = T Q(t) + TQ(t) = T ⊕ Q(t)

Applications of Flip-Flops

Counters
Shift Registers

Storage Registers, etc.

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Digital Electronics - Half Subtractor

In digital electronics, a subtractor is a combinational logic circuit that can perform the
subtraction of two number (binary numbers) and produce the difference between them.
It is a combinational circuit that means its output depends on its present inputs only.
Although, in practice, the subtraction of two binary number is accomplished by taking the
1's or 2's compliment of the subtrahend and adding it to the minuend.

In this way, the subtraction operation of binary numbers can be converted into simple
addition operation which makes hardware construction simple and less expensive. There
are two types of subtractors namely, Half Subtractor and Full Subtractor.

In this article, we will discuss the half subtractor, its basic definition, circuit diagram,
truth table, characteristic equation, etc. So let's begin with the basic definition of half
subtractor.

What is a Half-Subtractor?
A half-subtractor is a combinational logic circuit that have two inputs and two outputs
(i.e. difference and borrow). The half subtractor produces the difference between the two
binary bits at the input and also produces a borrow output (if any). In the subtraction (A-
B), A is called as Minuend bit and B is called as Subtrahend bit. The block diagram
and logic circuit diagram of the half subtractor is shown in Figure-1.

Hence, from the logic circuit diagram, it is clear that a half subtractor can be realized
using an XOR gate together with a NOT gate and an AND gate.

In the half subtractor as shown in figure-1, A and B are the inputs, d and b are the
outputs. Where, d indicates the difference and b indicates the borrow output. The borrow
output (b) is the signal that tells the next stage that a 1 has been borrowed.

Operation of Half Subtractor

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Now, let us understand the operation of the half subtractor circuit. Half subtractor
performs its operation to find the difference of two binary digits according to the rules of
binary subtraction, which are as follows −

The output borrow of b is zero (0) as long as the minuend bit (A) is greater than or equal
to the subtrahend bit (B), i.e. A ≥ B. The output borrow is a 1 when A = 0 and B = 1.

From the logic circuit diagram of the half subtractor, it is clear that the difference bit (d)
is obtained by the XOR operation of the two inputs A and B, and the borrow bit is
obtained by AND operation of the compliment of the minuend (A') with the subtrahend
(B).

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Truth Table of Half Subtractor

The following is the truth table the half-subtractor −

Inputs Outputs

A B D (Difference) B (Borrow)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

K-Map for Half Subtractor

We can use the K-Map (or Karnaugh Map), a method for simplifying Boolean algebra, to
determine equations of the difference bit (d) and the output borrow (b).

The K-Map simplification for half subtractor is shown in Figure-2.

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Characteristic Equation of Half Subtractor

The characteristic equations of the half subtractor, i.e. equations of the difference bit (d)
and the output borrow bit (b) are obtained by following the rules of binary subtraction.
These equations are given as follows −

The difference bit (d) of the half subtractor is given by XORing the two inputs A and B.
Therefore,

′ ′
Dif f erence, d = A ⊕ B = A B + AB

The borrow (b) of the half subtractor is the AND of A’ (compliment of A) and B.
Therefore,

′
Borrow, b = A B

Applications of Half Subtractor

The following are some important applications of half subtractor −

Half subtractor is used in ALU (Arithmetic Logic Unit) of processors.

Half subtractor can also be used in amplifiers to compensate the sound distortion.
It is also used to decrease the force of radio signals or audio signals.

Half subtractor is also used to increase or decrease operators.

Conclusion
From the above discussion, we can conclude that a half subtractor is a combinational
logic circuit that can calculate the difference of two binary digits. A half subtractor can
only be used to subtract the LSB (Least Significant Bit) of the subtrahend from the LSB
of the minuend when one binary number is subtracted from another binary number.

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Digital Electronics - Latches

A latch is an asynchronous sequential circuit whose output changes immediately with the
change in the applied input. A latch is used to store 1 bit information in a digital system,
so it is considered as the most elementary memory element.

In this chapter, we will explain in detail about latches in digital electronics along with
their types and applications.

What is a Latch?
In digital electronics, a latch is an asynchronous sequential circuit that can store 1-bit
information. It is used as the fundamental memory element in digital circuits.

A latch can have two stable states namely, set and reset. The set state is denoted by
the logic 1 and the reset state is represented by the logic 0. Due to these two stable
states, a latch is also known as a bistable-multivibrator. The state of a latch toggles
according to the applied input.

The most important thing to be noted about latches is that they do not have a clock
signal for synchronization. That is why they are called asynchronous sequential circuits.

The logic gates are the fundamental building blocks of latches. Since there is no
synchronization and clock signal used. Hence, the latches operate immediately on the
application of input signals.

Characteristics of Latches
Some key characteristics of latches are explained below −

Latches can store 1-bit of digital information that can be represented using either
logic 0 or logic 1. Thus, the latches are mainly used as memory elements in digital
circuits.

Latches have a feedback mechanism that allows them to maintain their current
state as it is until the next input is applied.

The operation of latches is completely controlled by applied inputs that means the
output of the latches updates based on the change in the input signals.

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Types of Latches
The following are the main types of latches that used in digital circuits and systems −

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SR Latch

JK Latch
D Latch

T Latch

Let us now discuss about each type of latch in detail.

SR Latch
The SR latch is a type of latch which has two input lines designated as S and R. Where, S
represents the Set input and R represents the Reset input. Thus, it is also known as Set-
Reset Latch.

The SR latch has two stable states namely Set state (S) and Reset state (R). The block
diagram of the SR latch is shown in the following figure.

In the case of SR latch, the S input sets the output Q to 1 and Q' to 0. On the other
hand, the R input sets the output Q to 0 and Q' to 1. In case, when both S and R inputs
are high, the latch is said to be in forbidden state.

The complete operation of the SR latch for different input combinations is described in
the following truth table −

Inputs Outputs
Comment
S R Q Q'

0 0 Q Q' No change

0 1 0 1 Reset state

1 0 1 0 Set state

1 1 X X Forbidden state

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The SR latch can be implemented by connecting two NOR gates in a cross-coupled

manner as shown in the following figure.

JK Latch
The JK latch is another type of latch which has two inputs namely, J and K. Here, the
input J is similar to S input and the input K is similar to R input in an SR latch.

The operation of the JK latch is similar to that of the SR latch but it does not have the
forbidden state. Instead, it has a toggle state in which the outputs Q and Q' swap their
states when both inputs J and K are 1.

Therefor, the JK latch is mainly designed to overcome the problem of forbidden state in
the SR latch.

The block diagram of the JK latch is shown in the following figure −

The truth table given below describes the operation of the JK latch for different input
combinations −

Inputs Outputs
Comment
J K Q Q'

0 0 Q Q' No change

0 1 0 1 Reset state

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1 0 1 0 Set state

1 1 Q' Q Toggle state

From this truth table, it is clear that the problem of forbidden state is addressed by
implementing the toggle state.

The logic circuit of the JK latch consists of a combination of two NOR gates and two AND
gates as shown in the following figure.

D Latch
The D Latch, also known as Data latch or transparent latch, is a type of bistable
multivibrator which has two input signals namely, D (Data) input and E (Enable) input.

The output Q of the D latch is same as the input applied at the D input line as long as
the E input is high. When the E input goes low, the output of the D latch is held as it is
until the new input is applied to the D input.

The block diagram of the D latch is shown in the following figure.

The truth table given below explains the operation of the D latch −

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Inputs Outputs
Comment
D E Q Q'

0 0 Q Q' No change

0 1 0 1 Reset state

1 0 Q Q' No change

1 1 1 0 Set state

The logic circuit diagram of the D latch is depicted in the following figure −

T Latch
T latch is a type of latch that toggles its output state (Q) when a logic 1 is applied to its
input line. Hence, it is also known as toggle latch.

The T latch is implemented by connecting the J and K inputs of the JK latch together as
shown in the following block diagram.

The truth table describing the operation of the T latch is shown below −

Input Present State Next State

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T Q Q' Q Q'

0 0 1 0 1

0 1 0 1 0

1 0 1 1 0

1 1 0 0 1

The logic circuit diagram of the T latch is shown in the following figure −

Applications of Latches
The latches find several applications in the field of digital electronics. They are most
elementary storage components used to store one bit of information in digital systems.

Some of the common applications of latches are listed here −

Latches are used as 1-bit memory element in digital systems.

Latches are used to design digital registers which are employed for storage and
manipulation of data in microprocessors and microcontrollers.

Latches are used to design flip-flops which are basically the synchronized latches.
Latches are also used in communication systems for temporary data storage or
buffering purposes.

Conclusion
In this chapter, we explained different types of latches used in digital systems along with
some examples of applications of latches.

In conclusion, a latch is a 1-bit storage device made up of logic gates. It is a type of

asynchronous sequential logic circuit which do not have a clocked signal for

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synchronization.

In digital systems, latches are used to serve some key functions like temporary data
storage, data flow control, etc.

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Digital Electronics - Multiplexers

A digital logic circuit that accepts several data inputs and allows only one of them at a
time to flow through the output is called a multiplexer or MUX. This article is meant for
explaining multiplexer in digital electronics, its block diagram, function, and different
types. So, let us start with the basic introduction of multiplexer

What is a Multiplexer?
As already mentioned, a multiplexer, also referred to as MUX, is a combination logic
circuit that is designed to accept multiple input signals and transfer only one of them
through the output line. In simple words, a multiplexer is a digital logic device that
selects one-out-of-N (N = 2n) input data sources and transmits the selected data to a
single output line.

The multiplexer is also called data selector as it selects one from several. The block
diagram of a typical 2n:1 multiplexer is shown in Figure 1.

In the case of multiplexer, the selection of desired data input to flow through the output
line is controlled with the help of SELECT lines. In the block diagram of mux in Figure 1,
I0, I1,... In-1, i.e., (2n) are the input lines, and "n" be the select lines. These select
lines will determine which input is to be routed to the output.

Hence, the multiplexer works as a multi-position switch whose operation is controlled by

digital signals. These digital control signals are applied to the select lines to determine
which data input will be switched to the output line.

Function of Multiplexer

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Multiplexer is a digital logic device which is used to perform multiplexing of data.

Where, multiplexing simply means sharing of data. Technically, when a particular data is
selected from multiple input data sources and transmitted the selected data to a single
output channel, it is called multiplexing.

There are two types of multiplexing namely, frequency multiplexing and time
multiplexing.

When multiple devices are connected to a single transmission line in a system. At any
point of time, only one device is using the line to transmit data, then this is called time
multiplexing. On the other hand, when multiple devices share a common line to transmit
data but at different frequencies, it is called frequency multiplexing.

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Types of Multiplexers
Based on input data lines and select lines, the multiplexer can be of several types. But,
in this article, we will discuss only the following three types of multiplexers −

2×1 Multiplexer

4×1 Multiplexer

Let us discuss each of these three multiplexers individually.

2×1 Multiplexer
The block diagram of a 2×1 multiplexer is shown in Figure 2. The 2×1 multiplexer is
basic two input multiplexer which has two data input lines designated as I0 and I1, one
data select line denoted by S and one output line denoted by Y. The 2×1 mux is used to
connect two 1-bit data sources to a common designation.

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In the 2×1 multiplexer, the logic level of the digital signal applied to the select line S
determines which data input will pass through the output line. The operation of the 2×1
multiplexer can be understood from the following truth table.

Select Line (S) Output (Y)

0 I0

1 I1

4×1 Multiplexer
4×1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one
output Y. The block diagram of 4×1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines. Truth table of 4×1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as

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′ ′ ′ ′
Y = S1 S0 I0 + S1 S0 I1 + S1 S0 I2 + S1 S0 I3

We can implement this Boolean function using Inverters, AND gates & OR gate. The
circuit diagram of 4×1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can
implement 8×1 Multiplexer and 16×1 multiplexer by following the same procedure.

Implementation of Higher-order Multiplexers

Now, let us implement the following two higher-order Multiplexers using lower-order
Multiplexers.

8×1 Multiplexer
16×1 Multiplexer

8×1 Multiplexer
In this section, let us implement 8×1 Multiplexer using 4×1 Multiplexers and 2×1
Multiplexer. We know that 4×1 Multiplexer has 4 data inputs, 2 selection lines and one
output. Whereas, 8×1 Multiplexer has 8 data inputs, 3 selection lines and one output.

So, we require two 4×1 Multiplexers in first stage in order to get the 8 data inputs.
Since, each 4×1 Multiplexer produces one output, we require a 2×1 Multiplexer in

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second stage by considering the outputs of first stage as inputs and to produce the final
output.

Let the 8×1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0
and one output Y. The Truth table of 8×1 Multiplexer is shown below.

Selection Inputs Output

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

We can implement 8×1 Multiplexer using lower order Multiplexers easily by considering
the above Truth table. The block diagram of 8×1 Multiplexer is shown in the following
figure.

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The same selection lines, s1 & s0 are applied to both 4×1 Multiplexers. The data
inputs of upper 4×1 Multiplexer are I7 to I4 and the data inputs of lower 4×1 Multiplexer
are I3 to I0. Therefore, each 4×1 Multiplexer produces an output based on the values of
selection lines, s1 & s0.

The outputs of first stage 4×1 Multiplexers are applied as inputs of 2×1 Multiplexer that
is present in second stage. The other selection line, s2 is applied to 2×1 Multiplexer.

If s2 is zero, then the output of 2×1 Multiplexer will be one of the 4 inputs I3 to
I0 based on the values of selection lines s1 & s0.

If s2 is one, then the output of 2×1 Multiplexer will be one of the 4 inputs I7 to I4
based on the values of selection lines s1 & s0.

Therefore, the overall combination of two 4×1 Multiplexers and one 2×1 Multiplexer
performs as one 8×1 Multiplexer.

16×1 Multiplexer
In this section, let us implement 16×1 Multiplexer using 8×1 Multiplexers and 2×1
Multiplexer. We know that 8×1 Multiplexer has 8 data inputs, 3 selection lines and one
output. Whereas, 16×1 Multiplexer has 16 data inputs, 4 selection lines and one output.

So, we require two 8×1 Multiplexers in first stage in order to get the 16 data inputs.
Since, each 8×1 Multiplexer produces one output, we require a 2×1 Multiplexer in
second stage by considering the outputs of first stage as inputs and to produce the final
output.

Let the 16×1 Multiplexer has sixteen data inputs I15 to I0, four selection lines s3 to s0
and one output Y. The Truth table of 16×1 Multiplexer is shown below.

Selection Inputs Output

S3 S2 S1 S0 Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

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0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

1 1 1 1 I15

We can implement 16×1 Multiplexer using lower order Multiplexers easily by considering
the above Truth table. The block diagram of 16×1 Multiplexer is shown in the following
figure.

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The same selection lines, s2, s1 & s0 are applied to both 8×1 Multiplexers. The data
inputs of upper 8×1 Multiplexer are I15 to I8 and the data inputs of lower 8×1
Multiplexer are I7 to I0. Therefore, each 8×1 Multiplexer produces an output based on
the values of selection lines, s2, s1 & s0.

The outputs of first stage 8×1 Multiplexers are applied as inputs of 2×1 Multiplexer that
is present in second stage. The other selection line, s3 is applied to 2×1 Multiplexer.

If s3 is zero, then the output of 2×1 Multiplexer will be one of the 8 inputs Is7 to I0
based on the values of selection lines s2, s1 & s0.

If s3 is one, then the output of 2×1 Multiplexer will be one of the 8 inputs I15 to I8
based on the values of selection lines s2, s1 & s0.

Therefore, the overall combination of two 8×1 Multiplexers and one 2×1 Multiplexer
performs as one 16×1 Multiplexer.

Applications of Multiplexers
In digital electronics, multiplexers have numerous applications in almost all types of
digital systems. Some important applications of multiplexers are as follows −

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Data routing and data selection

Parallel to series conversion

Logic function implementation

Generation of waveform, etc.

Conclusion
In this tutorial, we discussed in detail the different types of multiplexers used in digital
electronics along with their functions and applications.

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Digital Electronics - Priority Encoder

In digital electronics, an encoder is a combinational logic circuit which accepts inputs as
decimal digits and alphabetic characters, and produces the outputs as the coded
representation of the inputs. In other words, an electronic combinational circuit that
converts numbers and symbols into their corresponding coded format is called an
encoder. The operation performed by the encoder is called encoding which is a process
of converting familiar numbers and characters into their equivalent codes.

An encoder has 2n input lines and n-output lines. At a time, only one of the 2n input
lines is activated. The coded output of the encoder depends upon the activated input
line. There are several types of encoders available such as "octal to binary encoder",
"decimal to BCD encoder", "keyboard encoders", etc.

What is a Priority Encoder?

In case of an ordinary encoder, one and only one decimal input can be activated at any
given time. But in the case of some practical digital systems, two or more decimal inputs
can unintentionally become active at the same time that might cause a confusion. For
example, on a keyboard, a user presses key 4 before releasing another key 2. In such a
situation, the output will be corresponding to (6)10, instead of being (4)10 or (2)10. This
kind of problems can be solved with the help of priority encoder.

In digital electronics, a combinational logic circuit which produces outputs in response to

only one input among all those that may be activated at the same time is called a
priority encoder. For this, it uses a priority system, and hence it is named so.

One most popular priority system used is based on the relative magnitudes of the inputs.
According to the priority system, the decimal input having largest magnitude among all
the simultaneous inputs is encoded. Hence, as per this priority encoding system, the
priority encoder would encode 4 if both 4 and 2 are active at the same time.

In some practical systems, priority encoders have several inputs which are routinely
active at the same time. In such cases, the primary function of the encoder is to select
the input with the highest priority. This function of the priority encoder is known as
arbitration. For example, in a computer system, multiple input devices are connected,
and several of them may try to supply data to the system at the same time. In this case,
the priority encoder is responsible for enabling that input device which has the highest
priority among all the input devices.

Types of Priority Encoders

Several types of priority encoders are there. Some most important types of priority
encoders are listed and explained below.

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4 Input Priority Encoder

Decimal to BCD Priority Encoder

Octal to Binary Priority Encoder

Let us discuss each type of priority encoder in detail.

4-Input Priority Encoder

The logic circuit of the 4-input priority encoder is shown in Figure-1.

It has three outputs designated by A, B, and V. Where, A and B are the ordinary outputs
and V is the output that acts as a valid bit indicator. This third output V is set to 1 when
one or more inputs are equal to 1. In the case, when all the inputs to the encoder are
equal to 0, there is no any valid input, and thus the output V is set to 0. The other two
outputs, i.e. A and B of the encoder are not determined when V is equal to 0. Therefore,
when, V is equal to 0, the outputs A and B are specified as "don’t care conditions".

The truth table of the 4-input priority encoder is shown below.

Inputs (X = Don’t care) Outputs

I0 I1 I2 I3 A B V

0 0 0 0 X X 0

1 0 0 0 0 0 1

X 1 0 0 0 1 1

X X 1 0 1 0 1

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X X X 1 1 1 1

From this truth table, it can be observed that the higher the subscript number of the
input, the higher the priority of the input. Thus, the input I3 has the highest priority.
Therefore, regardless of the values of other inputs, when the input I3 is equal to 1, the
output for AB is 11, i.e. 3. The input I2 has the next lower priority, and then I1, and
finally I0 has the lowest priority.

We can write the Boolean expression for outputs A, B, and V from the above table as
follows,

¯
A = I3 + I3 I2 = I3 + I2

¯ ¯ ¯
B = I3 + I3 I2 I1 = I3 + I2 I1

And,

V = I3 + I2 + I1 + I0

Hence, the condition for the output V is an OR operation of all the input variables.

Decimal to BCD Priority Encoder

This type of priority encoder performs the function of encoding the decimal digits into 4-
bit BCD (Binary Coded Decimal) outputs. As it is a decimal to BCD priority encoder,
therefore, it produces a BCD corresponding to the decimal digit of highest priority among
all the inputs and ignores all others.

The truth table of the decimal to BCD priority encoder is given below.

Decimal Inputs (X = Don’t care) BCD Outputs

I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A1 A0

1 1 1 1 1 1 1 1 1 1 1 1 1

X X X X X X X X 0 0 1 1 0

X X X X X X X 0 1 0 1 1 1

X X X X X X 0 1 1 1 0 0 0

X X X X X 0 1 1 1 1 0 0 1

X X X X 0 1 1 1 1 1 0 1 0

X X X 0 1 1 1 1 1 1 0 1 1

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X X 0 1 1 1 1 1 1 1 1 0 0

X 0 1 1 1 1 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1 1 1 1 1 0

The truth table of the decimal to BCD priority encoder clearly shows that the magnitudes
of the decimal inputs determine their priorities. If any decimal input is HIGH, it will be
encoded if all other higher value inputs are LOW regardless of the state of all lower value
inputs.

Octal to Binary Priority Encoder

This type of priority encoder is used to perform encoding of octal code into binary code.
Hence, this type priority encoder has eight inputs and three outputs that produce
corresponding binary code as given in the truth table below.

Inputs Outputs

I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 V

0 0 0 0 0 0 0 0 X X X 0

1 0 0 0 0 0 0 0 0 0 0 1

X 1 0 0 0 0 0 0 0 0 1 1

X X 1 0 0 0 0 0 0 1 0 1

X X X 1 0 0 0 0 0 1 1 1

X X X X 1 0 0 0 1 0 0 1

X X X X X 1 0 0 1 0 1 1

X X X X X X 1 0 1 1 0 1

X X X X X X X 1 1 1 1 1

This is all about the priority encoder and its major types in digital electronics.

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Digital Electronics - Sequential Circuits

Digital circuits are classified into two major categories namely, combinational circuits
and sequential circuits. We have already discussed about combinational circuits in the
earlier chapters of this tutorial. This chapter will highlight the details of sequential
circuits.

A sequential circuit is a type of digital logic circuit whose output depends on present
inputs as well as past operation of the circuit. Let us start this section of the tutorial with
a basic introduction to sequential circuits.

What is a Sequential Circuit?

A sequential circuit is a logic circuit that consists of a memory element to store history
of past operation of the circuit. Therefore, the output of a sequential circuit depends on
present inputs as well as past outputs of the circuit.

The block diagram of a typical sequential circuit is shown in the following figure −

Here, it can be seen that a sequential circuit is basically a combination of a

combinational circuit and a memory element. The combinational circuit performs the
logical operations specified, while the memory element records the history of operation
of the circuit. This history is then used to perform various logical operations in future.

The sequential circuits are named so because they use a series of latest and previous
inputs to determine the new output.

Main Components of Sequential Circuit

A sequential circuit consists of several different digital components to process and hold
information in the system. Here are some key components of a sequential circuit
explained −

Logic Gates

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The logic gates like AND, OR, NOT, etc. are used to implement the data processing
mechanism of the sequential circuits. These logic gates are basically interconnected in a
specific manner to implement combinational circuits to perform logical operations on
input data.

Memory Element
In sequential circuits, the memory element is another crucial component that holds
history of circuit operation. Generally, flip-flops are used as the memory element in
sequential circuits.

In sequential circuits, a feedback path is provided between the output and the input that
transfers information from output end to the memory element and from memory
element to the input end.

All these components are interconnected together to design a sequential circuit that can
perform complex operations and store state information in the memory element.

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Types of Sequential Circuits

Based on structure, operation, and applications, the sequential circuits are classified into
the following two types −

Asynchronous Sequential Circuit

Synchronous Sequential Circuit

Let us discuss both of these sequential circuits in detail.

Asynchrnous Sequential Circuit

A type of sequential circuit whose operation does not depend on the clock signals is
known as an asynchronous sequential circuit. This type of sequential circuits
operates using the input pulses that means their state changes with the change in the
input pulses.

The main components of the asynchronous sequential circuits include un-clocked flip
flops and combinational logic circuits. The block diagram of a typical asynchronous
sequential circuit is shown in the following figure.

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From this diagram, it is clear that an asynchronous sequential circuit is similar to a

combinational logic circuit with a feedback mechanism.

Asynchronous sequential circuits are mainly used in applications where the clock signals
are not available or practical to use. For example, in conditions when speed of the task
execution is important.

Asynchronous sequential circuits are relatively difficult to design and sometimes they
produce uncertain output.

The ripple counter is a common example of asynchronous sequential circuit.

Synchronous Sequential Circuit

A synchronous sequential circuit is a type of sequential circuit in which all the memory
elements are synchronized by a common clock signal. Hence, synchronous sequential
circuits take a clock signal along with input signals.

In synchronous sequential circuits, the duration of the output pulse is equivalent to the
duration of the clock pulse applied. Take a look at the block diagram of a typical
synchronous sequential circuit −

In this figure, it can be seen that the memory element of the sequential circuit is
synchronized by a clock signal.

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The major disadvantage of the synchronous sequential circuits is that their operation is
quite slow. This is because, every time the circuit has to wait for a clock pulse for the
operation to take place. However, the most significant advantage of synchronous
sequential circuits is that they have a reliable and predictable operation.

Some common examples of synchronous sequential circuits include counters, registers,

memory units, control units, etc.

Sequential Circuits vs. Combinational Circuits

Given below is a list of some of the main advantages of using sequential circuits over
combinational logic circuits −

Sequential circuits can retain the operation history which is important in various
applications like data storage, feedback control systems, etc.
Sequential circuits exhibit dynamic behavior and can execute complex operation in
real time.
Sequential circuits comprise a feedback mechanism which improves the stability
and optimizes the system performance.
Synchronous sequential circuits use a common clock signal for synchronization that
ensures reliable operation of the circuit.
Sequential circuits can perform more complex operations using simpler circuit
designs than combinational circuits. Hence, their hardware complexity is lesser.

Disadvantages of Sequential Circuits

Sequential circuits do have several disadvantages too. Some of the key disadvantages of
using sequential circuits are listed below −

Sequential circuits have higher propagation delay because the input signal passes
through multiple stages of logic circuits and memory elements.
Sequential circuits are relatively complicated and time taking process to design and
analyze.
Sequential circuits require a proper synchronization and clock distribution to work
as intended.
As compared to combinational circuits, sequential circuits consume relatively more
power due to complex design and use of additional components like clock and
memory element.

Applications of Sequential Circuits

Sequential circuits are used in a wide range of applications in the field of digital
electronics.The following are some common examples of applications of sequential

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circuits −

Sequential circuits are used in digital counters employed in applications like

frequency division, event counting, time keeping, and more.

Sequential circuits are also used in digital memory devices like flip-flops, registers,
etc. to store and retrieve data.

Sequential circuits are used to design control circuits in digital systems.

Sequential circuits play an important role in sequential logic and state-based data
processing operations.
Sequential circuits are also used in automation systems to control the operation of
machines based on predefined logics.
In communication systems, sequential circuits are used to implement
communication protocols and data transmission standards.

Conclusion
Sequential circuits are important components in digital electronic systems. A sequential
circuit is nothing but a combination of combinational logic circuit and a memory element,
where the memory element is connected in a feedback mechanism with the
combinational circuit.

The most important thing to be noted about sequential circuits is that their output is
determined by both present inputs and previous inputs and outputs.

Sequential circuits are used to design complex digital systems that can perform advance
operations like real-time data processing, storage and transmission of data, counting
events, and more.

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Digital Electronics - Shift Registers

Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase
the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such
a group of flip-flop is known as a Register. The n-bit register will consist of n number
of flip-flop and it is capable of storing an n-bit word.

The binary data in a register can be moved within the register from one flip-flop to
another. The registers that allow such data transfers are called as shift registers. There
are four mode of operations of a shift register.

Serial In - Serial Out (SISO) Shift Register

Serial In - Parallel Out (SIPO) Shift Register

Parallel In - Serial Out (PISO) Shift Register

Parallel In - Parallel Out (PIPO) Shift Register

Serial In - Serial Out (SISO) Shift Register

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an
entry of a four bit binary number 1 1 1 1 is made into the register, this number should be
applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected
to serial data input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-
flop i.e. D2 and so on.

Block Diagram

Operation
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the
number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge
of clock, the FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.

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Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock
hits, FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third
negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 =
1110.

Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word
in the register is Q3 Q2 Q1 Q0 = 1111.

Truth Table

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Waveforms

Serial In - Parallel Out (SIPO) Shift Register

In such types of operations, the data is entered serially and taken out in parallel
fashion.
Data is loaded bit by bit. The outputs are disabled as long as the data is loading.

As soon as the data loading gets completed, all the flip-flops contain their
required data, the outputs are enabled so that all the loaded data is made
available over all the output lines at the same time.
4 clock cycles are required to load a four bit word. Hence the speed of operation
of SIPO mode is same as that of SISO mode.

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Block Diagram

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Parallel In - Serial Out (PISO) Shift Register

Data bits are entered in parallel fashion.

The circuit shown below is a four bit parallel input serial output register.
Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.
The binary input word B0, B1, B2, B3 is applied though the same combinational
circuit.
There are two modes in which this circuit can work namely - shift mode or load
mode.

Load Mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they will
pass B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of clock, the
binary input B0, B1, B2, B3 will get loaded into the corresponding flip-flops. Thus parallel
loading takes place.

Shift Mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence
the parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become
active. Therefore the shifting of data from left to right bit by bit on application of clock
pulses. Thus the parallel in serial out operation takes place.

Block Diagram

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Parallel In - Parallel Out (PIPO) Shift Register

In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1,
D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the
input binary bits will be loaded into the flip-flops simultaneously. The loaded bits will
appear simultaneously to the output side. Only clock pulse is essential to load all the
bits.

Block Diagram

Bidirectional Shift Register

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If a binary number is shifted left by one position then it is equivalent to

multiplying the original number by 2. Similarly if a binary number is shifted right
by one position then it is equivalent to dividing the original number by 2.

Hence if we want to use the shift register to multiply and divide the given binary
number, then we should be able to move the data in either left or right direction.

Such a register is called bi-directional register. A four bit bi-directional shift

register is shown in fig.

There are two serial inputs namely the serial right shift data input DR, and the
serial left shift data input DL along with a mode select input (M).

Block Diagram

Operation

Sr.No Condition Operation

If M = 1, then the AND gates 1, 3, 5 and 7 are enabled

whereas the remaining AND gates 2, 4, 6 and 8 will be
With M = 1 −
disabled.
1 Shift right
The data at DR is shifted to right bit by bit from FF-3 to
operation
FF-0 on the application of clock pulses. Thus with M = 1
we get the serial right shift operation.

When the mode control M is connected to 0 then the

AND gates 2, 4, 6 and 8 are enabled while 1, 3, 5 and 7
With M = 0 −
are disabled.
2 Shift left
The data at DL is shifted left bit by bit from FF-0 to FF-3
operation
on the application of clock pulses. Thus with M = 0 we
get the serial right shift operation.

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Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-directional
shift register. A shift register which can shift the data in both directions is called a bi-
directional shift register. Applying the same logic, a shift register which can shift the data
in both directions as well as load it parallely, is known as a universal shift register. The
shift register is capable of performing the following operation −

Parallel Loading
Left Shifting

Right Shifting

The mode control input is connected to logic 1 for parallel loading operation whereas it is
connected to 0 for serial shifting. With mode control pin connected to ground, the
universal shift register acts as a bi-directional register. For serial left operation, the input
is applied to the serial input which goes to AND gate-1 shown in figure. Whereas for the
shift right operation, the serial input is applied to D input.

Block Diagram

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Digital to Analog Converter

A Digital to Analog Converter (DAC) converts a digital input signal into an analog
output signal. The digital signal is represented with a binary code, which is a combination
of bits 0 and 1 while the analog signal is a continuous time function.

This chapter deals with Digital to Analog Converters in detail. The block diagram of DAC
is shown in the following figure −

A Digital to Analog Converter (DAC) consists of a number of binary inputs and a single
output. In general, the number of binary inputs of a DAC will be a power of two.

Types of Digital to Analog Converters

Depending on the construction and structure, there are two types of digital to analog
converters, they are −

Weighted Resistor DAC

R-2R Ladder DAC

The following sections discuss about these two types of DACs in detail.

Weighted Resistor DAC

A weighted resistor DAC produces an analog output, which is almost equal to the digital
(binary) input by using binary weighted resistors in the inverting adder circuit. In short,
a binary weighted resistor DAC is called as weighted resistor DAC.

The circuit diagram of a 3-bit binary weighted resistor DAC is shown in the following
figure −

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Recall that the bits of a binary number can have only one of the two values. i.e., either 0
or 1. Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the Most
Significant Bit (MSB) and Least Significant Bit (LSB) respectively.

The digital switches shown in the above figure will be connected to ground, when the
corresponding input bits are equal to '0'. Similarly, the digital switches shown in the
above figure will be connected to the negative reference voltage, −VR when the
corresponding input bits are equal to '1'.

In the above circuit, the non-inverting input terminal of an op-amp is connected to

ground. That means zero volts is applied at the non-inverting input terminal of op-amp.

According to the virtual short concept, the voltage at the inverting input terminal of op-
amp is same as that of the voltage present at its non-inverting input terminal. So, the
voltage at the inverting input terminal’s node will be zero volts.

The nodal equation at the inverting input terminal’s node is −

0 + VR b2 0 + VR b1 0 + VR b0 0 − V0
+ + + = 0
0 1 2
2 R 2 R 2 R Rf

V0 VR b2 VR b1 VR b0
⇒ = + +
0 1 2
Rf 2 R 2 R 2 R

VR Rf b2 b1 b0
⇒ V0 = ( + + )
0 1 2
R 2 2 2

Substituting, R = 2Rf in the above equation,

VR Rf b2 b1 b0
V0 = ( + + )
0 1 2
2Rf 2 2 2

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VR b2 b1 b0
∴ V0 = ( + + )
0 1 2
2 2 2 2

The above equation represents the output voltage equation of a 3-bit binary weighted
resistor DAC. Since the number of bits are three in the binary (digital) input, we will get
seven possible values of output voltage by varying the binary input from 000 to 111 for a
fixed reference voltage, VR.

We can write the generalized output voltage equation of an N-bit binary weighted
resistor DAC as shown below based on the output voltage equation of a 3-bit binary
weighted resistor DAC.

VR bN−1 bN−2 b0
∴ V0 = ( + + … + )
0 1 N−1
2 2 2 2

Disadvantages of Weighted Resistor DAC

The disadvantages of the binary weighted resistor DAC are as follows −

The difference between the resistance values corresponding to LSB & MSB will
increase as the number of bits present in the digital input increases.
It is difficult to design more accurate resistors as the number of bits present in
the digital input increases.

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R-2R Ladder DAC

The R-2R Ladder DAC overcomes the disadvantages of a binary weighted resistor DAC.
As the name suggests, R-2R Ladder DAC produces an analog output, which is almost
equal to the digital (binary) input by using a R-2R ladder network in the inverting adder
circuit.

The circuit diagram of a 3-bit R-2R Ladder DAC is shown in the following figure −

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Recall that the bits of a binary number can have only one of the two values. i.e., either 0
or 1. Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the Most
Significant Bit (MSB) and Least Significant Bit (LSB) respectively.

The digital switches shown in the above figure will be connected to ground, when the
corresponding input bits are equal to '0'. Similarly, the digital switches shown in above
figure will be connected to the negative reference voltage, −VR when the corresponding
input bits are equal to '1'.

It is difficult to get the generalized output voltage equation of a R-2R Ladder DAC. But
we can find the analog output voltage values of R-2R Ladder DAC for individual binary
input combinations easily.

Advantages of R-2R Ladder DAC

The advantages of a R-2R Ladder DAC are as follows −

R-2R Ladder DAC contains only two values of resistor: R and 2R. So, it is easy to
select and design more accurate resistors.
If a greater number of bits are present in the digital input, then we have to
include required number of R-2R sections additionally.

Due to the above advantages, R-2R Ladder DAC is preferable over binary weighted
resistor DAC.

Important Parameters of DACs

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The following are some key parameters and factors that we must consider while selecting
a digital to analog converter for a specific application −

Resolution
The number of discrete output levels that a digital to analog converter can produce is
known as its resolution. To obtain a smoother and accurate analog output signal, the
resolution of the digital to analog converter must be significantly high. The resolution of
a DAC is typically measured in bits.

Let us understand the importance of resolution of DAC. Consider a DAC that can handle
8-bits, it can represent 28 = 256 discrete output values. On the other hand, if a DAC can
handle 16-bits, then it is able to represent 216 = 65536 discrete output values. Hence,
the DAC with 16-bits can provide a smoother and more accurate representation of the
digital signal in analog format as compared to that the 8-bit DAC can do.

Accuracy
The accuracy of a digital to analog converter is the measure of how closer is the output
analog signal to the input digital signal. The high accuracy of DAC is an essential factor
to produce a highly precise analog output signal.

Power Consumption
This factor provides information about the power consumed by the digital to analog
converter during its operation. Ideally, a digital to analog converter must be power
efficient, so that it can extend the battery life and minimize the operational cost.

Operating Speed
The operating speed of a digital to analog converter represents the rate at which the DAC
converts a digital signal into analog signal. Typically, the speed of a DAC is measured in
samples per second (S/s) or megahertz (MHz).

The operating speed of the digital to analog converter also determines the maximum
frequency of the analog output signal that the DAC can generate accurately.

It is essential that a digital to analog converter used in applications like real-time signal
processing, generation of fast waveforms, high-speed communication, etc. must have a
significantly high-speed.

Noise Performance
The noise performance of a digital to analog converter represents the amount of noise
that can be introduced in the output signal during the conversion process. The unwanted

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noise can affect the signal-to-noise ratio and hence the signal quality. Therefore, we
should minimize the noise as much as possible to obtain a high-quality output analog
signal.

Applications of Digital to Analog Converters

Digital to analog converters are widely used in a variety of applications in the field of
digital electronics. The main function of a digital to analog converter is to convert a
digital signal into analog format.

The following are some common devices and systems in which the digital to analog
converters are used −

Audio amplifiers and playback systems

Video encoder systems

Data acquisition systems

Calibration of testing and measuring instruments

Motor control circuits

Digital signal processors

Telecommunication systems, etc.

Conclusion
Digital to analog converters are used in the field of electronics to provide an interface
between digital input and analog output. In this chapter, we explained in detail about the
types and applications of analog to digital converters.

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Full Adder in Digital Electronics

What is a Full Adder?
A combinational logic circuit that can add two binary digits (bits) and a carry bit, and
produces a sum bit and a carry bit as output is known as a full-adder.

In other words, a combinational circuit which is designed to add three binary digits and
produces two outputs (sum and carry) is known as a full adder. Thus, a full adder circuit
adds three binary digits, where two are the inputs and one is the carry forwarded from
the previous addition. The block diagram and circuit diagram of the full adder are shown
in Figure-1.

Hence, the circuit of the full adder consists of one EX-OR gate, three AND gates and one
OR gate, which are connected together as shown in the full adder circuit in Figure-1.

Operation of Full Adder

Full adder takes three inputs namely A, B, and Cin. Where, A and B are the two binary
digits, and Cin is the carry bit from the previous stage of binary addition. The sum output
of the full adder is obtained by XORing the bits A, B, and Cin. While the carry output bit
(Cout) is obtained using AND and OR operations.

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Truth Table of Full Adder

Truth table is one that indicates the relationship between input and output variables of a
logic circuit and explains the operation of the logic circuit. The following is the truth table

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of the full-adder circuit −

Inputs Outputs

A B Cin S (Sum) Cout (Carry)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Hence, from the truth table, it is clear that the sum output of the full adder is equal to 1
when only 1 input is equal to 1 or when all the inputs are equal to 1. While the carry
output has a carry of 1 if two or three inputs are equal to 1.

K-Map for Full Adder

K-Map (Karnaugh Map) is a tool for simplifying binary complex Boolean algebraic
expressions. The K-Map for full adder is shown in Figure-2.

Characteristic Equations of Full Adder

The characteristic equations of the full adder, i.e. equations of sum (S) and carry output
(Cout) are obtained according to the rules of binary addition. These equations are given
below −

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The sum (S) of the full-adder is the XOR of A, B, and Cin. Therefore,

′ ′ ′ ′ ′ ′
Sum, S = A ⊕ B ⊕ C in = A B C in + A BC + AB C + ABC in
in in

The carry (C) of the half-adder is the AND of A and B. Therefore,

Carry, C = AB + AC in + BC in

Advantages of Full Adder

The following are the important advantages of full adder over half adder −

Full adder provides facility to add the carry from the previous stage.
The power consumed by the full adder is relatively less as compared to half
adder.
Full adder can be easily converted into a half subtractor just by adding a NOT
gate in the circuit.
Full adder produces higher output that half adder.

Full adder is one of the essential part of critic digital circuits like multiplexers.
Full adder performs operation at higher speed.

Applications of Full Adder

The following are the important applications of full adder −

Full adders are used in ALUs (arithmetic logic units) of CPUs of computers.

Full adders are used in calculators.

Full adders also help in carrying out multiplication of binary numbers.

Full adders are also used to realize critic digital circuits like multiplexers.
Full adders are used to generate memory addresses.

Full adders are also used in generation of program counterpoints.

Full adders are also used in GPU (Graphical Processing Unit).

Conclusion
In this tutorial, we discussed all the key concepts related to full adders in digital
electronics. Full adders play an important role in many digital electronic circuits because
a full adder can be used realize several other critical digital circuits.

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Full Adder with NAND Gates

In digital electronics, there are different types of logic circuits used to perform different
kinds of arithmetic operations. One of them is adder. Adder (or Binary Adder) is a
combinational logic circuit that performs the addition of two or more binary numbers and
gives an output sum. There are two types of adders present namely, half adder and
full-adder.

Since, adder are logic circuits, thus they are implemented using different types of digital
logic gates such as OR gate, AND gate, NOT gate, NAND gates, NOR gates, etc. Here,
we will discuss the Full Adder Realization using NAND Gates. But before that let’s
have a look into the basics of full adder.

What is a Full Adder?

A combinational logic circuit that can add two binary digits (bits) and a carry bit, and
produces a sum bit and a carry bit as output is known as a full-adder. In other words, a
combinational circuit which is designed to add three binary digits and produces two
outputs (sum and carry) is known as a full adder. Thus, a full adder circuit adds three
binary digits, where two are the inputs and one is the carry forwarded from the previous
addition. The block diagram of the full adder is shown in Figure-1.

From the block diagram of the full adder, it is clear that it has three inputs namely A, B,
Cin. Where, A and B are the input bits, and Cin is the carry bit from previous stage. It
has two output variables namely sum (S) and carry (Cout).

Truth Table of Full Adder

The following is the truth table of the full-adder circuit −

Inputs Outputs

A B Cin S (Sum) Cout (Carry)

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0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Hence, from the truth table, it is clear that the sum output of the full adder is equal to 1
when only 1 input is equal to 1 or when all the inputs are equal to 1. While the carry
output has a carry of 1 if two or three inputs are equal to 1.

The output equations of the full adder can be obtained from the truth table of the full
adder. These equations are as follows −

Sum Output
′ ′ ′ ′ ′ ′
Sum, S = A B C in + A BC + AB C + ABC in = A ⊕ B ⊕ C in
in in

Carry Output
Carry, C out = AB + AC in + BC in

Now, let us discuss the realization of Full Adder with NAND gates.

Full Adder with NAND Gates

The full adder circuit can be realized using the NAND logic gates as shown in Figure-2.

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From the logic circuit diagram of the full adder using NAND gates, we can see that the
full adder requires 9 NAND gates.

Equation of the sum output for the full adder circuit with NAND gates is obtained as
follows −

¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
S = (A ⊕ B) ⋅ (A ⊕ B) C in ⋅ C in ⋅ (A ⊕ B) C in = A ⊕ B ⊕ C in

Where,

¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯
A ⊕ B = A ⋅ AB ⋅ B ⋅ AB

And equation of the carry output of the full adder circuit with NAND gate is given by,

¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯
C out = C in (A ⊕ B) ⋅ AB = AB + (A ⊕ B) C in

In this way, we may implement the full adder circuit using NAND gates only.

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Full Subtractor in Digital Electronics

What is a Full-Subtractor?
A full-subtractor is a combinational circuit that has three inputs A, B, bin and two
outputs d and b. Where, A is the minuend, B is subtrahend, bin is borrow produced by
the previous stage, d is the difference output and b is the borrow output.

As we know that the half-subtractor can only be used for subtraction of LSB (least
significant bit) of binary numbers. If there is any borrow during the subtraction of the
LSBs of two binary numbers, then it will affect the subtraction of next stages. Therefore,
the subtraction with borrow are performed by a full subtractor.

The block diagram and circuit diagram of a full-subtractor is shown in Figure-1.

Therefore, we can realize the full-subtractor using two XOR gates, two NOT gates, two
AND gates, and one OR gate.

Operation of Full Subtractor

Now, let us understand the operation of the full subtractor. Full subtractor performs its
operation to find the difference of two binary numbers according to the rules of binary
subtraction, which are as follows −

In the case of full subtractor, the 1s and 0s for the output variables (difference and
borrow) are determined from the subtraction of A – B – bin.

From the logic circuit diagram of the full subtractor, it is clear that the difference bit (d)
is obtained by the XOR operation of the two inputs A, B, and bin, and the output borrow
bit (b) is obtained by NOT, AND, and OR operations of variable A, B, and bin.

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Truth Table of Full-Subtractor

The truth table is one that gives relationship between input and output of a logic circuit.
The following is the truth table of the full-subtractor −

Inputs Outputs

A B Bin D (Difference) B (Borrow)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

K-Map for Full Subtractor

We can use the K-Map (or Karnaugh Map), a method for simplifying Boolean algebra, to
determine equations of the difference bit (d) and the output borrow bit (b).

The K-Map simplification for half subtractor is shown in Figure-2.

Characteristic Equations of Full Subtractor

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The characteristic equations of the full subtractor, i.e. equations of the difference (d) and
borrow output (b) are obtained by following the rules of binary subtraction. These
equations are given below −

The difference (d) of the full subtractor is the XOR of A, B, and bin. Therefore,

′ ′ ′ ′ ′ ′
Dif f erence, d = A ⊕ B ⊕ bin = A B bin + AB b + A Bb + ABbin
in in

The borrow (b) of the full subtractor is given by,

From the logic circuit diagram and k-map −

′ ′
Borrow, b = A B + (A ⊕ B) bin

From Truth Table

′ ′ ′ ′ ′
Borrow, b = A B bin + A Bb + A Bbin + ABbin
in

Or

′ ′ ′ ′ ′
′
Borrow, b = A B (bin + b ) + (AB + A B ) bin = A B + (A ⊕ B) bin
in

Applications of Full Subtractor

The following are some important applications of full subtractor −

Full subtractors are used in ALU (Arithmetic Logic Unit) in computers CPUs.

Full subtractors are extensively used to perform arithmetical operations like

subtraction in electronic calculators and many other digital devices.

Full subtractors are used in different microcontrollers for arithmetic subtraction.

They are used in timers and program counters (PC).

Full subtractors are also used in processors to compute addresses, tables, etc.
Full subtractors are also used in DSP (Digital Signal Processing) and networking
based systems.

Conclusion
From the above discussion, we can conclude that a full-subtractor is a combinational
logic circuit that can compute the difference of three binary digits. In a full subtractor,
the borrow (if any) from the previous stage is also used in subtraction operation in the
next stages. Therefore, full subtractors are used to perform subtraction of binary
numbers having any number of digits.

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Half Adder in Digital Electronics

Addition is one of the most basic operations performed by different electronic devices
like computers, calculators, etc. The electronic circuit that performs the addition of two
or more numbers, more specifically binary numbers, is called as adder. Since, the logic
circuits use binary number system to perform the operations, hence the adder is referred
to as binary adder

Depending on the number of bits that the circuit can add, adders (or binary adders) are
of two types −

Half Adder

Full Adder

In this article, we will discuss the half adder, its definition, circuit diagram, truth table,
kmap, characteristic equations, and applications.

What is a Half-Adder?
A combinational logic circuit which is designed to add two binary digits is called as a half
adder. The half adder provides the output along with a carry value (if any). The half
adder circuit is designed by connecting an EX-OR gate and one AND gate. It has two
input terminals and two output terminals for sum and carry. The block diagram and
circuit diagram of a half adder are shown in Figure-1.

From the logic circuit diagram of half adder, it is clear that A and B are the two input bits,
S is the output sum, and C is the output carry bit.

In the case of a half adder, the output of the EX-OR gate is the sum of two bits and the
output of the AND gate is the carry. Although, the carry obtained in one addition will not
be forwarded in the next addition because of this it is known as half adder.

Operation of Half Adder

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Half adder adds two binary digits according to the rules of binary addition. These rules
are as follows −

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 10 (Sum = 0 & Carry = 1)

According to these rules of binary addition, we can see that the first three operations
produce a sum whose length is one digit, whereas in the case of last operation (1 and 1),
the sum consists of two digits. Here, the MSB (most significant bit) of this result is called
a carry (which is 1) and the LSB (least significant bit) is called the sum (which is 0).

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Truth Table of Half Adder

Truth table is one that gives the relationship between inputs and outputs of a logic circuit
and explains the operation of the circuit. The following is the truth table of the half-adder
−

Inputs Outputs

A B S (Sum) C (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

K-Map for Half Adder

We can use the K-Map (Karnaugh Map), a method for simplifying Boolean algebra, to
determine equations of the sum bit (S) and the output carry bit (C) of the half adder
circuit.

The k-map for half adder circuit is shown in Figure-2.

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Characteristic Equations of Half-Adder

The characteristic equations of half adder, i.e., equations of sum (S) and carry (C) are
obtained according to the rules of binary addition. These equations are given below −

The sum (S) of the half-adder is the XOR of A and B. Thus,

′ ′
Sum, S = A ⊕ B = AB + A B

The carry (C) of the half-adder is the AND of A and B. Therefore,

Carry, C = A ⋅ B

Applications of Half Adder

The following are some important applications of half adder −

Half adder is used in ALU (Arithmetic Logic Unit) of computer processors to add
binary bits.

Half adder is used to realize full adder circuit.

Half adder is used in calculators.

Half adder is used to calculate addresses and tables.

Conclusion
From the above discussion, we can conclude that half adders are one of the basic
arithmetic circuits used in different electronic devices to perform addition of two binary
digits. The major drawback of a half adder is that it cannot add the carry obtained from
the addition of the previous stage. To overcome this drawback, full adders are used in
electronic systems.

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Half Adder with NAND Gates

In digital electronics, there are different types of logic circuits used to perform different
kinds of arithmetic operations. One of them is adder. Adder (or Binary Adder) is a
combinational logic circuit that performs the addition of two or more binary numbers and
gives an output sum. There are two types of adders present namely, half and full-adder.

Since, adder are logic circuits, thus they are implemented using different types of digital
logic gates such as OR gate, AND gate, NOT gate, NAND gates, etc. Here, we will discuss
the Half Adder Realization using NAND Gates. But before that let’s have a look into
the basics of half adder.

What is a Half-Adder?
A combinational logic circuit which is designed to add two binary digits is called as a half
adder. The half adder provides the output along with a carry value (if any). The half
adder circuit is designed by connecting an EX-OR gate and one AND gate. It has two
input terminals and two output terminals for sum and carry. The block diagram and
circuit diagram of a half adder are shown in Figure-1.

In the block diagram of the half adder, A and B are the input variables, S is the output
sum bit, and C is the output carry bit.

Truth Table of Half Adder

The following is the truth table of the half-adder −

Inputs Outputs

A B S (Sum) C (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

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1 1 0 1

From the truth table of half adder, we can find the output equations for Sum (S) and
Carry (C) bits. These output equations are given below −

The sum (S) of the half-adder is,

′ ′
Sum, S = AB + A B

The carry (C) of the half-adder is,

Carry, C = A ⋅ B

Half Adder with NAND Gates

We can implement the half adder circuit using NAND gates. The NAND gate is basically a
universal gate, i.e. it can be used for designing any digital circuit. The realization of half
adder with NAND gate is shown in Figure-2.

From the circuit of half adder with NAND gate, it is clear that the minimum of 5 NAND
gates are required to design a half adder circuit.

Here, we can see that the first NAND gate takes the input bits A and B. The output of the
first NAND gate is again given as the input to 3 NAND gates along with the original
inputs. Out of the three NAND gates, 2 NAND gates produce the outputs that are again
given as the input to the NAND gate which is connected at the end of the circuit.

This NAND gate at the end of the circuit gives the sum bit (S). Out of the three NAND
gates at the second stage, the third NAND gate generates the carry bit (C).

The operation of the circuit of half adder with NAND gates can be understood more
clearly with the help of following equations −

′ ′ ′ ′ ′
Sum, S = ((A ⋅ (AB) ) ⋅ (B ⋅ (AB) ) )

′ ′ ′ ′ ′ ′
⇒ Sum, S = ((A ⋅ (AB) ) ) + ((B ⋅ (AB) ) )

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′ ′
⇒ Sum, S = A ⋅ (AB) + B ⋅ (AB)

′ ′ ′ ′
⇒ Sum, S = A ⋅ (A + B ) + B ⋅ (A + B )

′ ′ ′ ′
⇒ Sum, S = AA + AB + A B + BB

′ ′
∴ Sum, S = AB + A B = A ⊕ B

Similarly, the carry bit (C) is given by,

′ ′
Carry, C = ((AB) ) = AB

Hence, in this way we can also realize the half adder in NAND logic.

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Half Subtractor using NAND Gates

In digital electronics, a subtractor is a combinational logic circuit that performs the
subtraction of two binary numbers. However, the subtraction of binary number can be
performed using adder circuits by taking 1’s or 2’s compliments. But, we may also realize
a dedicate circuit to perform the subtraction of two binary numbers.

In the subtraction of two binary numbers, each subtrahend bit of the number is
subtracted from its corresponding significant minuend bit to form a difference bit. During
the subtraction, if the minuend bit is smaller than the subtrahend bit, then a 1 is
borrowed from the next position. Depending upon the number of bits taken as input,
there are two types of subtractors namely, Half Subtractor and Full Subtractor.

A half subtractor is one which takes two binary digits as input and gives a difference bit
and a borrow bit (if any) as output.

On the other hand, a full subtractor is one that takes three bits as input, i.e. two are the
input bits and one is the input borrow bit from the previous stage, and gives a difference
bit and a output borrow bit as the output.

Since a subtractor is a combinational logic circuit, i.e. it is made of logic gates. We can
realize a full adder circuit using different types of logic gates like AND, OR, NOT, NAND,
NOR, etc.

Here, we will discuss the implementation of a half subtractor using NAND gates.
But before that let’s have a look into the basics of the half subtractor.

What is Half Subtractor?

A half-subtractor is a combinational circuit which has two inputs and two outputs
where one output is difference and another is borrow bit. The half subtractor produces
the difference between the two binary bits at the input and also produces a borrow
output (if any). In the subtraction (A-B), A is called as Minuend bit and B is called as
Subtrahend bit. The block diagram of the half subtractor is shown in Figure-1.

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Here, A and B are the input variables (binary digits) and d is the output difference bit
and b is the borrow bit. We can understand the operation of a half subtractor with the
help of its truth table.

Truth Table of Half Subtractor

The following is the truth table the half subtractor −

Inputs Outputs

A B D (Difference) B (Borrow)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Using this truth table, we can determine the output equation of the half subtractor. The
following are the equations of difference bit (d) and borrow bit (b) −

Different Bit (D) −

′ ′
Dif f erence, d = A B + AB = A ⊕ B

Borrow Bit (B)

′
Borrow, b = A B

Now, let us discuss the realization of half subtractor using NAND gates.

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Half Subtractor Using NAND Gates

We may implement the logic circuit of half subtractor using NAND gates only as shown in
figure-2.

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From this logic circuit diagram, we can see that 9 NAND gates are required for realization
of the half subtractor.

The output equations of the half subtractor in NAND logic are as follows −

Difference Bit (D)

¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯
Dif f erence, d = A ⋅ AB ⋅ B ⋅ AB = A ⊕ B

Borrow Bit (B)

¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯ ¯
¯¯¯
Borrow, b = B ⋅ AB = A B

In this way, we can realize the half subtractor using the NAND gates only.

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Implementation of a Full Subtractor using Two

Half Subtractors
A subtractor is a combinational logic circuit that can perform the subtraction of two
numbers (or binary numbers) and produce the difference between them. It is a
combinational logic circuit. Therefore, the output of the subtractor depends only on its
present inputs.

There are two types of subtractors namely,

Half Subtractor

Full Subtractor

Read this tutorial to find out how you can realize a full subtractor using half subtractors.
For the implementation of a full subtractor, we require two half subtractors. Let's start
with a brief overview of half and full subtractors.

What is a Half Subtractor?

A half-subtractor is a combinational logic circuit that has two inputs and two outputs
where one output is difference bit (d) and another is the borrow bit (b). The half
subtractor produces the difference between the two binary bits and also produces a
borrow output (if any). In the subtraction (A-B), A is called Minuend and B is called
Subtrahend bit.

The block diagram and logic circuit diagram of the half subtractor are shown in Figure-1.

From the logic diagram of the half subtractor, it can be seen that a half subtractor can be
realized using an XOR gate together with a NOT gate and an AND gate.

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The difference bit (d) of the half subtractor is given by XORing the two inputs A and B.
Therefore,

′ ′
Dif f erence, d = A ⊕ B = A B + AB

The borrow (b) of the half subtractor is the AND of A' (compliment of A) and B.
Therefore,

′
Borrow, b = A B

What is a Full Subtractor?

A full subtractor is also a combinational logic circuit which has three inputs A, B, bin
and two outputs "d" and "b". Where, "A" is the minuend bit, "B" is the subtrahend bit,
"bin" is borrow produced at the previous stage, d is the output difference bit and b is the
output borrow bit.

The block diagram and circuit diagram of a full-subtractor is shown in Figure-2.

From the logic diagram of the full subtractor, we can see that the implementation of a
fullsubtractor requires two XOR gates, two NOT gates, two AND gates, and one OR gate.

Now, let us discuss the realization of full subtractor using two half subtractors.

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Implementation of a Full Subtractor using Two Half Subtractors

A full subtractor can be realized using two half subtractors. It will take two half-
subtractors and one OR gate. The logic circuit diagram of the full subtractor using two
half subtractors is shown in Figure-3.

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The first half subtractor performs XOR operation on input bits A and B, and AND
operation on A' and B to produce an intermediate borrow bit

The second half subtractor performs the XOR operation on the output of first XOR gate
and the input borrow bit (bin), and the AND gate of the second half circuit gives an
output equal to (A'B + AB')'.bin.

The output of the second XOR gate is the output different bit (d), and the output borrow
bit (b) is obtained by ORing the outputs of two AND gates.

In this way, we can realize a full subtractor by cascading two half subtractors, as shown
in the above figure

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Master-Slave JK Flip Flop

A JK flip flop is a type of 1-bit memory element having inputs namely J and K, one
clock input, and two output specified by Q and Q'. The JK flip flop is an improved version
of SR flip flop which does not have forbidden state. To avoid the forbidden or
indeterminate state, the outputs of the JK flip flop are fed back to its inputs.

However, due to these feedback paths, a new problem is raised in the circuit, which is
called race around condition. Race around condition in the JK flip is a major problem in
which the outputs of flip flop are toggled continuously till the end of applied clock signal.

To avoid the problem of race around condition in JK flip flop, we use the JK flip flop in the
Master and Slave Mode. Hence, the JK flip flop is called Master-Slave Flip Flop.

So, let us start with the basic construction of the master-slave JK flip flop.

What is a Master-Slave JK Flip Flop?

Master Slave JK Flip Flop is a combination of two JK flip flops which are connected in
the cascaded manner as shown in Figure-1.

In this combination of two JK flip flop, one acts as a master flip flop and the other acts
as a slave flip flop. In this master-slave flip flop, the outputs of the master JK flip flop
are connected to the inputs of the slave JK flip flop. The outputs of the slave flip flop are
fed back to the inputs of the master JK flip flop.

In the master-slave JK flip flop, a NOT gate (Inverter) is also used which is connected to
clock signal in a manner that the inverted clock signal is applied to the slave flip flop.

Therefore, when clock signal to master flip flop is 0, then for slave flip flop the clock
signal is 1, and if the clock signal to master flip flop is 1, then for the slave flip flop it 0.

Operation of Master-Slave JK Flip Flop

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When the clock pulse goes to high, the slave flip flop becomes inactive and the inputs J
and K can control the state of the system.

When the clock pulse goes back to low, the information is transferred from master flip
flop to the slave flip flop, and the final output of the system is obtained.

From the circuit, it is clear that the master flip flop is positive level triggered and the
slave flip flop is negative level triggered. Consequently, the master flip flop responds
before the slave flip flop. Now, let us discuss the operation of the master-slave JK flip
flop for different combinations of inputs J and K.

When J = 0 and K = 0, both JK flip flops remains inactive and hence the output Q
remains unchanged. This is called Hold State of the master-slave JK flip flop.
When J = 0 and K = 1, the output Q' of the master flip flop is high and goes to the
input K of the slave flip flop. The clock signal forces the slave flip flop to reset.
Therefore, the slave flip flop has the same output has the master flip flop, i.e., high
Q' and low Q. This is called reset state of the master-slave JK flip flop.
When J = 1 and K = 0, the output Q of the master flip flop is high and goes to the
input J of the slave flip flop, the negative transition of the clock signal sets the slave
flip flop. Hence, this is called the set state of the master-slave JK flip flop.

When J = 1 and K = 1, for this input combination, the master flip flop toggles on
the positive transition of the clock pulse and the slave flip flop toggles on the
negative transition of the clock pulse. Hence, the problem of the race around
condition of the JK flip flop is solved.

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Truth Table of Master-Slave JK Flip Flop

The following is the truth table of the master-slave JK flip flop −

Inputs Output
Comment
J K Qn+1

0 0 Qn No Change

0 1 0 Reset

1 0 1 Set

1 1 Qn' Toggle

This is all about the master-slave JK flip-flop and its operation.

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Memory Devices
Memory is one of the important parts in a computer or any other digital system. It is
used to hold data and programs required for processing and performing tasks.

Memory also affects the performance, efficiency, and speed of the digital system. These
days, semiconductor memories are popular, as they provide a very high-speed operation,
large storage capacity, and compact size.

Here, we will explain the basic to advanced concepts related to semiconductor memory
devices.

What is Memory?
In the field of digital electronics, the memory is a device that is used to store data and
instruction in the digital systems like computers and other microprocessor-based
systems. In modern digital systems, the memory is made up of semiconductor materials
and known as semiconductor memory.

The memory is the device that provides the storage space in computer or any other
digital system where data is to be processed and instructions required for processing are
stored.

The memory is divided into a large number of small parts. Each part is called a memory
cell. Each memory cell or location has a unique address assigned to it which varies from
zero to total memory size minus one.

For example, if a computer has 64 kB memory size, then this memory unit has 64 ×
1024 = 65536 memory location or cells. Hence, the address of these locations ranges
from 0 to 65535.

Classification of Memory
Memory is primarily classified into two types, they are: Internal Memory and External
Memory.

Internal Memory
Internal memory is also known as primary memory, as it is directed connected to the
hardware architecture of the digital system. It is typically installed in the system’s
motherboard in form of ICs.

Examples of internal memory include cache memory, RAM (Random Access Memory),
ROM (Read Only Memory), etc.

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External Memory
External memory is also known as secondary memory. This memory is not directly
connected to the hardware architecture of the systems, instead it is connected through
cables as a peripheral device.

The external memory is primarily used to provide additional storage space to store data
and instructions permanently. Examples of external memory are CD, DVD, HDD, SSD,
USB drives, etc.

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Memory Hierarchy
Memory hierarchy is defined as an arrangement of different types of memory devices
used in a digital system depending on their characteristics, primarily speed and capacity.
The memory hierarchy helps us to select an appropriate memory to use in our system at
a specific level.

A typical memory hierarchy of memory for different memory devices is shown in the
following figure −

Some of key characteristics of this memory hierarchy, when we go from top to bottom −

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Capacity in terms of storage increases.

Cost per bit of storage decreases.

Frequency of access of the memory by the CPU decreases.

Access time by the CPU increases.

Functional Block Diagram of Memory

A memory is basically a group of multiple storage cells having a support circuit to
perform data read/write operations. The following figure depicts the functional block
diagram of a typical memory device −

It consists of the following main parts −

Address Lines

These lines are used to load the address of a specific memory location or cell.

Data Lines
These lines are used to read and write the data from/to the memory cell.

Read and Write Signal (R/W’)

This signal is used to read and write the data from and to the memory cells. When the R
signal is high, the data of the selected cell gets loaded on the data line. When the W’ line
goes low, the data on the data line is loaded into the selected memory cell.

Chip Select Signal (CS’)

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This signal is used to enable or disable the memory chip. It is an active low signal, which
means when this signal goes low, the memory chip is enabled and allow the read and
write operations to execute. Otherwise, the memory chip will be disabled.

Important Terms Related to Memory Operation

The following are some important terms and definitions which are related to the read and
write operations of memory −

Write Cycle Time − The write cycle time is defined as the minimum amount of
time for which a valid cell address is available for data writing operation in the cell.
Typically, it is of the order of 200 ns.
Write Pulse Time − The minimum duration of a write pulse is termed as write
pulse time and it is of the order of 120 ns.
Write Release Time − The minimum time for which the memory address is valid
before the write pulse is known as write release time.
Data Setup Time − The minimum amount of time for which the data remains valid
before the write pulse ends is known as data setup time. Typically, it is around 120
ns.

Data Hold Time − The minimum amount of time for which the data remains valid
after the write pulse ends is known as data hold time.

Read Cycle Time − The minimum amount of time for which a valid memory
address remains available for reading the data from a memory cell is known as read
cycle time. It is typically of the order of 200 ns.
Access Time − The amount of time required to access data from a memory cell is
referred to as access time of the memory. It is also of the order of 200 ns.
Read to Output Active Time − The minimum time that required for enabling the
output buffer after starting of the read pulse is called the read to output active
time. Typically, this time is of the order of 20 ns.

Read to Output Valid Time − The maximum delay time between the beginning of
the read pulse and the availability of the valid data at the data output line is known
as "read to output valid time".

These are some key terms whose knowledge is required to understand the read and
write operations of a memory device.

Characteristics of Memory Devices

In this section, we will focus on studying some key characteristics of memory devices
and their definitions and importance −

Storage Capacity

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This parameter denotes the total memory of the device. It is generally expressed in
terms of number of Bytes that it can store. For example, a memory of 1k × 8 bits can
store 1024 × 8 = 8192 Bytes of digital data.

Unit of Data Transfer

The number of bits that can be read or written in a single read or write cycle is called the
unit of data transfer. In general, the unit of data transfer is equal to the word length or
size of the data bus of the processor.

Modes of Access
It refers to the way in which the data can be read or write to the memory. There are
following three modes used in digital memory devices −

Sequential Access
In this mode, the data is read from or write to the memory in a predefined sequential
manner. In other words, to access the second file, we first access the first file, to access
the third file, firstly access the first and second files, and so on.

Random Access
In this mode, we can directly access any memory location in any order.

Direct Access
This mode is a combination of sequential and random access modes. It is also termed as
semi-random access mode.

Data Transfer Rate

It is defined as the amount of data that is read or write in one second. It is generally
measured in bits per second. Data transfer rate is referred to as bandwidth of memory.

Types of Memory Devices

Some of the important classifications of memory devices used in computers and digital
systems are listed and explained here.

Classification of memory on the basis of nature of data storage −

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Volatile Memory

Non-Volatile Memory

Classification of memory on the basis of access modes −

Sequential Access Memory

Random Access Memory

Now, let us discus all these types of memories in detail along with their subtypes and
characteristics.

Volatile Memory
A type of memory that requires continuous power supply to maintain the stored data is
called a volatile memory. If the power supply to the memory is turned off, the data
stored in it will be lost. Therefore, it is also termed as temporary memory.

Properties of Volatile Memory

The volatile memory loses its stored data when power supply to it is turned off. Volatile
memory has fast operational speed; thus, it can read and write data in a short span of
time.

Volatile memory is used to store data required to be accessed and perform operations.
RAM (Random Access Memory) is an example of volatile memory.

Non-Volatile Memory
A type of memory which can retain stored data even when no power supply is present is
known as non-volatile memory. It is also known as permanent memory and is used for
long-term storage of digital data.

Properties of Non-Volatile Memory

Non-volatile memory stores data permanently. It can retain the stored data even when
the power supply is switched off.

Non-volatile memory is slower than volatile memory. Hence, this memory has longer
read and write cycles.

Examples of non-volatile memory includes ROM (Read Only Memory), magnetic tapes,
optical discs, magnetic discs, USB drives, etc.

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Sequential Access Memory

A type of memory in which the stored data and information is accessed in a predefined
sequential manner is known as a sequential access memory.

Sometimes, it is also known as serial access memory, as the stored data is retrieved
in a serial order.

In a sequential access memory, the system must search the storage device from the
beginning of the memory address until it finds the required piece of data. In other words,
to retrieve the desired data, the system must access all memory addresses until it
reaches the desired data.

Properties of Sequential Access Memory

In a sequential access memory, data retrieval process executes in a sequential manner.
Where, the system starts from beginning of the memory and go sequential through all
memory addresses until the desired data is obtained.

Sequential access memory has slower access speed and longer read/write time. Magnetic
tapes are the examples of sequential access memory.

Random Access Memory

Random access memory, also called as direct access memory, is a type of memory in
which the desired data can be accessed directly, without going through the preceding
data. Hence, this memory allows to access any data in any order.

In other words, the direct access memory or random access memory has the ability to
read from or write to data in any memory location in the same time. Hence, the access
time for all the memory cells is the same and it does not depend on the physical location
of the cell within the memory array.

Properties of Random Access Memory

Random access memory allows data to be accessed in any random order. It provides
high speed data access i.e., fast read and write operations.

All memory locations of the random access memory are directly accessible to the
processing element of the digital system.

Examples of random access memory include RAM, ROM, hard disk, optical disks, and
other semiconductor memories, etc.

Conclusion

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In conclusion, a memory device is an important component in a digital system like

computer used to store data and information.

Different types of memory devices are used for different purposes. For example, a
volatile memory like RAM is used to hold temporary data which are required till the
process is complete.

On the other hand, a non-volatile memory is used to hold data permanently for a longer
period of time. For example, a hard disc is used to store user’s data in the computer
system.

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Multiplexer Design Procedure and Applications

A multiplexer (MUX) is a digital combinational logic circuit that accepts multiple data
inputs and allows only one of them at a time to transmit over an output channel. A
multiplexer consists of 2n input lines, n select lines, and one output line. In a
multiplexer, the routing of the desired data input to the output channel is done by the
logic level applied to the select lines. The functional block diagram of a multiplexer is
shown in Figure-1.

This chapter is primarily meant for explaining the design procedure of different types of
multiplexer circuits. More specifically, here we will discuss the design procedure of the
following three types of multiplexer −

2:1 Multiplexer
4:1 Multiplexer

8:1 Multiplexer

So let us now discuss the designing of each of these three types of multiplexer.

Designing a 2:1 Multiplexer

A 2:1 multiplexer (MUX) is one which has 2 input lines (I0 and I1), 1 select line (S), and
1 output line (Y). The logic level applied to the select line S determines which data input
will pass through the output line.

For determining the Boolean expression for output (Y) of the 2:1 multiplexer and its logic
circuit implementation, we first need its function table (truth table) that gives

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information about operation of the circuit. The function table of the 2:1 multiplexer with
data input I0 and I1 is shown below.

Select Line (S) Output (Y)

0 I0

1 I1

Using this truth table, we can write the logic expression for the output of 2:1 MUX as,

¯
Y = SI0 + SI1

To implement this logic expression, we require two AND gates, one NOT gate, and one
OR gate. The logic circuit of the 2:1 MUX is shown in Figure-2.

Operation
This logic circuit of the 2:1 MUX shown in figure-2 will work as follows −

When S = 0, the AND gate A is enabled and the AND gate B is disabled.
Therefore, the output Y = I0.

When S = 1, the AND gate A is disabled and the AND gate B is enabled.
Therefore, the output Y = I1.

This is how, we can design a 2:1 multiplexer.

Designing a 4:1 Multiplexer

A 4:1 multiplexer (MUX) is the MUX which has 4 input lines (I0, I1, I2, and I3 ), 2 select
line (S0 and S1), and 1 output line (Y). The logic levels applied to the select lines S0 and
S1 determine which data input will transmit to the output line.

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For determining the Boolean expression for output (Y) of the 4:1 multiplexer and its logic
circuitry, we require its function table (truth table) that provides information about the
operation of its circuit. The function table of the 4:1 multiplexer with data inputs I0, I1,
I2, and I3 is given below.

Select Lines
Output(Y)
S1 S0

0 0 I0

0 0 I1

1 0 I2

1 1 I3

Using this truth table, we can write the logic expression for the output of 4:1 MUX as,

¯ ¯ ¯ ¯
Y = S1 S0 I0 + S1 S0 I1 + S1 S0 I2 + S1 S0 I3

To implement this logic expression, we require four AND gates, two NOT gates, and one
OR gate. Thus, the logic circuit of the 4:1 MUX is shown in Figure-3.

Operation
This logic circuit of the 4:1 MUX shown in Figure-3 will work as follows −

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When S1 = 0 and S0 = 0, the AND gate A is enabled, and the AND gates B, C, and
D are disabled. So, the output Y = I0.

When S1 = 0 and S0 = 1, the AND gate B is enabled, and the AND gates A, C, and
D are disabled. So, the output Y = I1.

When S1 = 1 and S0 = 0, the AND gate C is enabled, and the AND gates A, B, and
D are disabled. So, the output Y = I2.

When S1 = 1 and S0 = 1, the AND gate D is enabled, and the AND gates A, B, and
C are disabled. So, the output Y = I3.

In this way, we can design a 4:1 multiplexer.

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Design 8:1 Multiplexer

An 8:1 multiplexer (MUX) is a combination logic circuit which has 8 input lines (I0, I1,
I2, I3, I4, I5, I6, and I7), 3 select line (S0, S1, and S2), and 1 output line (Y). The logic
levels applied to the select lines S0, S1, and S2 determine which data input will transmit
to the output line.

To determine the logic expression for output (Y) of the 8:1 multiplexer and its logic
circuitry, we require its function table (truth table) which provides information about the
operation of its logic circuit.

The function table of the 8:1 multiplexer with data inputs I0, I1, I2, I3, I4, I5, I6, and I7
and select lines, S0, S1, and S2 is given below.

Select Lines
Output (Y)
S2 S1 S0

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

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1 1 0 I6

1 1 1 I7

By using this function table, we can write the logic expression for the output of 8:1 MUX
as,

¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯
Y = S2 S1 S0 I0 + S2 S1 S0 I1 + S2 S1 S0 I2 + S2 S1 S0 I3 + S2 S1 S0 I4 + S2 S1 S0 I5 + S2 S1 S0 I6

+ S2 S1 S0 I7

To implement this logic expression, we require eight AND gates, three NOT gates, and
one OR gate. Therefore, the logic circuit of the 8:1 MUX is shown in Figure-4.

Operation
This logic circuit of the 8:1 MUX shown in Fgure-4 will operate as follows −

When S2 = 0, S1 = 0, and S0 = 0, the AND gate A is enabled, and all the other
AND gates in the logic circuit are disabled. So, the output Y = I0.

When S2 = 0, S1 = 0, and S0 = 1, the AND gate B is enabled, and all the other
AND gates in the logic circuit are disabled. So, the output Y = I1.

When S2 = 0, S1 = 1, and S0 = 0, the AND gate C is enabled, and all the other
AND gates in the logic circuit are disabled. So, the output Y = I2.

When S2 = 0, S1 = 1, and S0 = 1, the AND gate D is enabled, and all the other
AND gates in the logic circuit are disabled. So, the output Y = I3.

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When S2 = 1, S1 = 0, and S0 = 0, the AND gate E is enabled, and all the other
AND gates in the logic circuit are disabled. So, the output Y = I4.

When S2 = 1, S1 = 0, and S0 = 1, the AND gate F is enabled, and all the other
AND gates in the logic circuit are disabled. So, the output Y = I5.

When S2 = 1, S1 = 1, and S0 = 0, the AND gate G is enabled, and all the other
AND gates in the logic circuit are disabled. So, the output Y = I6.

When S2 = 1, S1 = 1, and S0 = 1, the AND gate H is enabled, and all the other
AND gates in the logic circuit are disabled. So, the output Y = I7.

In this way, we can design an 8:1 multiplexer.

Applications of Multiplexers
The multiplexer is one of the widely combinational logic circuits in digital systems. Some
important applications of the multiplexers are listed below.

Multiplexer is used as data selector device.

Multiplexers are used in communication systems to increase the efficiency of the
system.
Multiplexers are used in telephone networks for integration of several audio signals
on a single transmission line.
To maintain large amount of data, multiplexers are also used in computer memory
systems.
Multiplexers are also employed in TV broadcasting systems.

Multiplexers are used in satellite communication and GPS (Global Positioning

System).

Multiplexers are also used in PLC (Programmable Logic Control) systems, etc.

This is all about the multiplexer design procedure, and applications of

multiplexers.

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Parallel Adder and Parallel Subtractor

In digital electronics, adder and subtractor are the two most basic arithmetic
combinational circuits. The adder is a combinational arithmetic circuit used to perform
addition of two or more binary numbers. Whereas, the subtractor is a combination
arithmetic circuit used to perform subtraction of two binary numbers.

Depending on the form in which the addition and subtraction of binary numbers are
executed, the adder and subtractor are classified into following types −

Serial Adder

Parallel Adder

Serial Subtractor
Parallel Subtractor

This tutorial is meant for explaining Parallel Adder and Parallel Subtractor. But before
that let us first discuss the rules of Boolean algebra followed to perform the binary
addition and subtraction.

Binary Addition
The following rules are followed while performing binary addition −

Binary Digit A Binary Digit B Sum (A + B) Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Binary Subtraction
The following rules are to be followed while performing binary subtraction −

Binary Digit A Binary Digit B Difference (A - B) Borrow

0 0 0 0

0 1 1 1

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1 0 1 0

1 1 0 0

Now, let us discuss the parallel adder and parallel subtractor in detail.

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What is Parallel Adder?

A digital circuit that adds two binary numbers of any bit length in parallel form and
produces the sum of those number in parallel form is called a parallel adder.

A parallel adder basically consists of full adders in a chain form as shown in Figure 1.
Here, the output bit of each full adder is connected to the input carry terminal of the
next full adder circuit in the chain.

The parallel adder shown in Figure 1 is a 4-bit parallel adder as it can add two binary
number of 4 bits. Although, we can design a parallel adder circuit for any number of bits
by increasing the number of full adders in the chain.

In the above parallel adder circuit, the bit A is representing the augend bits and B is
representing the addend bits. The first input carry bit to the parallel adder is Cin and the
output carry bit of the parallel adder is C4. The output sum bits are designated by S. We
can also construct a parallel adder in the form of an IC. For example, when the 4-bit
parallel adder is formed in the IC form, then it will have four terminals for augend bits, 4
terminals for addend bits, 4 terminals for sum bits, and 2 terminals for input and output
carry bits.

Working of Parallel Adder

The parallel adder shown in figure-1 performs the binary addition of two numbers as per
the following step −

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Step 1 − Firstly, the full adder circuit FA1 adds the bits A1 and B1 along with the input
carry bit Cin to produce the sum bit S1, where it is the LSB (Least Significant Bit) of the
output sum. At this stage, a carry bit C1 is generated which is transferred to the next full
adder circuit in the chain.

Step 2 − The full adder circuit FA2 adds bits A2 and B2 along with the carry bit C1 from
the previous addition. It produces the sum bit S2 which is the second bit of the output
sum, and a carry bit C2 is also produced which again forwarded to the next full adder
FA3.

Step 3 − The full adder circuit FA3 adds inputs bits A3 and B3 along with the carry bit
C2 from previous addition to produce sum bit S3 and carry bit C3.

Step 4 − The full adder FA4 adds input bits A4 and B4 along with the carry bit C3
forward from FA3. It generates the last sum bit S4 and a last carry bit C4.

Step 5 − The output sum of the parallel adder is then given by,

Sout = C 4 S4 S3 S2 S1

What is Parallel Subtractor?

A digital arithmetic circuit which is used to find the arithmetic difference of two binary
numbers in parallel form is called a parallel subtractor.

We can implement a parallel subtractor in several ways such as combining half

subtractors and full subtractors, all full subtractors, all full adders, etc. Here, we have
realized a 4-bit parallel subtractor using all full adders with subtrahend bit complemented
as shown in Figure 2.

This is the 4-bit parallel subtractor, however, we can implement a parallel subtractor by
adding any number of full adders in the chain of the circuit shown in figure-2.

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The binary subtraction of two binary numbers can be conveniently accomplished by

means of 1's or 2's complement. Where, the complement method converts the
subtraction operation in simple addition operation.

The 2's complement of binary numbers is obtained by taking the 1's complement and
adding 1 to the least significant pair of bits. The 1's complement can be implemented
with the help of a NOT gate (inverter).

Working of Parallel Subtractor

The parallel subtractor shown in above figure-2 carries out the subtraction of two binary
numbers as per the following steps −

Step 1 − Firstly, the 1's complement of bit B1 obtained using an inverter and a 1 (Cin)
are added to obtain the 2's complement of the bit B1. Then, this 2's complemented B1 is
further added to A1. This will produce first bit of the output difference designated by S1,
and a carry bit C1 which is connected to the input carry of the FA2.

Step 2 − The full adder FA2 uses the input carry bit C1 to add with its input bit A2 and
the 2's complement of the input bit B2 to produce the second difference bit (S2) and the
carry bit C2.

Step 3 − The full adder FA3 uses the input carry bit C2 to add with its input bit A3 and
the 2's complement of the input bit B3 to produce the third difference bit (S3) and the
carry bit C3.

Step 4 − Finally, the full adder FA4 uses the carry bit C3 to add with its input bit A4 and
the 2's complement of the input bit B4 to produce the last difference bit (S4) and last
carry bit C4.

Once all the result bits are produced, they are expressed to give the difference of the
two binary numbers as S4S3S2S1 and borrow bit C4.

Conclusion
This is all about parallel adder and parallel subtractor in digital electronics. The most
significant advantage of the parallel adder and subtractor is that they perform the
arithmetic addition and subtraction of two binary numbers faster as compared to the
serial adder and subtractor.

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Programmable Logic Array (PLA)

In this chapter, we will talk about Programmable Logic Array (PLA), its block
diagram, and applications. The programmable logic array (PLA) is a type of
programmable logic device (PLD). Historically, PLA is the first PLD device. It contains an
array/matrix of AND and OR gates whose configuration is done as per the needs of
applications.

In a PLA, a set of fusible links is used to establish or remove the contact of a literal in the
AND operation or contact of a product term in the OR operation. Therefore, a PLA is a
type of PLD that allows both AND matrix and OR matrix to program.

In digital electronics, PLAs are used to design and implement a variety of complex
combinational circuits. However, some PLAs also have a memory element, hence they
can be used to implement sequential circuits as well.

Block Diagram of PLA

A programmable logic array (PLA) is a type of fixed architecture programmable logic
device (PLD) which consists of programmable AND and OR gates. A PLA contains a
programmable AND array which is followed by a programmable OR array.

The block diagram of the PLA is shown in the following figure −

It consists of the following main components −

Input Buffer
The input buffer is used in PLA to avoid the loading effect on the source that drives the
inputs.

AND Array/Matrix
The AND array/matrix is used in PLA to generate the product terms.

OR Array/Matrix

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In a PLA, the OR array/matrix is used to generate the desired output. This is done by
Oring the product terms to produce the sum terms.

Invert/Non-Invert Matrix
It is a buffer used in PLAs to set the output to active-high or active-low.

Output Buffer
This buffer is used at the output side. It is mainly provided to increase the driving
capability of the programmable logic array (PLA).

Combinational Logic Design using PLA

In the field of digital electronics, the PLAs are extensively used for designing
combinational logic circuits. The greatest advantage of designing combinational circuits
using PLAs is that PLA consist of programmable AND and OR arrays which allows to
implement custom desired logic functions.

The step-by-step procedure to design a combinational logic circuit using PLAs is

explained below −

Step 1 − Develop a PLA program table that shows the inputs, product terms, and
outputs.

Step 2 − Design the AND matrix that can generate the desired product terms.

Step 3 − Design the OR matrix that can generate the desired output.

Step 4 − Design the invert/non-invert matrix to set the active-low or active-high output.

Step 5 − Finally, program the PLA by utilizing the PLA program table.

Let us understand this process of combinational circuit design using PLA with the help of
an example.

Example
Design a full-adder circuit using programmable logic array (PLA).

Solution
A full-adder consists of three-inputs and two outputs. Since it has 3 inputs, thus there
are total 8 product terms which are given in the following truth table of the full adder −

Inputs Outputs

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A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

From this truth table, the output sum (S) and the output carry (Cout) are given by,

S = ∑ m(1, 2, 4, 7)

C out = ∑ m(3, 5, 6, 7)

Thus, their Boolean expressions will be,

¯
¯¯¯ ¯
¯¯¯¯¯¯ ¯
¯¯¯ ¯
¯¯¯ ¯
¯¯¯ ¯
¯¯¯¯¯¯
S = A B C in + A B C in + A B C in + A B C in

C out = A B + B C in + A C in

From these two Boolean expressions, we can see that there are seven product terms and
two sum terms. The PLA program table for this full-adder circuit is shown below −

Inputs Outputs
Sr.No Product Terms
A B Cin S Cout

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1 0 1 0 1 -
¯
¯¯¯ ¯
¯¯¯¯¯¯
A B C in

¯
¯¯¯ ¯
2 0 0 1 1 -
¯¯¯
A B C in

3 ¯
¯¯¯ ¯
A B C in
¯¯¯¯¯¯
1 0 0 1 -

4 A B C in 1 1 1 1 -

5 A B 1 1 - - 1

6 B C in - 1 1 - 1

7 A C in 1 - 1 - 1

T T

In this PLA program table, "1" stands for the connection and "-" stands for the absence
of the product term in the output. "T" stands for true and it represents the active-high
output.

The PLA circuit diagram of the full-adder is shown in the following figure.

This example illustrates the complete step-by-step procedure to implement a

combinational logic circuit using PLA.

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Advantages of PLAs

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The following are some key advantages of Programmable Logic Arrays (PLAs) that make
them indispensable in the field of digital electronics −

PLAs provide flexibility in terms of design and implementation of a variety of digital

logic operations. PLAs can be used to implement custom logic functions required to
fulfil the needs of different applications.

PLAs also minimize the time required to design and develop a new digital circuit or
system.

PLAs provide a less expensive way of implementing highly complex digital logic
functions. PLAs eliminate the need of discrete components to implement a logic
function, hence they result in space efficiency.
Since PLAs are programmable, they can be modified on their designs without re-
fabricating the entire circuit.

Disadvantages of PLAs
However, PLAs offer several advantages as discussed above. But they also have some
disadvantages which are listed below −

For a large number of inputs and outputs, PLAs are highly complex to design and
implement. Being a fixed architecture device, PLAs have limited performance in
terms of speed and processing power.

A PLA is generally optimized for a specific application, as it has a fixed number of

AND gates and OR gates. This constraint disallows the designers to implement
highly complex logic functions with the same PLA.
Program a PLA is a time consuming and complex process.

Applications of PLAs
Programmable Logic Arrays (PLAs) are widely used in various applications across
different fields. The following are some common applications of PLAs −

PLAs are used in the field of digital signal processing to implement various logical
functions, such as filtering, convolution, Fourier transformation, etc.

In control systems, PLAs are used to implement control logic functions of various
components like feedback, PID controllers, state machines, etc.

PLAs are used to perform different types of arithmetic operations like addition,
subtraction, multiplication, and division.

PLAs also find their application in the field data compression and encryption
technologies. PLAs are used in digital communication systems and networking
equipment to implement algorithms for protocol handling, packet processing, error
detection and correction, and more.

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PLAs are also used in different measuring instruments such as digital oscilloscopes,
protocol analyzers, logic analyzer, etc.

Conclusion
A PLA is nothing but a kind of digital logic device used to implement complex digital
functions without need of discrete components like AND gates, OR gates, etc. In this
chapter, we explained the basics and applications of programmable logic arrays (PLAs).

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Programmable Logic Devices

Programmable Logic Devices (PLDs) are a collection of integrated circuits which are
configured to perform various logical functions. PLDs play an important role in the field of
engineering and technology, as they form the basis of innovation and support engineers
to develop automated digital systems to improve process flexibility and efficiency. Here,
"programmable" means defining a function that can be performed multiple times without
human intervention.

Programmable Logic Devices (PLDs) are the integrated circuits. They contain an array of
AND gates & another array of OR gates. There are three kinds of PLDs based on the type
of array(s), which has programmable feature.

Programmable Read Only Memory

Programmable Array Logic

Programmable Logic Array

The process of entering the information into these devices is known as programming.
Basically, users can program these devices or ICs electrically in order to implement the
Boolean functions based on the requirement. Here, the term programming refers to
hardware programming but not software programming.

In this chapter, we will explain the basic concepts of programmable logic devices, their
types, advantages, limitations, and applications.

Programmable Read Only Memory (PROM)

Read Only Memory (ROM) is a memory device, which stores the binary information
permanently. That means, we can’t change that stored information by any means later. If
the ROM has programmable feature, then it is called as Programmable ROM (PROM).
The user has the flexibility to program the binary information electrically once by using
PROM programmer.

PROM is a programmable logic device that has fixed AND array & Programmable OR
array. The block diagram of PROM is shown in the following figure.

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Here, the inputs of AND gates are not of programmable type. So, we have to generate
2n product terms by using 2n AND gates having n inputs each. We can implement these
product terms by using nx2n decoder. So, this decoder generates ‘n’ min terms.

Here, the inputs of OR gates are programmable. That means, we can program any
number of required product terms, since all the outputs of AND gates are applied as
inputs to each OR gate. Therefore, the outputs of PROM will be in the form of sum of
min terms.

Example
Let us implement the following Boolean functions using PROM.

A(X, Y, Z) = ∑ m (5, 6, 7)

B(X, Y, Z) = ∑ m (3, 5, 6, 7)

The given two functions are in sum of min terms form and each function is having three
variables X, Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for
producing these two functions. The corresponding PROM is shown in the following
figure.

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Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have
the access of all these min terms. But, only the required min terms are programmed in
order to produce the respective Boolean functions by each OR gate. The symbol ‘X’ is
used for programmable connections.

What is a Programmable Logic Device?

A Programmable Logic Device (PLD) can be defined as an integrated circuit (IC) which
can be programmed to perform specific functions. Here, programming means we can
define a set of instructions that can be executed to perform the functions multiple times
without need of any human intervention.

The primary need of developing PLDs is occurred to implement digital logic functions that
can copy the behavior of conventional logic circuits and replicate it many times. However,
the PLDs are different from normal digital logic circuits in terms of programmability,
which means we can define the desired logic functions by setting a collection of
instructions in the device.

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Types of PLDs
Based on the type of device used, Programmable Logic Devices (PLDs) can be classified
into the following two types −

Bipolar PLDs
CMOS PLDs

Let us discuss each type of programmable logic device in detail.

Bipolar PLDs
Bipolar PLDs are the types of programmable logic devices in which Bipolar Junction
Transistor (BJT) is the main functional device. Bipolar PLDs are the older versions of
programmable logic devices. Thus, they were commonly used before the development of
CMOS PLDs.

The following are some important characteristics of the bipolar programmable logic
devices −

Bipolar PLDs provide fast switching speeds and hence they can operate at higher
frequencies.
Bipolar PLDs are better suited for applications involving rapid signal processing
and require fast response times.

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Bipolar PLDs require more power to operate.

Bipolar PLDs have better immunity to electronic noise and interference.

All these characteristics make the bipolar programmable logic devices well-suited to use
in the applications where high-speed operation and reliability are critical, such as
aerospace, military, and telecommunications systems.

CMOS PLDs
CMOS PLDs stand for Complementary Metal Oxide Semiconductor Programmable Logic
Devices. As their name implies, CMOS PLDs use the CMOS transistors i.e., NMOS (N-
channel Metal Oxide Semiconductor) and PMOS (P-channel Metal Oxide Semiconductor)
transistors as the fundamental component.

CMOS PLDs are basically the modern versions of PLDs and are widely used in modern
digital systems due to their numerous advantages.

Some important characteristics of CMOS PLDs are described below −

CMOS PLDs require very less amount of power to operate. Hence, this
characteristic makes the CMOS PLDs well-suited to use in battery-power devices
where energy efficiency is an important factor.

CMOS PLDs are more reliable and robust. As they are designed to withstand
against various environmental factors like high/low temperatures, voltage
fluctuations, and different radiation interferences.
CMOS PLDs are also excellent in terms of scalability.

CMOS PLDs are newer PLD devices and hence are very commonly used in various
modern electronics devices like consumer electronics, medical equipment, industrial
automation systems, automotive systems.

PLD Programming Languages

In the case of programmable logic devices (PLDs), several different types of Hardware
Description Languages (HDLs) are used to program them. Using these PLD programming
languages, engineers and designers can define the behavior and logical functionality of
the PLD circuit.

Some of the most commonly used PLD programming languages are described here −

VHDL

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VHDL stands for VHSIC Hardware Description Language. It is a standardized hardware

description language used for modelling and simulating digital circuits and systems.
Using VHDL, engineers and developers can specify the structure and functionality of the
digital circuits. VHDL is a best suited programming language for both combinational and
sequential circuits because of its concurrent and sequential descriptions support.

VHDL is one of the most widely used programming language for designing and
verification of highly complex digital circuits and systems like PLDs, ASICs, FPGAs, and
more.

Verilog
Verilog is also a Hardware Description Language (HDL) used for designing and
programming of PLDs. Similar to VHDL, Verilog also supports the concurrent and
sequential descriptions that empower engineers and designers to define the structure
and behavior of digital circuits.

This programming language is most commonly used in semiconductor industries for

designing and programming different kinds of digital systems.

PALASM
PALASM stands for Programmable Array Logic Assembler. It is another Hardware
Description Language (HDL) and Assembler used for programming programmable logic
devices (PLDs). In the case of PALASM, the behavior, logic function, and structure of
PLDs are described using a textual language format. Thus, the developers have to write
PALASM code to describe the desired logic functions and interconnections. After that
these codes are assembled into a format which is suitable for programmable logic
devices.

However, PALASM is an older hardware description language that was very commonly
used in the 1980s and early 1990s for developing PLD-based logic circuits.

ABEL
ABEL stands for Advanced Boolean Expression Language. It is a high-level hardware
description language developed for programming the Programmable Logic Devices
(PLDs).

In ABEL, the logic equations, truth tables, and register transfer level design descriptions
are specified using a clearly readable syntax. Then, the ABEL compiler translates all
these design descriptions into a format suitable for programming the desired PLDs. ABEL
was a very commonly used user-friendly hardware description language in the 1990s.

CUPL

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CUPL stands for Compiler for Universal Programmable Logic. It is another Hardware
Description Language (HDL) and Compiler used for programming different kinds of PLDs.
In this programming language, the logic functions, truth tables, and sequential logic
instructions are specified in the form of simple syntax.

This HDL language was also very popular in the 1990s and early 2000s and was used for
designing PLD based logic circuits.

All these are some important programming languages used to design and program the
programmable logic devices. The languages PALASM, ABEL, and CUPL are mainly in low-
complexity devices. Whereas, VHDL and Verilog are used to program the modern highly-
complex PLDs.

Advantages of Programmable Logic Devices

Programmable Logic Devices (PLDs) have numerous advantages that make them vital
tools in the field of digital system design. Some of the important benefits of
programmable logic devices are listed here −

Programmable logic devices (PLDs) are easy to program and reprogram. Hence,
they provide significant flexibility in terms of designing and implementation of a
variety of logic functions.
PLDs allow for designing custom logic circuits to fulfil the specific requirements of
applications. This can be done by programming the internal logic circuits of the
device.

PLDs can be used in prototyping and testing of digital circuits which help in new
product development at a faster rate. By speeding up the product development
process, PLDs help to reduce the time and cost involved in hardware design.
PLDs provide a fast and cost-effective way of developing medium to complex digital
logic circuits and systems. PLDs help to develop simple, less expensive, and
compact digital systems by integrating a large number of logic functions and
components into a single device.
PLDs also support modern processing techniques like parallel processing, pipeline
processing, etc. This feature helps to achieve high performance by simultaneous
execution of logic functions.

Limitations of Programmable Logic Devices

Programmable Logic Devices (PLDs) offer several advantages as discussed above, but
they also have certain limitations. The following are some of the key limitations of
programmable logic devices −

A programmable logic device can be designed to support a finite number of logic

functions and elements. Thus, the implementation of complex digital circuits may
require multiple devices.

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A PLD typically has a fixed number of input/output (I/O) pins. This limitation can
cause an issue in terms of connectivity and interfacing with external/peripheral
devices.
Programming a PLD requires knowledge of Hardware Description Languages (HDLs)
and design tools. Sometimes PLDs can malfunction due to unintentional
reprogramming or data corruption.

PLDs do not have inherent support for complex arithmetic operations and other
high-level programming operations that are used in general purpose processors.
Therefore, developers have to implement such operations and functionalities
through custom logic designs.

Applications of Programmable Logic Devices

Programmable Logic Devices (PLDs) are used in a wide range of applications across
different fields and industries to design digital logic circuits and implement various logic
functions. Some common applications of programmable logic devices are listed below −

PLDs are widely used in embedded systems to perform different real-time

operations like controlling, interfacing, and processing of data.
In the field of digital signal processing, PLDs are used to design digital filters,
develop modem algorithms, perform signal processing, etc.
PLDs play an important role in communication systems, as they help in
performing various operations like signal routing, data encryption and decryption,
protocol conversion, and more.

In the field of aerospace and defence, PLDs are employed for accomplishing
various critical functions like flight control, operating radar systems, guiding
missiles, encryption of confidential data and more.
PLDs are also used in robotics and industrial automation to control and monitor
the operations of machinery.
In medical equipment, PLDs are used for automated high-speed data processing,
real-time analysis of medical data, patient monitoring, etc.

Conclusion
In conclusion, a programmable logic device is a digital device that can be programmed or
trained to perform a specific logic function. It is primarily used for automation and
efficiency improvement purposes in various applications.

In this chapter, we explained the basics, types, advantages, limitations, and applications
of PLDs. In the upcoming chapter, we will explore different kinds of programmable logic
devices along with their features and characteristics.

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Race-around Condition in JK Flip-flop

Let's start this chapter with a brief introduction of JK flip-flop and its block diagram and
truth table, before moving on to discuss the race-around condition.

JK Flip-Flop
JK flip-flops is a one-bit storage device which has two stable states. The block diagram
representation of a JK flip-flops is shown in Figure-1.

It has two inputs specified by "J" and "K", one clock input for synchronization of the
circuit, and two outputs represented by Q and Q'.

When clock signal is absent, the output of the JK flip-flop is independent of the inputs J
and K. When the clock signal is present, the output of the JK flip-flops changes according
to the inputs J and K.

Truth Table of JK Flip-Flop

The operation of the JK flip-flops can be studied from its truth table which is given as
follows −

Inputs Previous State Output (Next State)

Comment
J K Qn Qn+1

0 0 0 0 No Change

0 0 1 1 No Change

0 1 0 0 Reset

0 1 1 0 Reset

1 0 0 1 Set

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1 0 1 1 Set

1 1 0 1 Toggle

1 1 1 0 Toggle

Now, let us discuss the race-around condition in the JK flip-flops.

Race-around Condition in JK Flip-flops

From the above truth table of the JK flip-flops, it can be observed that when J = 1 and K
=1, then output Qn+1 = Qn', which means for inputs J = 1 and K = 1, the JK flip-flops
acts as a toggle switch.

Let us consider the inputs J = 1 and K = 1, and the output Q = 0. After the propagation
delay (let Δt) of the flip-flops, the output of the JK flip-flops changes from 0 to 1. As we
know, the output of the JK flip-flops is connected to its inputs. Hence, the output also
acts as input, and thus after the next delay (Δt), the output will change from 1 to 0. This
process will continue till the end of the applied clock signal. Thus, the output of the JK
flip-flops is uncertain. This condition of JK flip-flops is called the race-around
condition.

Race-around condition in JK flip-flops is shown in Figure-2, where T is the total duration

of clock pulse.

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How the Race-around Condition Can be Avoided?

The problem of the race-around condition does not exist in the flip-flops where the inputs
do not change during the presence of clock pulse. But, in the case of JK flip-flops, the
inputs change during the clock pulse due to the feedback path present between inputs
and outputs. Hence, in JK flip-flops, the race around condition is a major problem.

The problem of race-around condition and the uncertainty of output can be avoided by
increasing the delay of the flip-flops. For that, the delay of the flip-flops must be greater

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than the duration of the clock signal, i.e. Δt > T. In another way, the duration of the
applied clock signal (T) must be reduced to make it less than the delay of the flip-flops
(Δt).

However, the increase in the delay of the flip-flops is not a good practice because it
decreases the speed of the system. On the other hand, it is also quite difficult to
decrease the duration of the clock pulse (T) beyond the delay of the flip-flops (Δt). This
is because, the delay of the JK flip-flops (Δt) is of the order of nanoseconds.

Hence, the most practical way to solve the problem of race-around condition in JK flip-
flops is to use the JK flip-flops in the Master and Slave Mode. In the master-slave
mode of JK flip-flops, two JK flip-flops are cascaded.

This is all about the race-around condition and its remedies in JK flip-flops.

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RAM and ROM

In the last chapter, we had a discussion on memory devices and their characteristics.
Read this chapter to understand the characteristics of the two most important types of
memories named, RAM (Random Access Memory) and ROM (Read Only Memory) which
are used in digital systems like computer, laptops, smartphones, etc.

What is RAM?
A RAM constitutes the internal memory of the CPU for storing data, program and
program result. It is read/write memory. It is called Random Access Memory (RAM).

Since the access time in RAM is independent of the address to the word that is, each
storage location inside the memory is as easy to reach as other location & takes the
same amount of time. We can reach into the memory at random & extremely fast but
can also be quite expensive.

RAM is a volatile memory i.e., data stored in it is lost when we switch off the computer or
if there is a power failure. Hence, a backup uninterruptible power system (UPS) is often
used with computers. RAM is small, both in terms of its physical size and in the amount
of data it can hold.

Types of RAM
RAM or Random Access Memory is classified into the following two types −

Static RAM (SRAM)

Dynamic RAM (DRAM)

Let’s discuss about these two types of RAMs in detail.

Static RAM (SRAM)

The word "static" indicates that the memory retains its contents as long as power
remains applied. However, data is lost when the power gets down due to volatile nature.
SRAM chips use a matrix of 6-transistors and no capacitors. Transistors do not require
power to prevent leakage, so SRAM need not have to be refreshed on a regular basis.

Because of the extra space in the matrix, SRAM uses more chips than DRAM for the
same amount of storage space, thus making the manufacturing costs higher. Static RAM
is mainly used as cache memory needs to be very fast and small.

Characteristics of SRAM

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The following are some important characteristics of SRAM −

Being a type of RAM, the SRAM is also a volatile memory. Thus, it requires a
continuous power supply to maintain its stored data. If power supply is removed or
switched off, the data stored in the SRAM will delete.
SRAM is a high-speed random access memory. SRAM does not need to be refreshed
to maintain its stored data.
SRAM is made up of semiconductor components called flip-flops which store data.
SRAM has lower storage density. This is mainly because of its complex memory
cell structure. This also results in larger physical size.

SRAM is mostly employed in digital systems in which high-speed data access is

important. For example, it is used as CPU cache memory, high-speed buffers, and
registers in microprocessors and microcontrollers.
SRAM is relatively more expensive. This is mainly because of its lower storage
density and higher manufacturing cost.

Dynamic RAM (DRAM)

DRAM, unlike SRAM, must be continually refreshed in order for it to maintain the data.
This is done by placing the memory on a refresh circuit that rewrites the data several
hundred times per second. DRAM is used for most system memory because it is cheap
and small.

All DRAMs are made up of memory cells. These cells are composed of one capacitor and
one transistor.

Characteristics of DRAM
The important characteristics of DRAM (Dynamic Random Access Memory) are listed
below −

Since DRAM is also a random access memory, hence it is also a volatile memory
and thus requires a continuous power supply to retain its stored data. The data
stored in DRAM is lost, when power supply to is turned off.

In DRAM, the memory cells are made up of capacitors and transistors. Where each
memory cell can store a 1-bit of data in the form electric charge in a capacitor.

In DRAM, to prevent losing stored data due to leakage in capacitor, a refresh circuit
is required for periodic refresh cycles. This is the primary reason the term
"dynamic" is used in DRAM.
For DRAM, the access time is typically of the order in nanoseconds (ns). DRAM is
less expensive than SRAM.

This is all about RAM (Random Access Memory) and its types. Let us now discuss about
another type of memory device called ROM.

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What is ROM?
ROM stands for Read Only Memory. The memory from which we can only read but cannot
write on it. This type of memory is non-volatile. The information is stored permanently in
such memories during manufacture.

A ROM, stores such instruction as are required to start computer when electricity is first
turned on, this operation is referred to as bootstrap. ROM chip are not only used in the
computer but also in other electronic items like washing machine and microwave oven.

Types of ROM
The following are some important types of Read Only Memory (ROM) −

MROM
PROM

EPROM
EEPROM

Let’s discuss these different types of ROMs in detail along with their important
characteristics.

MROM (Masked ROM)

The very first ROMs were hard-wired devices that contained a pre-programmed set of
data or instructions. These kinds of ROMs are known as Masked ROMs. It is inexpensive
ROM.

Since it is a type of ROM, thus it is also a non-volatile memory. The MROMs are
programmed at the time of manufacturing and its data cannot be modified or changed at
a later point of time.

Characteristics of MROM
The following are some important characteristics of MROM −

MROM is a non-volatile memory. Hence, it can retain its data even when power
supply is turned off or removed.
MROM is mainly used for storing permanent software and instructions like firmware,
bootloader code, and other system data essential for system operations.

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In MROM, data and programs are written during the manufacturing process. Once it
is programmed, the stored data cannot be modified or changed. Thus, it is a one-
time programmable memory.

Another important characteristic of MROM, it is a read-only memory. Thus, it

supports read only operations.

MROM is an inexpensive type of read only memory.

The major disadvantage of the MROM is its limited flexibility that means once it
is programmed, the stored data cannot be changed or deleted.

PROM (Programmable Read Only Memory)

PROM is a read-only memory that can be modified only once by a user. The user buys a
blank PROM and enters the desired contents using a PROM programmer.

Inside the PROM chip, there are small fuses which are burnt open during programming.
It can be programmed only once and is not erasable.

Characteristics of PROM
Here are the important characteristics of the programmable read only memory −

PROM also retains its stored data, when the power supply is turned off.
PROM is a programmable memory, but it can be programmed by the user only
once. Then, its stored data cannot be changed, deleted, or rewritten.
In PROM, the memory cells are made by using either fuse-based technology, in
which storing the data involves blowing of tiny fuses.
PROM is also a read only memory, thus it supports read operations only.

Like MROM, PROM also offers limited flexibility, as the data cannot be changed or
erased, once it is programmed.

EPROM (Erasable and Programmable Read Only Memory)

The EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40
minutes. Usually, an EPROM eraser achieves this function.

During programming, an electrical charge is trapped in an insulated gate region. The

charge is retained for more than ten years because the charge has no leakage path. For
erasing this charge, ultra-violet light is passed through a quartz crystal window (lid). This
exposure to ultra-violet light dissipates the charge. During normal use, the quartz lid is
sealed with a sticker.

Characteristics of EPROM

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Some of the key characteristics of EPROM are highlighted below −

EPROM provides a permanent storage for data even in the absence of power supply.
EPROM is an electrically programmable memory. Hence, it can be programmed by
applying specific voltage levels to its write circuit.
EPROM can be erased multiple times by exposing it to UV rays for around 20 to 30
minutes. Then, it can be reprogrammed again.
EPROM chips have a quartz window on its top. This is provided to penetrate the UV
rays to erase the stored data.
EPROM provides the high storage density. Hence, it can hold large amounts of data
in a relatively small physical space.
EPROM is slower to write, that can affect overall performance of the system.

EEPROM (Electrically Erasable and Programmable Read Only

Memory)
The EEPROM is programmed and erased electrically. It can be erased and reprogrammed
about ten thousand times. Both erasing and programming take about 4 to 10 ms
(millisecond).

In EEPROM, any location can be selectively erased and programmed. EEPROMs can be
erased one byte at a time, rather than erasing the entire chip. Hence, the process of re-
programming is flexible but slow.

Characteristics of EEPROM
The important characteristics of electrically erasable programmable read only memory
are highlighted below −

Being a ROM, EEPROM stores data permanently.

EEPROM can be erased and reprogrammed electrically and does not require any
special equipment or UV rays for erasing the stored data.
EEPROM can be erased and reprogrammed multiple times.

EEPROM also provides random data access capabilities. This feature allows for
efficient and fast data manipulation and management.

EEPROM consumes very less power. Hence, it is better suited to use in battery-
powered devices where energy efficiency is important.

EEPROM is a cost effective read only memory device designed use in modern digital
systems.

Conclusion

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In this chapter, we explained the basics RAM and ROM along with their different types
and characteristics.

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Synchronous or Clocked S-R Flip-Flop

In digital electronics, a flip-flop is a most elementary memory element used in several
electronic circuit to store 1-bit information. A flip-flop is a basically a bistable
multivibrator having two stable states.

Flip-flops are made up of an interconnection of logic gates. However, a logic gate itself
does not storage capability, but when several logic gates are arranged in a specific
manner, they can store information. Also, flip-flop is the most fundamental building block
of sequential logic circuits. The block diagram representation of a typical flip-flop is
shown in Figure-1.

A flip-flop has one or more inputs and two outputs, usually represented by Q and Q'
along with a clock input. The clock input is used to trigger the flip-flop so that it can
change states of its outputs.

There are several types of flip-flops such as SR flip-flop, JK flip-flop, D flip-flop, and
T flip-flop. Each type of flip-flop has its unique properties and characteristics needed for
a particular purpose.

Synchronous and Asynchronous Flip-flops

A flip-flop whose logic circuit is clocked/triggered by a clock signal is known as a
synchronous flip-flop. Thus, the output states of the synchronous flip-flop do not
change in the absence of the clock signal, even if its inputs change many times.

On the other hand, an asynchronous flip-flop is one in which there is no clock signal,
hence its output changes instantly on the application of inputs.

Now, let us discuss the clocked or synchronous S-R flip-flop in detail.

What is a Clocked SR Flip-flop?

The type flip-flop which has two inputs namely S (Set) and R (Reset) is termed as an SR
flipflop. If the S and R inputs of the flip-flop control its outputs when a clock pulse is
present (i.e. goes from either low to high or high to low), then it called a clocked SR

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flip-flop. Since, the clock signal synchronizes the operation of the SR flip-flop, hence the
clocked SR flip-flop is also known as synchronous SR flip-flop. The block diagram of a
clocked or synchronous SR flip-flop is shown in Figure-2.

The logic circuit diagram of the clocked or synchronous SR flip-flop is shown in Figure-3
below.

As it can be seen that the circuit consists of four NAND gates. The clock signal is
connected to the NAND gates C and D and the inputs S and R also applied to the NAND
gates C and D. The NAND gates A and B are cross-coupled to form the storage circuit of
the flip-flop.

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Operation of Clocked SR Flip-Flop

The operation of this circuit of clocked SR flip-flop is as described as follows −

When the clock signal is not applied, the SR flip-flop circuit remains inactive, and
there is no change in the outputs of the flip-flop.
When the clock signal is applied, the flip-flop circuit becomes active and operates as
explained below −

When S = 0 and R = 0, the output of NAND gates C and D are S' = 1 and R' =
1. Hence, the outputs of the NAND gates A and B remains unchanged. This is
called Hold State of the SR flip-flop.

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When S = 0 and R = 1, the output of the NAND gates C and D are S' = 1 and
R' = 0, the output of the NAND gate A is 0 and that of NAND gate B is 1. This
is called Reset State of the SR flip-flop.

When S = 1 and R = 0, the output of the NAND gates C and D are S' = 0 and
R' = 1, the output of the NAND gate A is 1 and that of the NAND gate B is 0.
This is called Set State of the SR flip-flop.
When S = 1 and R = 1, the output of the NAND gates C and D are S' = 0 and
R' = 0, the outputs of the both NAND gates A and B try to become 1, which is
not possible. This is called Forbidden State of the SR flip-flop.

Truth Table of Clocked SR Flip-Flop

We can also express the operation of the clocked SR flip-flop in the form of a truth table
as given below. Here, S and R specifies the inputs, Qn specifies the present state of the
output, and Qn+1 specifies the state of the output after change in input and application
of clock pulse.

Inputs Output
Comment
S R Qn Qn+1

0 0 0 0 No Change / Hold

0 0 1 1 No Change / Hold

0 1 0 0 Reset

0 1 1 0 Reset

1 0 0 1 Set

1 0 1 1 Set

1 1 0 X Forbidden

1 1 1 X Forbidden

From this truth table of the clocked SR flip-flop we can directly write the Boolean
expression for its output Qn+1 as follows −

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Hence, the characteristics equation of the SR flip-flop is,

′
Q n+1 = S + R Qn

Applications of Clocked SR Flip-Flop

The clocked SR flip-flops are used in the following applications −

Digital counters
Storage and shift registers

Data storage elements

Data transfer systems

Frequency divider circuits, etc.

Conclusion
A clocked SR flip-flop is a sequential logic circuit used as a 1 bit storage device in digital
systems. It has two inputs S (Set) and R (Reset). When R is high, SR flip-flop is said to
be in reset state; when S is high, SR flip-flop is called in set state; when both inputs S
and R are high, SR flip-flop is said to be in forbidden or invalid state; and when both
inputs S and R are low, SR flip-flop is said to be in no change or hold state.

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What is D Flip Flop?

What is D Flip Flop?
The D flip-flop is a clocked flip-flop with a single digital input 'D'. Each time a D flip-flop
is clocked, its output follows the state of 'D'. The D Flip Flop has only two inputs D and
CP. The D inputs go precisely to the S input and its complement is used to the R input.

Considering the pulse input is at 0, the outputs of gates 3 and 4 are at the 1 level and
the circuit cannot convert state regardless of the value of D. The D input is sampled
when CP = 1. If D is 1, the Q output goes to 1, locating the circuit in the set state. If D is
0, output Q goes to 0, and the circuit switches to a clear state.

Truth Table of D Flip Flop

The truth table for D flip-flop is as shown in the table.

S D QN+1

0 0 0

0 1 1

1 0 0

1 1 1

The logic symbol for the D flip-flop is shown in the figure.

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The D flip flop obtains the destination from its capacity to manage data into its internal
storage. This type of flip-flop is known as a gated D-latch. The CP input is provided given
the destination G (for gate) to denote that this input allows the gated latch to create
applicable data entry into the circuit.

The binary data present at the data input of the D flip flop is changed to the Q output
when the CP input is allowed. The output follows the data input considering the pulse
continues in its 1 state. When the pulse goes to 0, the binary data that was displayed at
the data input at the time the pulse transition appeared is retained at the Q output until
the pulse input is allowed again.

The truth table for the D flip flop is displayed in the table. It demonstrates that the next
state of the flip flop is independent of the current state since QN+1 is similar to input D
whether Q is similar to 0 or 1. This defines that an input pulse will change the value of
input D into the output of the flip flop independent of the value of the output earlier the
pulse was used.

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What is JK Flip Flop?

What is JK Flip Flop?
JK flip-flop can be treated as an alteration of the SR flip-flop. J represents SET, and 'K'
represents CLEAR. In the JK flip-flop, the ‘S’ input is known as the ‘J’ input, and the ‘R’
input is known as the ‘K’ input. The output of the JK flip-flop does not modify if both ‘J’
and ‘K’ are ‘0’. If both the inputs are ‘1’, then the output dial to its free.

The figure shows the circuit diagram of a JK flip-flop.

Truth Table of JK Flip Flop

The truth table of the JK flip-flop is displayed in the table.

S R QN-1

0 0 QN

0 1 0

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1 0 1

1 1 ¯
¯¯¯¯¯¯
QN

The logic symbol for the JK flip-flop is demonstrated in the diagram.

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What is Set-Reset (SR) Flip-flop?

What is Set-Reset (SR) Flip-flop?
Flip flops are an application of logic gates. A flip-flop circuit can stay in a binary state
continually (as long as power is transferred to the circuit) before conducted by an input
signal to switch states. S-R flip-flop represents SET-RESET flip-flops. The SET-RESET flip-
flop includes two NOR gates and also two NAND gates. These flip-flops are also known as
SR Latch.

The SR flip-flop has two inputs such as the ‘Set’ input and a ‘Reset’ input. The two
¯
¯¯¯
outputs of SR flip-flop are the main output Q and its complement Q.

The diagram shows the circuit diagram of an SR flip-flop.

Truth Table of SR Flip Flop

The truth table of SR flip flop is shown in the table.

S R QN.1 ¯
¯¯¯¯¯¯¯¯¯
QN⋅1

0 0 QN ¯
¯¯¯¯¯¯
QN

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0 1 0 1

1 0 1 0

1 1 Indeterminate Indeterminate

A team of cross-coupled NOR gates can describe an SR flip-flop, wherein, the output of
one gate is related to one of the two inputs of the other gate and vice versa. The
complementary input of one NOR gate is ‘R’ while the complementary input of the other
gate is ‘S’.

¯
¯¯¯
The input ‘R’ makes the output Q and the gate with the ‘S’ input makes the output Q.

The logic symbol of the SR flip-flop is shown in the figure.

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What is T Flip Flop?

What is T Flip Flop?
The T flip-flop is also called toggle flip-flop. It is a change of the JK flip-flop. The T flip
flop is received by relating both inputs of a JK flip-flop. The T flip-flop is received by
relating the inputs ‘J’ and ‘K’. When T = 0, both AND gates are disabled. Therefore, there
is no change in the output. When T= 1, the output toggles.

The diagram demonstrates the circuit diagram of a T flip-flop.

Truth Table of T Flip Flop

The truth table of T flip-flop is displayed in the table.

QN T QN+1

0 0 0

0 1 1

1 0 1

1 1 0

The logic symbol of the T flip-flop is shown in the figure.

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