UNIT-2

COMBINATIONAL CIRCUITS
Half Adder in Digital Logic
•
A half adder is a digital logic circuit that performs binary addition of two single-bit
binary numbers. It has two inputs, A and B, and two outputs, SUM and CARRY. The
SUM output is the least significant bit (LSB) of the result, while the CARRY output
is the most significant bit (MSB) of the result, indicating whether there was a carry-
over from the addition of the two inputs. The half adder can be implemented using
basic gates such as XOR and AND gates.
What is Half Adder?
The half adder is a basic building block for more complex adder circuits such as
full adders and multiple-bit adders. It performs binary addition of two single-bit
inputs, A and B, and provides two outputs, SUM and CARRY.
The SUM output is the least significant bit (LSB) of the result, which is the XOR of
the two inputs A and B. The XOR gate implements the addition operation for
binary digits, where a “1” is generated in the SUM output only when one of the
inputs is “1”.
The CARRY output is the most significant bit (MSB) of the result, indicating
whether there was a carry-over from the addition of the two inputs. The CARRY
output is the AND of the two inputs A and B. The AND gate generates a “1” in the
CARRY output only when both inputs are “1”.
Half adder is the simplest of all adder circuits. Half adder is a combinational
arithmetic circuit that adds two numbers and produces a sum bit (s) and carry bit
(c) both as output. The addition of 2 bits is done using a combination circuit called
a Half adder. The input variables are augend and addend bits and output variables
are sum & carry bits. A and B are the two input bits.
let us consider two input bits A and B, then sum bit (s) is the X-OR of A and B. it is
evident from the function of a half adder that it requires one X-OR gate and one
AND gate for its construction.
Truth Table
Here we perform two operations Sum and Carry, thus we need two K-maps one
for each to derive the expression.
Logical Expression
For Sum

Sum = A XOR B
For Carry

Carry = A AND B
Implementation
Note: Half adder has only two inputs and there is no provision to add a carry
coming from the lower order bits when multi addition is performed.
Advantages of Half Adder in Digital Logic
• Simplicity: A half adder is a straightforward circuit that requires a couple of
fundamental parts like XOR AND entryways. It is not difficult to carry out and
can be utilized in numerous advanced frameworks.
• Speed: The half adder works at an extremely rapid, making it reasonable for
use in fast computerized circuits.
Disadvantages of Half Adder in Digital Logic
• Limited Usefulness: The half adder can add two single-piece numbers and
produce a total and a convey bit. It can’t perform expansion of multi-bit
numbers, which requires the utilization of additional intricate circuits like full
adders.
• Lack of Convey Info: The half adder doesn’t have a convey input, which
restricts its value in more mind boggling expansion tasks. A convey input is
important to perform expansion of multi-bit numbers and to chain numerous
adders together.
• Propagation Deferral: The half adder circuit has a proliferation delay, which
is the time it takes for the result to change in light of an adjustment of the info.
This can cause timing issues in computerized circuits, particularly in fast
frameworks.
•

Application of Half Adder in Digital Logic

• Arithmetic circuits: Half adders are utilized in number-crunching circuits to
add double numbers. At the point when different half adders are associated in
a chain, they can add multi-bit double numbers.
• Data handling: Half adders are utilized in information handling applications
like computerized signal handling, information encryption, and blunder
adjustment.
 • Address unraveling: In memory tending to, half adders are utilized in
address deciphering circuits to produce the location of a particular memory
area.
• Encoder and decoder circuits: Half adders are utilized in encoder and
decoder circuits for computerized correspondence frameworks.
• Multiplexers and demultiplexers: Half adders are utilized
in multiplexers and demultiplexers to choose and course information.
• Counters: Half adders are utilized in counters to augment the count by one.

Full Adder in Digital Logic

•
Full Adder is the adder that adds three inputs and produces two outputs. The
first two inputs are A and B and the third input is an input carry as C-IN. The
output carry is designated as C-OUT and the normal output is designated as S
which is SUM. The C-OUT is also known as the majority 1’s detector, whose
output goes high when more than one input is high. A full adder logic is designed
in such a manner that can take eight inputs together to create a byte-wide adder
and cascade the carry bit from one adder to another. we use a full adder because
when a carry-in bit is available, another 1-bit adder must be used since a 1-bit
half-adder does not take a carry-in bit. A 1-bit full adder adds three operands and
generates 2-bit results.
 Full Adder Truth Table:

Logical Expression for SUM: = A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN = C-

IN (A’ B’ + A B) + C-IN’ (A’ B + A B’) = C-IN XOR (A XOR B) = (1,2,4,7)

Logical Expression for C-OUT: = A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN = A

B + B C-IN + A C-IN = (3,5,6,7)
Another form in which C-OUT can be implemented: = A B + A C-IN + B C-IN (A
+ A’) = A B C-IN + A B + A C-IN + A’ B C-IN = A B (1 +C-IN) + A C-IN + A’ B C-IN = A
B + A C-IN + A’ B C-IN = A B + A C-IN (B + B’) + A’ B C-IN = A B C-IN + A B + A B’ C-
IN + A’ B C-IN = A B (C-IN + 1) + A B’ C-IN + A’ B C-IN = A B + A B’ C-IN + A’ B C-IN
= AB + C-IN (A’ B + A B’)
Therefore COUT = AB + C-IN (A EX – OR B)
 Full Adder logic circuit.
Implementation of Full Adder using Half Adders:
2 Half Adders and an OR gate is required to implement a Full Adder.

With this logic circuit, two bits can be added together, taking a carry from the
next lower order of magnitude, and sending a carry to the next higher order of
magnitude.
Implementation of Full Adder using NAND gates:

Implementation of Full Adder using NOR gates:

Total 9 NOR gates are required to implement a Full Adder.

In the logic expression above, one would recognize the logic expressions of a 1-
bit half-adder. A 1-bit full adder can be accomplished by cascading two 1-bit half
adders.

Advantages and Disadvantages of Full Adder in Digital Logic

Advantages of Full Adder in Digital Logic:

1.Flexibility: A full snake can add three information bits, making it more flexible
than a half viper. It can likewise be utilized to add multi-bit numbers by binding
different full adders together.
2.Carry Info: The full viper has a convey input, which permits it to perform
expansion of multi-bit numbers and to chain different adders together.
3.Speed: The full snake works at an extremely fast, making it reasonable for use
in rapid computerized circuits.
Disadvantages of Full Adder in Digital Logic:
1.Complexity: The full snake is more mind boggling than a half viper and
requires more parts like XOR, AND, or potentially entryways. It is likewise more
challenging to execute and plan.
 2.Propagation Deferral: The full viper circuit has a proliferation delay, which is
the time it takes for the result to change in light of an adjustment of the info. This
can cause timing issues in computerized circuits, particularly in fast frameworks.
Application of Full Adder in Digital Logic:
1.Arithmetic circuits: Full adders are utilized in math circuits to add twofold
numbers. At the point when different full adders are associated in a chain, they
can add multi-bit paired numbers.
2.Data handling: Full adders are utilized in information handling applications
like advanced signal handling, information encryption, and mistake rectification.
3.Counters: Full adders are utilized in counters to addition or decrement the
count by one.
4.Multiplexers and demultiplexers: Full adders are utilized in multiplexers
and demultiplexers to choose and course information.
5.Memory tending to: Full adders are utilized in memory addressing circuits to
produce the location of a particular memory area.
6.ALUs: Full adders are a fundamental part of Number juggling Rationale Units
(ALUs) utilized in chip and computerized signal processors.

Half Subtractor in Digital Logic

Last Updated : 30 Jul, 2024

•
A half subtractor is a digital logic circuit that performs binary subtraction of two
single-bit binary numbers. It has two inputs, A and B, and two outputs,
DIFFERENCE and BORROW. The DIFFERENCE output is the difference between
the two input bits, while the BORROW output indicates whether borrowing was
necessary during the subtraction.
The half subtractor can be implemented using basic gates such as XOR and NOT
gates. The DIFFERENCE output is the XOR of the two inputs A and B, while the
BORROW output is the NOT of input A and the AND of inputs A and B.
Half Subtractor
Half subtractor is a combination circuit with two inputs and two outputs that
are different and borrow. It produces the difference between the two binary bits
at the input and also produces an output (Borrow) to indicate if a 1 has been
borrowed. In the subtraction (A-B), A is called a Minuend bit and B is called
a Subtrahend bit.
Truth Table

The SOP form of the Diff and Borrow is as follows:

Diff= A'B+AB'
Borrow = A'B
Implementation
Logical Expression
Difference = A XOR B
Borrow = \overline{A}B
Advantages of Half Adder and Half Subtractor
1. Simplicity: The half adder and half subtractor circuits are simple and easy to
design, implement, and debug compared to other binary arithmetic circuits.
2. Building blocks: The half adder and half subtractor are basic building blocks
that can be used to construct more complex arithmetic circuits, such as full
adders and subtractors, multiple-bit adders and subtractors, and carry look-
ahead adders.
3. Low cost: The half adder and half subtractor circuits use only a few gates,
which reduces the cost and power consumption compared to more complex
circuits.
4. Easy integration: The half adder and half subtractor can be easily integrated
with other digital circuits and systems.
Disadvantages of Half Adder and Half Subtractor
1. Limited functionality: The half adder and half subtractor can only perform
binary addition and subtraction of two single-bit numbers, respectively, and
are not suitable for more complex arithmetic operations.
2. Inefficient for multi-bit numbers: For multi-bit numbers, multiple half
adders or half subtractors need to be cascaded, which increases the
complexity and decreases the efficiency of the circuit.
3. High propagation delay: The propagation delay of the half adder and half
subtractor is higher compared to other arithmetic circuits, which can affect
the overall performance of the system.

Application of Half Subtractor in Digital Logic:

1.Calculators: Most mini-computers utilize advanced rationale circuits to
perform numerical tasks. A Half Subtractor can be utilized in a number cruncher
to deduct two parallel digits from one another.
2.Alarm Frameworks: Many caution frameworks utilize computerized rationale
circuits to identify and answer interlopers. A Half Subtractor can be utilized in
these frameworks to look at the upsides of two parallel pieces and trigger a
caution in the event that they are unique.
3.Automotive Frameworks: Numerous advanced vehicles utilize computerized
rationale circuits to control different capabilities, like the motor administration
framework, stopping mechanism, and theater setup. A Half Subtractor can be
utilized in these frameworks to perform computations and examinations.
4.Security Frameworks: Advanced rationale circuits are usually utilized in
security frameworks to identify and answer dangers. A Half Subtractor can be
utilized in these frameworks to look at two double qualities and trigger a caution
in the event that they are unique.
5.Computer Frameworks: Advanced rationale circuits are utilized broadly in PC
frameworks to perform estimations and examinations. A Half Subtractor can be
utilized in a PC framework to deduct two paired values from one another.

A full subtractor is a combinational circuit that performs subtraction of two bits,

one is minuend and other is subtrahend, taking into account borrow of the
previous adjacent lower minuend bit. This circuit has three inputs and two
outputs. The three inputs A, B and Bin, denote the minuend, subtrahend, and
previous borrow, respectively. The two outputs, D and Bout represent the
difference and output borrow, respectively. Although subtraction is usually
achieved by adding the complement of subtrahend to the minuend, it is of
academic interest to work out the Truth Table and logic realisation of a full
subtractor; x is the minuend; y is the subtrahend; z is the input borrow; D is the
difference; and B denotes the output borrow. The corresponding maps for logic
functions for outputs of the full subtractor namely difference and borrow.
Here’s how a full subtractor works:
1. First, we need to convert the binary numbers to their two’s complement form
if we are subtracting a negative number.
2. Next, we compare the bits in the minuend and subtrahend at the
corresponding positions. If the subtrahend bit is greater than or equal to the
minuend bit, we need to borrow from the previous stage (if there is one) to
subtract the subtrahend bit from the minuend bit.
3. We subtract the two bits along with the borrow-in to get the difference bit. If
the minuend bit is greater than or equal to the subtrahend bit along with the
borrow-in, then the difference bit is 1, otherwise it is 0.
4. We then calculate the borrow-out bit by comparing the minuend and
subtrahend bits. If the minuend bit is less than the subtrahend bit along with the
borrow-in, then we need to borrow for the next stage, so the borrow-out bit is 1,
otherwise it is 0.
The circuit diagram for a full subtractor usually consists of two half-subtractors
and an additional OR gate to calculate the borrow-out bit. The inputs and outputs
of the full subtractor are as follows:
Inputs:
A: minuend bit
B: subtrahend bit
Bin: borrow-in bit from the previous stage
Outputs:
Diff: difference bit
Bout: borrow-out bit for the next stage
Truth Table –
From above table we can draw the K-Map as shown for “difference” and

“borrow”.

Logical expression for difference –

D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= Bin(A’B’ + AB) + Bin’(AB’ + A’B)
= Bin( A XNOR B) + Bin’(A XOR B)
= Bin (A XOR B)’ + Bin’(A XOR B)
= Bin XOR (A XOR B)
= (A XOR B) XOR Bin
Logical expression for borrow –
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= A’B’Bin +A’BBin’ + A’BBin + A’BBin + A’BBin + ABBin
= A’Bin(B + B’) + A’B(Bin + Bin’) + BBin(A + A’)
= A’Bin + A’B + BBin

OR

Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin

= Bin(AB + A’B’) + A’B(Bin + Bin’)
= Bin( A XNOR B) + A’B
= Bin (A XOR B)’ + A’B
Logic Circuit for Full Subtractor –

Implementation of Full Subtractor using Half Subtractors – 2 Half Subtractors and

an OR gate is required to implement a Full Subtractor.
 Carry Look-Ahead Adder
Last Updated : 23 Feb, 2023

•
The adder produce carry propagation delay while performing other arithmetic
operations like multiplication and divisions as it uses several additions or
subtraction steps. This is a major problem for the adder and hence improving the
speed of addition will improve the speed of all other arithmetic operations.
Hence reducing the carry propagation delay of adders is of great importance.
There are different logic design approaches that have been employed to
overcome the carry propagation problem. One widely used approach is to
employ a carry look-ahead which solves this problem by calculating the carry
signals in advance, based on the input signals. This type of adder circuit is called
a carry look-ahead adder.
Here a carry signal will be generated in two cases:
1. Input bits A and B are 1
2. When one of the two bits is 1 and the carry-in is 1.
In ripple carry adders, for each adder block, the two bits that are to be added are
available instantly. However, each adder block waits for the carry to arrive from
its previous block. So, it is not possible to generate the sum and carry of any
block until the input carry is known. The block waits for the block to
produce its carry. So there will be a considerable time delay which is carry
propagation delay.
Consider the above 4-bit ripple carry adder. The sum is produced by the
corresponding full adder as soon as the input signals are applied to it. But the
carry input is not available on its final steady-state value until carry is
available at its steady-state value. Similarly depends on and on .
Therefore, though the carry must propagate to all the stages in order that
output and carry settle their final steady-state value.

The propagation time is equal to the propagation delay of each adder block,
multiplied by the number of adder blocks in the circuit. For example, if each full
adder stage has a propagation delay of 20 nanoseconds, then will reach its
final correct value after 60 (20 × 3) nanoseconds. The situation gets worse, if we
extend the number of stages for adding more number of bits.

Carry Look-ahead Adder :

A carry look-ahead adder reduces the propagation delay by introducing more
complex hardware. In this design, the ripple carry design is suitably transformed
such that the carry logic over fixed groups of bits of the adder is reduced to two-
level logic. Let us discuss the design in detail.
Consider the full adder circuit shown above with corresponding truth table. We
define two variables as ‘carry generate’ and ‘carry propagate’ then,

The sum output and carry output can be expressed in terms of carry
generate and carry propagate as

where produces the carry when both , are 1 regardless of the input
carry. is associated with the propagation of carry from to .
The carry output Boolean function of each stage in a 4 stage carry look-ahead
adder can be expressed as

From the above Boolean equations we can observe that does not have to wait
for and to propagate but actually is propagated at the same time
as and . Since the Boolean expression for each carry output is the sum of
products so these can be implemented with one level of AND gates followed by
an OR gate.

The implementation of three Boolean functions for each carry output ( ,

and ) for a carry look-ahead carry generator shown in below figure.
Time Complexity Analysis :
We could think of a carry look-ahead adder as made up of two “parts”

1. The part that computes the carry for each bit.

2. The part that adds the input bits and the carry for each bit position.

The complexity arises from the part that generates the carry, not the
circuit that adds the bits.
Now, for the generation of the carry bit, we need to perform a AND between
(n+1) inputs. The complexity of the adder comes down to how we perform this
AND operation. If we have AND gates, each with a fan-in (number of inputs
accepted) of k, then we can find the AND of all the bits in time.
This is represented in asymptotic notation as .

Advantages and Disadvantages of Carry Look-Ahead Adder :

 Advantages –

• The propagation delay is reduced.

• It provides the fastest addition logic.

Disadvantages –

• The Carry Look-ahead adder circuit gets complicated as the number of

variables increase.
• The circuit is costlier as it involves more number of hardware.
NOTE :
For n-bit carry lookahead adder to evaluate all the carry bits it requires [n(n +
1)]/2 AND gates and n OR gates.

BCD Adder in Digital Logic

Last Updated : 28 Aug, 2024

•
BCD stands for binary coded decimal. It is used to perform the addition of BCD
numbers. A BCD digit can have any of ten possible four-bit representations.
Suppose, we have two 4-bit numbers A and B. The value of A and B can vary from
0(0000 in binary) to 9(1001 in binary) because we are considering decimal
numbers.
The output will vary from 0 to 18 if we are not considering the carry from the
previous sum. But if we are considering the carry, then the maximum value of
output will be 19 (i.e. 9+9+1 = 19). When we are simply adding A and B, then we
get the binary sum. Here, to get the output in BCD form, we will use BCD Adder.

What is BCD Adder?

A BCD adder is a circuit for the addition of two binary-coded decimal numbers.
BCD is another format used in representing numbers where each digit will be
represented using a 4-bit binary code. In BCD, it is obvious that the most
significant bit (leftmost) is always 0, and therefore each digit will be confined to
the range 0-9.
A BCD adder contains four full-adder circuits in cascade. Each full-adder is
contrived to consider both the two BCD digits being added and a carry-in from the
previous stage. The output of each full-adder produces a sum bit and a carry-out
bit, which becomes the input to the following stage.
When adding BCD numbers, if the sum of two BCD digits is greater than 9, the
result is greater than 1001 in binary and hence is not valid in BCD. A correction
needs to be performed by adding 0110 (6 in BCD) to the sum to get the correct
BCD result.
A BCD adder is, overall, a design capable of correctly adding two BCD numbers and
making all necessary corrections so that the answer is also a valid BCD number.
Steps to Design a BCD Adder
• Find Number of Digits : Find out how many Extended digits of BCD the adder
should support. A BCD digit requires 4 bits.
• Adder Structure : The full adder connected in series could be selected as the
general adder structure. Any extra full-adder shall be incremented by one
BCD digit addition plus a carry from the previous stage.
• Full-Adder Circuit Implementation : Implement a full-adder circuit capable
of adding two 4-bit BCD digits with a carry-in. The full adder shall output a
sum bit and a carry-out bit
• Interconnect the Full-Adders : Now, full-adders are connected in series with
each other; at this point, carry-out from each stage will be given to carry-in of
the next higher order stage.
• Provide BCD Correction : The logic is implemented detecting whether the
sum of two BCD digits is greater than 9. In the case of such, 0110 is added to
the sum, and carry propagates to the next higher order stage.
• Test the BCD Adder : The BCD adder functionality needs to be checked with
the application of different BCD numbers to its input for the correctness of
addition and correction handling.
Example 1:
Input :
A = 0111 B = 1000
Output :
Y = 1 0101
Explanation: We are adding A(=7) and B(=8).
The value of binary sum will be 1111(=15).
But, the BCD sum will be 1 0101,
where 1 is 0001 in binary and 5 is 0101 in binary.
Example 2:
Input :
A = 0101 B = 1001
Output :
Y = 1 0100
Explanation: We are adding A(=5) and B(=9).
The value of binary sum will be 1110(=14).
But, the BCD sum will be 1 0100,
where 1 is 0001 in binary and 4 is 0100 in binary.
Note: If the sum of two numbers is less than or equal to 9, then the value of BCD sum
and binary sum will be same otherwise they will differ by 6(0110 in binary). Now,
lets move to the table and find out the logic when we are going to add “0110”.
We are adding “0110” (=6) only to the second half of the table. The conditions
are:
1. If C’ = 1 (Satisfies 16-19)
2. If S3′.S2′ = 1 (Satisfies 12-15)
3. If S3′.S1′ = 1 (Satisfies 10 and 11)
So, our logic is
C’ + S3′.S2′ + S3′.S1′ = 1

Advantages of BCD Adder

There are various reasons why a BCD adder is beneficial in digital logic.
• Decimal Precision : BCD adders guarantee that when adding decimal
numbers, they do not make mistakes since the process is conducted on digits
that are Binary-Coded Decimal direct (0-9) this rules out any error related to
switching from base 10 to base 2 or vice versa.
• Simplified Decimal Arithmetic : When it comes to decimal arithmetic
operations, BCD adders offer computerized systems with an easier way out
making them fit for fields where calculations are predominantly in decimals
such as, anywhere money is involved – shopping stores or market areas;
calculators; and even real-time clocks.
• Common Display Compatibility : The common display technologies such as
7-segment displays are directly compatible with BCD numbers thus making
BCD adders suitable for applications where output should be displayed
directly in decimal format.
• Mistake Recognition : Just a simple addition is all that is required by such
devices so as to find out the parity of invalid BCDs (for instance those larger
than digit 9), making it easier for FEC systems. In this manner it forms part of
an error detection system and correction scheme that ensure precision
results.
• High-Efficiency Circuit Design : BCD adders facilitate the creation of
efficient, optimized circuits specifically designed for decimal arithmetic,
which results in speedier processing times and less complicated digital
circuits.
These benefits show how critical BCD adders are in processing decimal
arithmetic using digital logic well and correctly.
Disadvantages of BCD Adder
• Memory Misallocation : In comparison to binary digits, the BCD figures take
up more memory to portray comparable values, hence generating greater
memory use within BCD operational systems.
• Restricted Set of Values : BCD adders are constrained to only decimal digits
(0-9) hence cannot carry out direct arithmetic on values that are beyond this
range without extra conversion circuitry thus restricting their versatility in
some applications.
• Lower Speed of Arithmetic Operations : Since they require BCD correction
and manage decimal numbers, BCD adders may have lower operational
speeds than binary ones affecting the overall performance of digital systems.
• Compatibility concerns : BCD arithmetic could be at odds with some
techniques or algorithms especially those that are improved to perform better
in binary arithmetic; hence you get such compatibility problems when using
both types of arithmetics within a system.
• High Circuit Complexity : BCD adders are more complicated than binary
adders owing to BCD correction logic requirements that make sure valid BCD
outputs are produced. This increased complexity can also lead to bigger
circuit sizes as well as more difficult designs.

Parallel Adder and Parallel Subtractor

 Last Updated : 04 Sep, 2024

•
Adding and Subtracting numbers is very simple in digital electronics. To do
this for quickly and efficiently, Most of the for binary numbers (numbers made of
1 and 0), we use circuits like the Parallel Adder and Parallel Subtractor. These
types of circuits can handle more than one bit at a time, making the process
faster.
Binary Addition
Binary addition works sane as a to regular addition, but it only uses two digits: 0
and 1.
0+0=0
0+1=1
1+0=1
1 + 1 = 10 (1 is a carry)
Example
We are working on 13 = 1 1 0 1 and 11 = 1 0 1 1
1 1 0 1 + 1 0 1 1 ──────────── 1 1 0 0 0
So, the final answer is 11000, If we convert in a decimal so answer is 24.
Binary Subtraction
Binary subtraction is a same as regular subtraction, but with binary numbers. We
mostly use a method called 2’s complement to make subtraction simple.
Steps for Binary Subtraction:
Find the 1’s complement of the factor ( You need to do like this 0 to 1 and 1 to
0).
Add 1 in the 1’s complement, and you will get the 2’s complement.
Add the 2’s complement to the minuend.
Example:
Now we are adding 13 and 11
1 1 0 1 – 1 0 1 1 ▔▔▔▔ 0 0 1 0 = 2

How it works
• Find the 1’s complement of 1011: 0100.
• Add 1 to get the 2’s complement: 0101.
• Now, add it to the minuend:
1 1 0 1 + 0 1 0 1 ───── 1 0 0 1 0
At this time we are working on 4 bit numbers, we ignore the carry, so the result
is 0010 (this binary means 2 in decimal).
Parallel Adder
A single full adder performs the addition of two one bit numbers and an input
carry. But a Parallel Adder is a digital circuit capable of finding the
arithmetic sum of two binary numbers that is greater than one bit in length by
operating on corresponding pairs of bits in parallel. It consists of full adders
connected in a chain where the output carry from each full adder is connected to
the carry input of the next higher order full adder in the chain.
A n bit parallel adder requires n full adders to perform the operation.
So for the two-bit number, two adders are needed while for four bit number, four
adders are needed and so on. Parallel adders normally incorporate carry
lookahead logic to ensure that carry propagation between subsequent stages of
addition does not limit addition speed.

Working of Parallel Adder

1. As you can show in the figure, first of all the full adder FA1 add A1 and B1
along with the carry C1 to generate the sum S1 (the first bit of the output
sum) and the carry C2 which is connected to the next adder in chain.
2. Next, the full adder FA2 uses this carry bit C2 to add with the input bits A2
and B2 to generate the sum S2(the second bit of the output sum) and the
carry C3 which is again further connected to the next adder in chain and so
on.
3. The process continues till the last full adder FAn uses the carry bit Cn to add
with its input An and Bn to generate the last bit of the output along last carry
bit Cout.
Parallel Subtractor
A Parallel Subtractor is a digital circuit capable of finding the arithmetic difference
of two binary numbers that is more than one bit in length by operating on pairs of
bits in parallel. The parallel subtractor can be designed in several ways including
combination of half and full subtractors, all full subtractors or all full adders with
the complement of the number being subtracted input.

Working of Parallel Subtractor

1. As shown in the figure, the parallel binary subtractor is formed by
combination of all full adders with subtrahend complement input.
2. This operation considers that the addition of minuend along with the 2’s
complement of the subtrahend is equal to their subtraction.
3. Firstly the 1’s complement of B is obtained by the NOT gate and 1 can be
added through the carry to find out the 2’s complement of B. This is further
added to A to carry out the arithmetic subtraction.
4. The process continues till the last full adder FAn uses the carry bit Cn to add
with its input An and 2’s complement of Bn to generate the last bit of the
output along last carry bit Cout.
Advantages of parallel Adder/Subtractor
1. The parallel adder/subtractor performs the addition operation faster as
compared to serial adder/subtractor.
2. Time required for addition does not depend on the number of bits.
3. The output is in parallel form i.e all the bits are added/subtracted at the same
time.
4. It is less costly.
Disadvantages of parallel Adder/Subtractor
1. Each adder has to wait for the carry to come from the previous adder in the
chain.
2. The propagation delay( delay associated with the travelling of carry bit) is
found to increase with the increase in the number of bits to be added.
Conclusion
Parallel Adders and Parallel Subtractors are special circuits used in digital
electronics to add and subtract binary numbers faster. They are faster because
they handle multiple bits at the same time. While they have some advantages, like
speed, they also have control, such as the delay caused by carrying bits from one
adder to another adder.

Multiplexers in Digital Logic

What Are Multiplexers?

A multiplexer is a combinational circuit that has many data inputs and a single
output, depending on control or select inputs. For N input lines, log2(N) selection
lines are required, or equivalently, for 2n2n input lines, n selection lines are
needed. Multiplexers are also known as “N-to-1 selectors,” parallel-to-serial
converters, many-to-one circuits, and universal logic circuits. They are mainly
used to increase the amount of data that can be sent over a network within a
certain amount of time and bandwidth .

Types of Mux
The Mux can be of different types based on input but in this article we will go
through two major types of mux which are

• 2×1 Mux
• 4×1 Mux
2×1 Multiplexer
The 2×1 is a fundamental circuit which is also known 2-to-1 multiplexer that are
used to choose one signal from two inputs and transmits it to the output. The 2×1
mux has two input lines, one output line, and a single selection line. It has various
applications in digital systems such as in microprocessor it is used to select
between two different data sources or between two different instructions.
Block Diagram of 2:1 Multiplexer with Truth Table
Given Below is the Block Diagram and Truth Table of 2:1 Mux. In this Block
Diagram where I0 and I1 are the input lines ,Y is the output line and S0 is a single
select line.

Block Diagram of 2:1 Multiplexer with Truth Table

The output of the 2×1 Mux will depend on the selection line S0,
• When S is 0(low), the I0 is selected
• when S0 is 1(High), I1 is selected
Logical Expression of 2×1 Mux
Using the Truth Table ,the Logical Expression for Mux can be determined as
Y=S0‾.I0+S0.I1Y=S0.I0+S0.I1

Circuit Diagram of 2×1 Multiplexers

Using truth table the circuit diagram can be given as
 Circuit Diagram of 2×1 Mux

4×1 Multiplexer
The 4×1 Multiplexer which is also known as the 4-to-1 multiplexer. It is a
multiplexer that has 4 inputs and a single output. The Output is selected as one of
the 4 inputs which is based on the selection inputs. The number of the Selection
lines will depend on the number of the input which is determined by the
equation log2nlog2n ,In 4×1 Mux the selection lines can be determined as log4=2log4
=2 ,slo two selections are needed.
Block Diagram of 4×1 Multiplexer
In the Given Block Diagram I0, I1, I2, and I3 are the 4 inputs and Y is the Single
output which is based on Select lines S0 and S1.
The output of the multiplexer is determined by the binary value of the selection
lines
• When S1S0=00, the input I0 is selected.
• When S1S0=01, the input I1 is selected.
• When S1S0=10, the input I2 is selected.
• When S1S0=11, the input I3 is selected.
Truth Table of 4×1 Multiplexer
Given Below is the Truth Table of 4×1 Multiplexer

Circuit Diagram of 4×1 Multiplexers

Using truth table the circuit diagram can be given as
Multiplexer can act as universal combinational circuit. All the standard logic
gates can be implemented with multiplexers.
Implementation of Different Gates with 2:1 Mux
Given below are the Implementation of Different gate using 2:1 Mux
Implementation of NOT gate using 2 : 1 Mux
The Not gate from 2:1 Mux can be obtained by
• Connect the input signal to one of the data input lines(I0).
• Then connect a line (0 or 1) to the other data input line(I1)
• Connect the same input line Select line S0 which is connected to D0.
Given Below is the Diagram for the Logical Representation of NOT gate using 2 :
1 Mux
Implementation of AND gate using 2 : 1 Mux
The And gate from 2:1 Mux can be obtained by
• Connect the input Y to I1.
• Connect the input X to the selection line S0.
• Connect a line(0) to I0.
Given Below is the Diagram for the Logical Representation of AND gate using 2 :
1 Mux

For further more on the Implementation of AND gate using 2 : 1 Mux

Implementation of OR gate using 2 : 1 Mux
The OR gate from 2:1 Mux can be obtained by
• Connect input X to the selection line S0.
• Connect input Y to I1.
• Connect Line(1) to I1.

Given Below is the Diagram for the Logical Representation of OR gate using 2 : 1
Mux
Implementation of NAND, NOR, XOR and XNOR gates requires two 2:1 Mux. First
multiplexer will act as NOT gate which will provide complemented input to the
second multiplexer.
Implementation of NAND gate using 2 : 1 Mux
The NAND gate from 2:1 Mux can be obtained by
• In first mux take inputs and 1 and 0 and y as selection line.
• In Second MUX the Output from mux is connected to I1.
• line(1) is given to the I0.
• x is given as selection line for the second Mux.

Given Below is the Diagram for the Logical Representation of NAND gate using 2
: 1 Mux

For further more on the Implementation of NAND gate using 2 : 1 Mux

Implementation of NOR gate using 2 : 1 Mux

The Nor gate from 2:1 Mux can be obtained by
• In first mux take inputs and 1 and 0 and y as selection line.
• In Second MUX the Output from mux is connected to I0.
• line(0) is given to the I1.
• x is given as selection line for the second Mux.

Given Below is the Diagram for the Logical Representation of NOR gate using 2 :
1 Mux

For further more on the Implementation of NOR gate using 2 : 1 Mux

Implementation of EX-OR gate using 2 : 1 Mux
The Nor gate from 2:1 Mux can be obtained by
• In first mux take inputs and 1 and 0 and y as selection line.
• In Second MUX the Output from mux is connected to I1.
• y is given to the I0.
• x is given as selection line for the second Mux.

Given Below is the Diagram for the Logical Representation of EX-OR gate using
2 : 1 Mux
Implementation of EX-NOR gate using 2 : 1 Mux
Given Below is the Diagram for the Logical Representation of EX-OR gate using
2 : 1 Mux

The Nor gate from 2:1 Mux can be obtained by

• In first mux take inputs and 1 and 0 and y as selection line.
• In Second MUX the Output from mux is connected to I0.
• y is given to the I1.
• x is given as selection line for the second Mux.

Implementation of Higher Order MUX using Lower

Order MUX
Given Below are the Implementation of Higher Order MUX Using Lower Order
MUX
4 : 1 MUX using 2 : 1 MUX
Three 2: 1 MUX are required to implement 4 : 1 MUX.
 4 : 1 MUX using 2 : 1 MUX

Similarly,

While an 8:1 MUX requires seven (7) 2:1 MUX, a 16:1 MUX requires fifteen (15)
2:1 MUX, and a 64:1 MUX requires sixty-three (63) 2:1 MUX. Hence, we can draw
the conclusion that an 2n:12n:1 MUX requires sixty-three (63) 2:1 MUX. Hence, we
can draw the conclusion that an 2 n :1 MUX requires (2n−1)2:1 MUX
(2 n −1)2:1 MUX.
16 : 1 MUX using 4 : 1 MUX
Given Below is the logical Diagram of 16:1 Mux Using 4:1 Mux
In general, to implement B : 1 MUX using A : 1 MUX , one formula is used to
implement the same.
B / A = K1,
K1/ A = K2,
K2/ A = K3

K N-1 / A = K N = 1 (till we obtain 1 count of MUX).

And then add all the numbers of MUXes = K1 + K2 + K3 + …. + K N .

To implement 64 : 1 MUX using 4 : 1 MUX
Using the above formula, we can obtain the same.
64 / 4 = 16
16 / 4 = 4
4 / 4 = 1 (till we obtain 1 count of MUX)
Hence, total number of 4 : 1 MUX are required to implement 64 : 1 MUX = 16 + 4
+ 1 = 21.

f ( A, B, C) = ∑∑ ( 1, 2, 3, 5, 6 ) with don’t care (7)

using A and B as the select lines for 4 : 1 MUX,
AB as select: Expanding the minterms to its boolean form and will see its 0 or 1
value in Cth place so that they can be placed in that manner.
AC as select : Expanding the minterms to its Boolean form and will see its 0 or 1
value in Bth place so that they can be place in that manner.

BC as select : Expanding the minterms to its boolean form and will see its 0 or 1
value in A th place so that they can be place in that manner.
Advantages of MUX
• Efficiency : The Mux has good efficiency in routing multiple input signals to a
single out signal based on control signals.
• Optimization : The Mux helps to conserve resources such as wires, pins
and integrated circuit (IC).
• Different Implementation: The Mux can be used to implement different
digital logic functions such AND,OR etc.
• Flexibility: Mux can be easily configure according to the requirements and
accommodate different data sources, enhancing system versatility.
Disadvantages of MUX
• Limited number of data sources: The number of input that can be taken by
a multiplexer is restricted by the number of control lines, which can cause
limitations in certain applications.
• Delay: Multiplexers can have some delay in the signal path, which can have
impact on the performance of the circuit.
• Complex control rationale: The control logic for multiplexers can be
complex, particularly for bigger multiplexers with an large number of inputs.
 • Power utilization: Multiplexers can consume more power compared with
other simple l ogic gate , particularly when they have a large number of
inputs.
Applications of MUX
• Data Routing : The Mux is used for data routing in the digital system where
they select one of the several data lines and re-route it the output.
• Data Selection : The Mux is used for data selection where they select data
source according to the select lines.
• Analog-to-Digital Conversion : The Mux are used in ADC to select different
analog input channels.
• Address Decoding : The Mux are used in Microprocessors or memory for
address decoding.
• Logic Function Implementation : Mux can be used to implement various
logic functions.
•

Encoders and Decoders in Digital Logic

Last Updated : 10 Jul, 2024

•
Binary code of N digits can be used to store 2N distinct elements of coded
information. This is what encoders and decoders are used for.
Encoders convert 2N lines of input into a code of N bits and Decoders decode the
N bits into 2N lines.
1. Encoders – An encoder is a combinational circuit that converts binary
information in the form of a 2N input lines into N output lines, which represent N
bit code for the input. For simple encoders, it is assumed that only one input line
is active at a time. As an example, let’s consider Octal to Binary encoder. As
shown in the following figure, an octal-to-binary encoder takes 8 input lines and
generates 3 output lines.
Truth Table –
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

As seen from the truth table, the output is 000 when D0 is active; 001 when D1 is
active; 010 when D2 is active and so on.
Implementation –
From the truth table, the output line Z is active when the input octal digit is 1, 3, 5
or 7. Similarly, Y is 1 when input octal digit is 2, 3, 6 or 7 and X is 1 for input octal
digits 4, 5, 6 or 7. Hence, the Boolean functions would be:
X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7
Hence, the encoder can be realised with OR gates as follows:

One limitation of this encoder is that only one input can be active at any given
time. If more than one inputs are active, then the output is undefined. For
example, if D6 and D3 are both active, then, our output would be 111 which is the
output for D7. To overcome this, we use Priority Encoders. Another ambiguity
arises when all inputs are 0. In this case, encoder outputs 000 which actually is
the output for D0 active. In order to avoid this, an extra bit can be added to the
output, called the valid bit which is 0 when all inputs are 0 and 1 otherwise.

Priority Encoder –
A priority encoder is an encoder circuit in which inputs are given priorities.
When more than one inputs are active at the same time, the input with higher
priority takes precedence and the output corresponding to that is generated. Let
us consider the 4 to 2 priority encoder as an example. From the truth table, we
see that when all inputs are 0, our V bit or the valid bit is zero and outputs are
not used. The x’s in the table show the don’t care condition, i.e, it may either be 0
or 1. Here, D3 has highest priority, therefore, whatever be the other inputs, when
D3 is high, output has to be 11. And D0 has the lowest priority, therefore the
output would be 00 only when D0 is high and the other input lines are low.
Similarly, D2 has higher priority over D1 and D0 but lower than D3 therefore the
output would be 010 only when D2 is high and D3 are low (D0 & D1 are don’t
care).
Truth Table –
D3 D2 D1 D0 X Y V

0 0 0 0 x x 0
D3 D2 D1 D0 X Y V

0 0 0 1 0 0 1

0 0 1 x 0 1 1

0 1 x x 1 0 1

1 x x x 1 1 1

Implementation –
It can clearly be seen that the condition for valid bit to be 1 is that at least any
one of the inputs should be high. Hence,
V = D0 + D1 + D2 + D3
For X:

=> X = D2 + D3 For Y:
=> Y = D1 D2’ + D3 Hence, the priority 4-to-2 encoder can be realized as follows:

2. Decoders –
A decoder does the opposite job of an encoder. It is a combinational circuit that
converts n lines of input into 2
n
lines of output. Let’s take an example of 3-to-8 line decoder.
Truth Table –
X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0
 X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Implementation –
D0 is high when X = 0, Y = 0 and Z = 0. Hence,
D0 = X’ Y’ Z’
Similarly,
D1 = X’ Y’ Z
D2 = X’ Y Z’
D3 = X’ Y Z
D4 = X Y’ Z’
D5 = X Y’ Z
D6 = X Y Z’
D7 = X Y Z
Hence,
Applications of Decoders
Decoders are commonly used combinational circuits. It converts n inputs to
generate 2n outputs. The decoders have applications in multiple fields like
computers, communication systems, digital circuits and many more. In this
article, we will explore the applications of decoders along with the basic
information of the decoders. Table of Content Deco
6 min read

Applications of Encoders
An encoder is an important combinational circuit that has applications in
different fields like computers, electronics, machines, communication systems
etc. The encoders take 2n inputs and generate n outputs. In this article, we will
 explore the different applications of encoders in detail. Table of Content
EncoderApplications of EncodersConclusion
5 min read

Encoder in Digital Logic

Last Updated : 27 Dec, 2024

•
An encoder is a digital circuit that converts a set of binary inputs into a unique
binary code. The binary code represents the position of the input and is used to
identify the specific input that is active. Encoders are commonly used in digital
systems to convert a parallel set of inputs into a serial code.
What is Encoder?
An Encoder is a combinational circuit that performs the reverse operation of
a Decoder. It has a maximum of 2^n input lines and ‘n’ output lines, hence it
encodes the information from 2^n inputs into an n-bit code. It will produce a
binary code equivalent to the input, which is active High. Therefore, the encoder
encodes 2^n input lines with ‘n’ bits.
The basic principle of an encoder is to assign a unique binary code to each possible
input. For example, a 2-to-4 line encoder has 2 input lines and 4 output lines and
assigns a unique 4-bit binary code to each of the 2^2 = 4 possible input
combinations. The output of an encoder is usually active low, meaning that only
one output is active (low) at any given time, and the remaining outputs are inactive
(high). The active low output is selected based on the binary code assigned to the
active input.

Encoder

Types of Encoders
There are different types of Encoders which are mentioned below.
• 4 to 2 Encoder
• Octal to Binary Encoder (8 to 3 Encoder)
• Decimal to BCD Encoder
• Priority Encoder
4 to 2 Encoder
The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0, and two outputs A1
& A0. At any time, only one of these 4 inputs can be ‘1’ in order to get the respective
binary code at the output. The figure below shows the logic symbol of the 4 to 2
encoder.

4 to 2 Encoder

The Truth table of 4 to 2 encoders is as follows.

INPUTS OUTPUTS

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Logical expression for A1 and A0:

A1 = Y3 + Y2
A0 = Y3 + Y1
The above two Boolean functions A1 and A0 can be implemented using two input
OR gates :
 Implementation using OR Gate

Octal to Binary Encoder (8 to 3 Encoder)

The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs: Y7 to Y0 and 3
outputs: A2, A1 & A0. Each input line corresponds to each octal digit value and
three outputs generate corresponding binary code. The figure below shows the
logic symbol of octal to the binary encoder.

Octal to Binary Encoder (8 to 3 Encoder)

The truth table for the 8 to 3 encoder is as follows.

INPUTS OUTPUTS

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Logical expression for A2, A1, and A0.

A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
The above two Boolean functions A2, A1, and A0 can be implemented using four
input OR gates.
 Implementation using OR Gate

Decimal to BCD Encoder

The decimal-to-binary encoder usually consists of 10 input lines and 4 output
lines. Each input line corresponds to each decimal digit and 4 outputs correspond
to the BCD code. This encoder accepts the decoded decimal data as an input and
encodes it to the BCD output which is available on the output lines. The figure
below shows the logic symbol of the decimal to BCD encoder :
 Decimal to BCD Encoder

The truth table for decimal to BCD encoder is as follows.

INPUTS OUTPUTS

Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 0 1 0 0 0 0 1

0 0 0 0 0 0 0 1 0 0 0 0 1 0

0 0 0 0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 0 1 0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0 0 0 0 1 0 1
 INPUTS OUTPUTS

0 0 0 1 0 0 0 0 0 0 0 1 1 0

0 0 1 0 0 0 0 0 0 0 0 1 1 1

0 1 0 0 0 0 0 0 0 0 1 0 0 0

1 0 0 0 0 0 0 0 0 0 1 0 0 1

Logical expression for A3, A2, A1, and A0.

A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
The above two Boolean functions can be implemented using OR gates.
 Implementation using OR Gate

Priority Encoder
A 4 to 2 priority encoder has 4 inputs: Y3, Y2, Y1 & Y0, and 2 outputs: A1 & A0.
Here, the input, Y3 has the highest priority, whereas the input, Y0 has the lowest
priority. In this case, even if more than one input is ‘1’ at the same time, the output
will be the (binary) code corresponding to the input, which is having higher
priority. The truth table for the priority encoder is as follows.
INPUTS OUTPUTS

Y3 Y2 Y1 Y0 A1 A0 V
INPUTS OUTPUTS

0 0 0 0 X X 0

0 0 0 1 0 0 1

0 0 1 X 0 1 1

0 1 X X 1 0 1

1 X X X 1 1 1

The logical expression for A1 is shown below.

Logical Expression

The Logical Expression for A0 is shown below.

 Logical Expression

The above two Boolean functions can be implemented as.

 Priority Encoder

There are some errors that usually happen in Encoders are mentioned below.
• There is an ambiguity, when all outputs of the encoder are equal to zero.
• If more than one input is active High, then the encoder produces an output,
which may not be the correct code.
So, to overcome these difficulties, we should assign priorities to each input of the
encoder. Then, the output of the encoder will be the code corresponding to the
active high inputs, which have higher priority.
Application of Encoders
• Encoders are very common electronic circuits used in all digital systems.
• Encoders are used to translate the decimal values to the binary in order to
perform binary functions such as addition, subtraction, multiplication, etc.
• Other applications especially for Priority Encoders may include detecting
interrupts in microprocessor applications.
Advantages of Encoders in Digital Logic
• Reduction in the number of lines: Encoders reduce the number of lines
required to transmit information from multiple inputs to a single output,
 which can simplify the design of the system and reduce the cost of
components.
• Improved reliability: By converting multiple inputs into a single serial code,
encoders can reduce the possibility of errors in the transmission of
information.
• Improved performance: Encoders can enhance the performance of a digital
system by reducing the amount of time required to transmit information from
multiple inputs to a single output.
Disadvantages of Encoders in Digital Logic
• Increased complexity: Encoders are typically more complex circuits
compared to multiplexers , and require additional components to implement.
• Limited to specific applications: Encoders are only suitable for applications
where a parallel set of inputs must be converted into a serial code.
• Limited flexibility: Encoders are limited in their flexibility, as they can only
encode a fixed number of inputs into a fixed number of outputs.
•

Latches in Digital Logic

Last Updated : 20 May, 2024

•
Latch is a digital circuit which converts its output according to its inputs
instantly. To implement latches, we use different logic gates. In this article, we
will see the definition of latches, latch types like SR, gated SR, D, gated D, JK and T
with its truth table and diagrams and advantages and disadvantages of latch.
Table of Content
• What are Latches?
• Types of Latches
• SR Latch
• Gated SR Latch
• D Latch
• Gated D Latch
• JK Latch
• T Latch
• Advantages of Latches
• Disadvantages of Latches
What are Latches?
Latches are digital circuits that store a single bit of information and hold its value
until it is updated by new input signals. They are used in digital systems as
temporary storage elements to store binary information. Latches can be
implemented using various digital logic gates, such as AND, OR, NOT, NAND, and
NOR gates.
Latches are widely used in digital systems for various applications, including
data storage, control circuits, and flip-flop circuits. They are often used in
combination with other digital circuits to implement sequential circuits, such as
state machines and memory elements.
Latches Definition
Latches are basic storage elements that operate with signal levels (rather than
signal transitions). Latches controlled by a clock transition are flip-flops. Latches
are level-sensitive devices. Latches are useful for the design of the asynchronous
sequential circuit. Latches are sequential circuit with two stable states. These are
sensitive to the input voltage applied and does not depend on the clock pulse.
Flip flops that do not use clock pulse are referred to as latch.
Types of Latches in Digital Electronics
In digital electronics different types of latches are:
• SR Latches
• Gated SR Latches
• D Latches
• Gated D Latches
• JK Latches
• T Laches

SR Latch
S-R latches i.e., Set-Reset latches are the simplest form of latches and are
implemented using two inputs: S (Set) and R (Reset). The S input sets the output
to 1, while the R input resets the output to 0. When both S and R inputs are at 1,
the latch is said to be in an “undefined” state. They are also known as preset and
clear states. The SR latch forms the basic building blocks of all other types of flip-
flops.
Truth Table of SR Latch
The below table represents the truth table of SR latch.
 S R Q Q’

0 0 Latch Latch

0 1 0 1

1 0 1 0

1 1 0 0

Logic Diagram of SR Latch

SR Latch is a logic circuit with:
• 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
• 2 input S for SET and R for RESET
• 2 output Q, Q’.
The below logic diagram represents the SR latch using NAND gate.

The below logic diagram represents SR latch using NOR Gate.

Different Cases of SR Latch
The different cases of SR latch are discussed below.
Case 1: S’ = R’ = 1 (S = R = 0)
If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.
If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1 respectively.
Case 2: S’ = 0, R’ = 1 (S = 1, R = 0)
• As S’ = 0, the output of 1st NAND gate, Q = 1 (SET state).
• In second NAND gate, as Q and R’ inputs are 1, Q’=0.
Case 3: S’ = 1, R’ = 0 (S = 0, R = 1)
• As R’=0, the output of 2nd NAND gate, Q’ = 1.
• In first NAND gate, as Q and S’ inputs are 1, Q = 0 (RESET state).

Case 4: S’ = R’ = 0 (S = R = 1)
When S = R = 1, both Q and Q’ becomes 1 which is not allowed. So, the input
condition is prohibited.
Gated SR Latch
A Gated SR latch is a SR latch with enable input which works when enable is 1
and retain the previous state when enable is 0.
Truth Table of Gated SR Latch
The below table represents the truth table of Gated SR latch.
Enable S R Qn+1

0 X X Qn

1 0 0 Qn

1 0 1 0

1 1 0 1

1 1 1 X

Logic Diagram of Gated SR Latch

The below logic diagram represents the gated SR latch.

Logic Diagram of Gated SR Latch

D Latch
D latches are also known as transparent latches and are implemented using two
inputs: D (Data) and a clock signal. The output of the latch follows the input at
the D terminal as long as the clock signal is high. When the clock signal goes low,
the output of the latch is stored and held until the next rising edge of the clock.
Truth Table of D Latch
The below table represents the truth table of D latch.
E D Q Q’

0 0 Latch Latch
 E D Q Q’

0 1 Latch Latch

1 0 0 1

1 1 1 0

Logic Diagram of D Latch

The below logic diagram represents the D latch.

Logic Diagram of D Latch

Gated D Latch
D latch is similar to SR latch with some modifications made. Here, the inputs are
complements of each other. The D latch stands for “data latch” as this latch stores
single bit temporarily.
Truth Table of Gated D Latch
The below table represents the truth table of Gated D latch.
Enable D Qn Qn+1 STATE

1 0 x 0 RESET

1 1 x 1 SET

0 x x Q(n) No Change

Characteristics Equation: Qn+1 = EN.D + EN’.Qn

Logic Diagram of Gated D Latch
The below logic diagram represents the gated D latch.

JK Latch
JK latch has two inputs J and K. The output gets toggled when the J and K inputs
are high. JK latch is just like SR latch, but it eliminates the undefined state of SR
latch.
Truth Table of JK Latch
The below table represents the truth table of JK latch.
J K Qn+1 Comment

0 0 Q No change

0 1 0 Reset

1 0 1 Set

1 1 Q’ Toggle

Logic Diagram of JK Latch

The below logic diagram represents the JK latch.
 Logic Diagram of JK Latch

T Latch
When the JK inputs of JK latch are shorted we get the T latch. In T latch the
outputs are toggled when the inputs are high.
Logic Diagram of T Latch
The below logic diagram represents the T latch.
 Logic Diagram of T Latch

Advantages of Latches
Some of the advantages of latches are listed below.
1. Easy to Implement: Latches are simple digital circuits that can be easily
implemented using basic digital logic gates.
2. Low Power Consumption: Latches consume less power compared to other
sequential circuits such as flip-flops.
3. High Speed: Latches can operate at high speeds, making them suitable for use
in high-speed digital systems.
4. Low Cost: Latches are inexpensive to manufacture and can be used in low-
cost digital systems.
5. Versatility: Latches can be used for various applications, such as data
storage, control circuits, and flip-flop circuits.
Disadvantages of Latches
Some of the disadvantages of latches are listed below.
1. No Clock: Latches do not have a clock signal to synchronize their operations,
making their behavior unpredictable.
2. Unstable State: Latches can sometimes enter into an unstable state when
both inputs are at 1. This can result in unexpected behavior in the digital
system.
 3. Complex Timing: The timing of latches can be complex and difficult to
specify, making them less suitable for real-time control applications.

Unit-3
Sequential circuit

o Introduction of Sequential Circuits

o Difference between Combinational and Sequential Circuit
o Flip-Flop types, their Conversion and Applications

Flip-Flop types, their Conversion and

Applications
•
Table of Content
• Flip-Flop
• Types
• S-R Flip Flop
• J-K Flip Flop
• D Flip Flop
• T Flip Flop
• Conversion for Flip Flops
• Applications
What is a Flip-Flop?
The flip-flop is a circuit that maintains a state until directed by input to change
the state. A basic flip-flop can be constructed using four-NAND or four-NOR
gates. Flip-flop is popularly known as the basic digital memory circuit. It has its
two states as logic 1(High) and logic 0(low) states. A flip flop is a sequential
circuit which consist of single binary state of information or data. The digital
circuit is a flip flop which has two outputs and are of opposite states. It is also
known as a Bistable Multivibrator.
Types of Flip-Flops
Given Below are the Types of Flip-Flop
• SR Flip Flop
• JK Flip Flop
• D Flip Flop
• T Flip Flop
Logic diagrams and truth tables of the different types of flip-flops are as follows:
S-R Flip Flop
In the flip flop, with the help of preset and clear when the power is switched ON,
the states of the circuit keeps on changing, that is it is uncertain. It may come to
set(Q=1) or reset(Q’=0) state. In many applications, it is desired to initially set or
reset the flip flop that is the initial state of the flip flop that needs to be assigned.
This thing is accomplished by the preset(PR) and the clear(CLR).
Block Diagram of S-R Flip Flop
Given Below is the Block Diagram of S-R Flip Flop
 S-R Flip Flop

Circuit Diagram and Truth Table of S-R Flip Flop

Given Below is the Diagram of S-R Flip Flop with its Truth Table
Operations of S-R Flip Flop
Given Below is the Operations of S-R Flip Flop
• Case 1(PR=CLR=1): The asynchronous inputs are inactive and the flip flop
responds freely to the S,R and the CLK inputs in the normal way.
• Case 2(PR=0 and CLR=1):This is used when the Q is set to 1.
• Case 3(PR=1 and CLR=0):This is used when the Q’ is set to 1.
• Case 4(PR=CLR=0): This is an invalid state.
Characteristics Equation for SR Flip Flop
QN+1 = QNR’ + SR’

J-K Flip Flop

In JK flip flops, The basic structure of the flip flop which consists of Clock (CLK),
Clear (CLR), Preset (PR).
Block Diagram of J-K Flip Flop
Given Below is Block Diagram of J-K Flip Flop

J-K Flip Flop

Circuit Diagram and Truth Table of J-K Flip Flop

Given Below is the Diagram of J-K Flip Flop with its Truth Table
Operations of J-K Flip Flop
Given Below is the Operations of J-K Flip Flop
• Case 1 (PR=CLR=0 ):This condition is in its invalid state.
• Case 2 (PR=0 and CLR=1):The PR is activated which means the output in the
Q is set to 1. Therefore, the flip flop is in the set state.
• Case 3 (PR=1 and CLR=0):The CLR is activated which means the output in
the Q’ is set to 1. Therefore, the flip flop is in the reset state.
• Case 4 (PR=CLR=1):In this condition the flip flop works in its normal way
whereas the PR and CLR gets deactivated.
Race Around Condition in J-K Flip Flop
When the J and K both are set to 1, the input remains high for a longer duration
of time, then the output keeps on toggling. Toggle means that switching in the
output instantly i.e. Q=0, Q’=1 will immediately change to Q=1 and Q’=0 and this
continuation keeps on changing. This change in output leads to race around
condition.
Characteristics Equation for JK Flip Flop
QN+1 = JQ’N + K’QN

D Flip Flop
The D Flip Flop Consists a single data input(D), a clock input(CLK),and two
outputs: Q and Q’ (the complement of Q).
Block Diagram of D Flip Flop
Given Below is the Block Diagram of D Flip Flop

D FLIP FLOP

Circuit Diagram and Truth Table of D Flip Flop

Given Below is the Diagram of D Flip Flop with its Truth Table
Operation of the D Flip-Flop
Given Below is the operation of D Flip-Flip
• Case 1 (PR=CLR=0):This conditions is represents as invalid state where both
PR(present) and CLR(clear) inputs are inactive.
• Case 2 (PR=0 and CLR=1):This state is set state in which PR is inactive (0)
and CLR is active(1) and the output Q is set to 1.
• Case 3 (PR=1 and CLR=0):This state is reset state in which PR is active (1)
and CLR is inactive (0) and the complementary output Q’ is set to 1.
• Case 4 (PR=CLR=1):In This state the flip flop behaves as normal, both PR and
CLR inputs are active(1).
Characteristics Equation for D Flip Flop
QN+1 = D

T Flip Flop
The T Flip Flop consists of data input (T), a clock input (CLK), and two outputs: Q
and Q’ (the complement of Q).
Block Diagram of T Flip Flop
Given Below is the Block Diagram of T Flip Flop
 T FLIP FLOP

Circuit Diagram and Truth Table of T Flip Flop

Given Below is the Circuit Diagram and Truth Table of T Flip Flop

Operation of the T Flip-Flop

Given Below is the Operation of T Flip-Flop
• Case 1 (T=0):In this condition the flip-flop remains in its current state
regardless of clock input,Also the Output Q will remain unchanged unit the
value of T will not change.
• Case 2 (T=1):In this condition the flip flop will change when T input is 1,At
each rising or falling edge of the clock signal the output Q will be in
complementary state.
Characteristics Equation for T Flip Flop
QN+1 = Q’NT + QNT’ = QN XOR T

Conversion for Flip Flops

The Excitation Table of the Flip Flop can be given as
EXCITATION TABLE:

Steps To Convert from One Flip Flop to Other

Let there be required flipflop to be constructed using sub-flipflop:
1. Draw the truth table of the required flip-flop.
2. Write the corresponding outputs of sub-flipflop to be used from the excitation
table.
3. Draw K-Maps using required flipflop inputs and obtain excitation functions
for sub-flipflop inputs.
4. Construct a logic diagram according to the functions obtained.
Convert SR To JK Flip Flop
The Table for the SR To JK is given as
Excitation Functions and Logic Diagram
Function and Logic Diagram for the conversion is given below
Convert SR To D Flip Flop
The Table for the SR To JK is given as
Excitation Functions and Logic Diagram
Function and Logic Diagram for the conversion is given below

Applications of Flip-Flops
These are the various types of flip-flops being used in digital electronic circuits
and the applications of Flip-flops are as specified below.
• Counters: The Flip Flop are used in the Counter Circuits for Counting pulse or
events.
• Frequency Dividers: The Flip Flop are used in Frequency Dividers to divide
the frequency of a input signal by a specific factor.
• Shift Registers: The Shift registers consist of interconnected flip-flops that
shift data serially.
• Storage Registers: The Storage Resistor uses Flip Flop to store data in binary
information.
• Bounce elimination switch: The Flip Flop are used in Bounce elimination
switch to eliminate the contact bounce.
• Data storage: The Flip Flop are used in the Data Storage to store binary data
temporarily or permanently.
• Data transfer: The Flip Flops are used for data transfer in different electronic
parts.
• Latch: The Latches are the Sequential circuit which uses Flip Flop for
temporary storage of data
• Registers: The Registers are mode from the array of flip flop which are used
to store data temporarily.
• Memory: The Flip Flops are the main components in the memory unit for
data storage.
Flip-Flop Types – FAQs
What is the difference between edge-triggered and level-triggered
flip-flops?
The Edge flip flop changes only when there is specific transitions of the clock signal
and level trigger flip flop changes only to continuous level of the clock signal.
How does a master-slave flip-flop differ from a simple flip-flop?
The Master Salve have two interconnected flip-flops whci operates as master and
other as slave.
What are the key differences between synchronous and
asynchronous flip-flops?
The Synchronous flip flops only changes to clico signal and Asynchronous flip flop
changes independent of the clock signal.

Conversion of S-R Flip-Flop into T Flip-Flop

Prerequisite - Flip-flop Here, we will discuss the process of conversion of S-R
Flip-Flop into a T Flip-Flop using an example. Rules for conversion: Step-1: Find
the characteristics table of required flip-flop and the excitation table of the
existing (given) flip-flop. Step-2: Find the expression of given flip-flop in terms of
required flip-flop us
1 min read

Conversion of J-K Flip-Flop into T Flip-Flop

Prerequisite - Flip-flop 1. J-K Flip-Flop: JK flip-flop shares the initials of Jack
Kilby, who won a Nobel prize for his fabrication of the world's first integrated
circuit, some people speculate that this type of flip flop was named after him
because a flip-flop was the first device that Kilby build when he was developing
integrated circuits. J-K
1 min read

Conversion of S-R Flip-Flop into D Flip-Flop

Prerequisite - Flip-flop 1. S-R Flip-Flop : S-R flip-flop is similar to S-R latch expect
clock signal and two AND gates. The circuit responds to the positive edge of clock
pulse to the inputs S and R. 2. D Flip-Flop : D Flip-Flop is a modified SR flip-flop
which has an additional inverter. It prevents the inputs from becoming the same
value. Conver
1 min read

Conversion of J-K Flip-Flop into D Flip-Flop

JK Flip-Flip is basically a gated SR flip-flop which has an additional input that is
clock input. It prevents the invalid output that may be obtained when both the
inputs are 1. Whereas D Flip-Flop is a modified SR flip-flop which has an
additional inverter. It prevents the inputs from becoming the same value. What is
Flip-Flop? A flip-flop is a ba
6 min read

JK Flip Flop and SR Flip Flop

Flip Flop is popularly known as the basic digital memory circuit. It has two states
as logic 1(High) and logic 0(low) states. A flip flop is a sequential circuit which
consists of a single binary state of information or data. The digital circuit is a flip
flop which has two outputs and are of opposite states. It is also known as a
Bistable Multivib
8 min read

Applications of Flip Flop

Digital electronics is a very important branch of engineering used for circuit
design and data storage. Flip Flops are an important part of digital electronics
and are widely used for different purposes. In this article, we will study what are
flip flops and the principles used in the working of flip flops. We will also see the
applications of flip
10 min read

Difference between Flip-flop and Latch

Flip-flops and latches are two kinds of memory circuits used in electronics. The
main difference between them is how they react to changes. A latch changes its
output whenever its input changes. This means it's always ready to respond. On
the other hand, a flip-flop only changes its output at specific moments, like when
its control signal goes from
6 min read

D Flip Flop
Prerequisite : Introduction to Sequential Circuit Flip Flop is an electronic device
or to be precise a kind of memory component that can hold one bit of data. A flip
flop has two states, that is "SET" and "RESET". Those states are represented with
the binary values 0 and 1. The flip flop remains in its current state until its
receives a signal that
5 min read

Mod 6 Johnson Counter (with D flip-flop)

Johnson counters are one of the most important applications of shift registers.
They are created by connecting multiple flip-flops to one another (such that the
output of one flip-flop is the input for another), and by connecting the
complement of the output of the last flip-flop to the input of the first flip-flop. For
a mod 6 Johnson counter, 3 f
1 min read

Mod 2 Ring Counter (with D flip-flop)

Ring counters are one of the most important applications of shift registers. They
are created by connecting multiple flip-flops to one another (such that the output
of one flip-flop is the input for another), and by connecting the output of the last
flip-flop to the input of the first flip-flop. For a mod 2-ring counter, two flip-flops
will be requ
1 min read

T Flip Flop
Flip-flop is a term that comes under digital electronics, and it is an electronic
component that is used to store one single bit of information. Diagrammatic
Representation of Flip FlopSince Flip Flop is a sequential circuit its input is based
upon two parameters, one is the current input and the other is the output from
the previous state.It has t
4 min read

What is JK Flip-Flop ?
In Digital Electronic flip-flops are widely used for handling binary information.
These fundamental building blocks are used to store and manipulate information
as per our needs. From the Flipflop family, Jack Kilby flip-flop(JK Flipflop) is
versatile and can be used as a basic memory element. It can also store toggle
functionality with a diversity
8 min read

Master-Slave JK Flip Flop

Prerequisite -Flip-flop types and their ConversionRace Around Condition In JK
Flip-flop - For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q
output will toggle as long as CLK is high, which makes the output of the flip-flop
unstable or uncertain. This problem is called race around condition in J-K flip-
flop. This problem (R
4 min read

SR Flip Flop
In this article, we will go through SR Flip Flop, we will start our article with the
definition and construction of the flip-flip, and then we will go through its Basic
 Block Diagram with its working and characteristic block diagram, at last, we will
conclude our article with its applications. Table of Content SR Flip
FlopConstruction Basic Block D
5 min read

Types and Applications of LED

Visible LEDs and invisible LEDs are two classes of light emitting diodes. The
wavelength or color of emitting light depends on the forbidden gap or energy gap
of the materials. Types of LED : Gallium Phosphide (GaP) – red, yellow and
greenAluminium Gallium Phosphide (AlGaP) – greenGallium Nitride (GaN) –
green, emerald greenGallium Arsenide (GaAs)
2 min read

Analog to Analog Conversion (Modulation)

Analog Signal: An analog signal is any continuous signal for which the time
varying feature of the signal is a representation of some other time varying
quantity i.e., analogous to another time varying Signal. Analog to Analog
Conversion - Analog-to-analog conversion, or modulation, is the representation
of analog information by an analog signal. I
3 min read

Introduction of Sequential Circuits

Last Updated : 28 Dec, 2024

•
Sequential circuits are digital circuits that store and use the previous state
information to determine their next state. Unlike combinational circuits, which
only depend on the current input values to produce outputs, sequential circuits
depend on both the current inputs and the previous state stored in memory
elements.
Sequential Circuit
Sequential circuits are digital circuits that store and use previous state
information to determine their next state. They are commonly used in digital
systems to implement state machines, timers, counters, and memory elements and
are essential components in digital systems design. Sequential circuits are
commonly used in digital systems to implement state machines, timers, counters,
and memory elements. The memory elements in sequential circuits can be
implemented using flip-flops, which are circuits that store binary values and
maintain their state even when the inputs change.
Sequential circuit is a combinational logic circuit that consists of inputs variable
(X), logic gates (Computational circuit), and output variable (Z).

A combinational circuit produces an output based on input variables only, but

a sequential circuit produces an output based on current input and previous
output variables. That means sequential circuits include memory elements that
are capable of storing binary information. That binary information defines the
state of the sequential circuit at that time. A latch capable of storing one bit of
information.

As shown in the figure, there are two types of input to the combinational logic :
1. External inputs which are not controlled by the circuit.
2. Internal inputs, which are a function of a previous output state.
Secondary inputs are state variables produced by the storage elements, whereas
secondary outputs are excitations for the storage elements.
Types of Sequential Circuits
There are two types of sequential circuits
Asynchronous Sequential Circuit
These circuits do not use a clock signal but uses the pulses of the inputs. These
circuits are faster than synchronous sequential circuits because there is clock
pulse and change their state immediately when there is a change in the input
signal. We use asynchronous sequential circuits when speed of operation is
important and independent of internal clock pulse.

But these circuits are more difficult to design and their output is uncertain.
Synchronous Sequential Circuit
These circuits uses clock signal and level inputs (or pulsed) (with restrictions on
pulse width and circuit propagation). The output pulse is the same duration as the
clock pulse for the clocked sequential circuits. Since they wait for the next clock
pulse to arrive to perform the next operation, so these circuits are
bit slower compared to asynchronous. Level output changes state at the start of
an input pulse and remains in that until the next input or clock pulse.

We use synchronous sequential circuit in synchronous counters, flip flops, and in

the design of MOORE-MEALY state management machines. We use sequential
circuits to design Counters, Registers, RAM, MOORE/MEALY Machine and other
state retaining machines.
Clock Signal and Triggering
Clock signal is a kind of control signal that allows the elements of synchronous
circuits to be in phase or phenomena that occur in circuits. It is derived from the
square wave that has a high and a low level, it helps in measuring the sequential
changes in the circuit states. The clock signal also makes a pulse simultaneously
on all the circuit parts that are needed for the proper work of synchronous
sequential circuits.
Types of Triggering
In Sequential circuits, triggering denotes the way, in terms of which the state
changes take place. There are two main types of triggering
Level Triggering
Level triggering happens when the change of state is from the level of the clock
signal is high or low. The circuit depends on the level of the clock signal rather than
the rising or the falling edge of it. There are two types of level triggering:
1. Positive Level Triggering: The circuit changes state when it is high time in
the clock cycle i.e. when the clock signal is high.
2. Negative Level Triggering: The circuit changes state when the clock signal is
in the low state.

Edge Triggering
Edge triggering occurs when the state change is initiated by the transition (rising
or falling edge) of the clock signal. The circuit responds to the clock signal’s edges
rather than its levels. There are two types of edge triggering:
1. Positive Edge Triggering: The circuit changes state on the rising edge
(transition from low to high) of the clock signal.
2. Negative Edge Triggering: The circuit changes state on the falling edge
(transition from high to low) of the clock signal.

Edge Triggering

Advantages of Sequential Circuits

1. Memory: Sequential circuits have the ability to store binary values, which
makes them ideal for applications that require memory elements, such as
timers and counters.
2. Timing: Sequential circuits are commonly used to implement timing and
synchronization in digital systems , making them essential for real-time
control applications.
3. State machine implementation: Sequential circuits can be used to implement
state machines, which are useful for controlling complex digital systems and
ensuring that they operate as intended.
4. Error detection: Sequential circuits can be designed to detect errors in digital
systems and respond accordingly, improving the reliability of digital systems.
Disadvantages of Sequential Circuits
1. Complexity: Sequential circuits are typically more complex than
combinational circuits and require more components to implement.
 2. Timing constraints: The design of sequential circuits can be challenging due to
the need to ensure that the timing of the inputs and outputs is correct.
3. Testing and debugging: Testing and debugging sequential circuits can be
more difficult compared to combinational circuits due to their complex
structure and state-dependent outputs.
Applications
Sequential circuits find application in virtually almost every digital system today
because of their capacity to handle state information. Some common applications
include:
• Counters: Appearing in commonly in digital clocks, frequency counters, and
event counters.
• Registers: Found in microprocessors and digital systems as a storage medium,
a transfer medium and a medium for manipulating data.
• Memory Elements: Used in RAM and other storage devices to keep data in a
temporary hold.
• State Machines: Made use in control systems , communication processes, and
different digital devices for state control.
• Timers: It is applied in time measurement, delay production, and scheduling
functions in digital circuits.

Difference between Combinational and

Sequential Circuit
Last Updated : 03 Oct, 2024

•
In digital electronics, circuits are classified into two primary categories: The
combinational circuits and the sequential circuits. Where the outputs depend
on the current inputs are called combination circuit, combinational circuits are
simple and effective for functions like addition, subtraction and logical works.
In contrast, the sequential circuits possess memory that store past inputs;
hence the output depends on the current inputs in addition to the previous
input data. There is a clear difference between these two categories of circuits,
which makes it important to understand the differences in order to create
functioning circuits.
What is Combinational Circuit?
A combinational circuit is a kind of digital electronic circuit of which outputs
depend on the present inputs and have no connections to the past inputs.
These circuits do such tasks as additions, subtractions and logically AND, OR
and NOR circuits. The key characteristics of combinational circuits include:
• No Memory Elements: The output is dependent solely on the current
policy inputs.
• Immediate Response: Good input differs from its output and bad input
differs from its output.
• Examples: The most commonly encountered examples are adders,
multiplexers and encoders.

Combinational Circuit

Advantages of Combinational Circuits

• Simplicity: It is easier to design and implement more so because it lacks
memory elements mainly.
• Speed: Operational at a faster rate as the output automatically adjusts
with the changes in inputs.
• Resource Efficiency: Generally it needs far fewer components as
compared to its equivalent sequential circuits.
Disadvantages of Combinational Circuits
• Limited Functionality: Is not able to perform operations that need
historical information or sequence details.
• Complexity with Increased Inputs: It becomes difficult to
design combinational circuits when there are many inputs.
What is Sequential Circuit?
Sequential circuits are quite different from combinational circuits in the sense
that they employ memory components. A sequential circuit provides output
based on current inputs as well as prior inputs; therefore, it is more functional.
Key features include:
• Memory Elements: These circuits have flip-flop or latch to store past
state information.
• Time Dependency: Current input values as well as the previous input
states have an impact on the output.
• Examples: Recurrent ones are counters and registers, while other formal
ones are finite state machines.
 Sequential Circuit

Advantages of Sequential Circuits

• Memory Utilization: Able to store the previous states in order to perform
the operations.
• Functional Versatility: It is used for those tasks which need a series of
operations, state machines, and counters.
Disadvantages of Sequential Circuits
• Complexity: More difficult to design compared to counter-propagators
due to the use of memory elements.
• Slower Operation: Output changes may represent a delay because often
they require data processing from the past.
Difference between Combinational and Sequential
Circuit
Sequential
Aspect Combinational Circuit Circuit

Output
depends on
both current
Output depends only on the current inputs.
inputs and past
states
Definition (memory).

Requires
Memory Does not require memory elements. memory
Elements elements like
 Sequential
Aspect Combinational Circuit Circuit

flip-flops or
latches.

Output is
dependent on
Output is immediate, based on input
clock pulses
Timing changes.
and previous
Dependency states.

Requires a
clock signal to
No clock signal required.
synchronize
Clock Signal state changes.

More complex
due to memory
Design Simpler design without the need for memory.
and clock
Complexity management.

Slower due to
Faster, as outputs change instantly with dependency on
inputs. clock cycles
Speed and past states.

Performs
operations that
Performs basic logical operations without
require
sequence dependency.
sequences or
Functionality timed events.

Counters, Shift
Registers, Flip-
Adders, Subtractors, Multiplexers, Encoders.
Flops, State
Examples Machines.
 Sequential
Aspect Combinational Circuit Circuit

Higher power
consumption
Generally lower power consumption. due to memory
Power and clock
Consumption circuitry.

Used in
applications
involving
Used in tasks requiring direct logical
sequential
operations (e.g., arithmetic).
operations
(e.g., counters,
Application registers).

Counters in Digital Logic

Last Updated : 06 Mar, 2023

•
A Counter is a device which stores (and sometimes displays) the number of times
a particular event or process has occurred, often in relationship to a clock
signal. Counters are used in digital electronics for counting purpose, they can
count specific event happening in the circuit. For example, in UP counter a counter
increases count for every rising edge of clock. Not only counting, a counter can
follow the certain sequence based on our design like any random sequence
0,1,3,2… .They can also be designed with the help of flip flops. They are used as
frequency dividers where the frequency of given pulse waveform is divided.
Counters are sequential circuit that count the number of pulses can be either in
binary code or BCD form. The main properties of a counter are timing , sequencing
, and counting. Counter works in two modes
Up counter
Down counter
Counter Classification
Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter
1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven
by main clock and the clock input of rest of the following flip flop is driven by
output of previous flip flops. We can understand it by following diagram-

It is evident from timing diagram that Q0 is changing as soon as the rising edge of
clock pulse is encountered, Q1 is changing when rising edge of Q0 is
encountered(because Q0 is like clock pulse for second flip flop) and so on. In this
way ripples are generated through Q0,Q1,Q2,Q3 hence it is also
called RIPPLE counter and serial counter. A ripple counter is a cascaded
arrangement of flip flops where the output of one flip flop drives the clock input
of the following flip flop
2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock
which drives each flip flop so output changes in parallel. The one advantage of
synchronous counter over asynchronous counter is, it can operate on higher
frequency than asynchronous counter as it does not have cumulative delay
because of same clock is given to each flip flop. It is also called as parallel
counter.

Synchronous counter circuit

 Timing diagram synchronous counter
From circuit diagram we see that Q0 bit gives response to each falling edge of
clock while Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is
dependent on Q2,Q1 and Q0.

Decade Counter
A decade counter counts ten different states and then reset to its initial states. A
simple decade counter will count from 0 to 9 but we can also make the decade
counters which can go through any ten states between 0 to 15(for 4 bit counter).

Clock pulse Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1
2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

Truth table for simple decade counter

Decade counter circuit diagram

 Shift Registers in Digital Logic
Last Updated : 27 Dec, 2024

•
Pre-Requisite: Flip-Flops
Flip flops can be used to store a single bit of binary data (1 or 0). However, in
order to store multiple bits of data, we need multiple flip-flops. N flip flops are
to be connected in order to store n bits of data. A Register is a device that is
used to store such information. It is a group of flip-flops connected in series
used to store multiple bits of data. The information stored within these registers
can be transferred with the help of shift registers.
Shift Register is a group of flip flops used to store multiple bits of data. The
bits stored in such registers can be made to move within the registers and
in/out of the registers by applying clock pulses. An n-bit shift register can be
formed by connecting n flip-flops where each flip-flop stores a single bit of
data. The registers which will shift the bits to the left are called “Shift left
registers”. The registers which will shift the bits to the right are called “Shift
right registers”. Shift registers are basically of following types.

Types of Shift Registers

• Serial In Serial Out shift register
• Serial In parallel Out shift register
• Parallel In Serial Out shift register
• Parallel In parallel Out shift register
• Bidirectional Shift Register
• Universal Shift Register
• Shift Register Counter
Serial-In Serial-Out Shift Register (SISO)
The shift register, which allows serial input (one bit after the other through a
single data line) and produces a serial output is known as a Serial-In Serial-
Out shift register. Since there is only one output, the data leaves the shift
register one bit at a time in a serial pattern, thus the name Serial-In Serial-Out
Shift Register. The logic circuit given below shows a serial-in serial-out shift
register. The circuit consists of four D flip-flops which are connected in a serial
manner. All these flip-flops are synchronous with each other since the same
clock signal is applied to each flip-flop.
 Serial-In Serial-Out Shift Register (SISO)

The above circuit is an example of a shift right register, taking the serial data
input from the left side of the flip flop. The main use of a SISO is to act as a
delay element.
Serial-In Parallel-Out Shift Register (SIPO)
The shift register, which allows serial input (one bit after the other through a
single data line) and produces a parallel output is known as the Serial-In
Parallel-Out shift register. The logic circuit given below shows a serial-in-
parallel-out shift register. The circuit consists of four D flip-flops which are
connected. The clear (CLR) signal is connected in addition to the clock signal
to all 4 flip flops in order to RESET them. The output of the first flip-flop is
connected to the input of the next flip flop and so on. All these flip-flops are
synchronous with each other since the same clock signal is applied to each
flip-flop.
 Serial-In Parallel-Out shift Register (SIPO)

The above circuit is an example of a shift right register, taking the serial data
input from the left side of the flip-flop and producing a parallel output. They are
used in communication lines where demultiplexing of a data line into several
parallel lines is required because the main use of the SIPO register is to
convert serial data into parallel data.
Parallel-In Serial-Out Shift Register (PISO)
The shift register, which allows parallel input (data is given separately to each
flip flop and in a simultaneous manner) and produces a serial output is known
as a Parallel-In Serial-Out shift register. The logic circuit given below shows a
parallel-in-serial-out shift register. The circuit consists of four D flip-flops which
are connected. The clock input is directly connected to all the flip-flops but the
input data is connected individually to each flip-flop through a multiplexer at the
input of every flip-flop. The output of the previous flip-flop and parallel data
input are connected to the input of the MUX and the output of MUX is
connected to the next flip-flop. All these flip-flops are synchronous with each
other since the same clock signal is applied to each flip-flop.
 Parallel-In Serial-Out Shift Register (PISO)

A Parallel in Serial Out (PISO) shift register is used to convert parallel data to
serial data.
Parallel-In Parallel-Out Shift Register (PIPO)
The shift register, which allows parallel input (data is given separately to each
flip flop and in a simultaneous manner) and also produces a parallel output is
known as Parallel-In parallel-Out shift register. The logic circuit given below
shows a parallel-in-parallel-out shift register. The circuit consists of four D flip-
flops which are connected. The clear (CLR) signal and clock signals are
connected to all 4 flip-flops. In this type of register, there are no
interconnections between the individual flip-flops since no serial shifting of the
data is required. Data is given as input separately for each flip flop and in the
same way, output is also collected individually from each flip flop.
 Parallel-In Parallel-Out Shift Register (PIPO)

A Parallel in Parallel out (PIPO) shift register is used as a temporary storage

device and like SISO Shift register it acts as a delay element.
Bidirectional Shift Register
If we shift a binary number to the left by one position, it is equivalent to
multiplying the number by 2 and if we shift a binary number to the right by one
position, it is equivalent to dividing the number by 2. To perform these
operations we need a register which can shift the data in either direction.
Bidirectional shift registers are the registers that are capable of shifting the
data either right or left depending on the mode selected. If the mode selected
is 1(high), the data will be shifted toward the right direction and if the mode
selected is 0(low), the data will be shifted towards the left direction. The logic
circuit given below shows a Bidirectional shift register. The circuit consists of
four D flip-flops which are connected. The input data is connected at two ends
of the circuit and depending on the mode selected only one gate is in the active
state.
 Bidirectional Shift Register

Universal Shift Register

Universal Shift Register is a type of register that contains the both right shift and
the left shift. It has also parallel load capabilities. Generally, these types of
registers are taken as memory elements in computers. But, the problem with
this type of register is that it shifts only in one direction. In simple words, you
mean that the universal shift register is a combination of the bidirectional shift
register and the unidirectional shift register.
 Universal Shift Register

N-bit universal shift register consists of flip-flops and multiplexers. Both are N
in size. In this, all the n multiplexers share the same select lines and this select
input selects the suitable input for flip-flops.
Shift Register Counter
Shift Register Counters are the shift registers in which the outputs are
connected back to the inputs in order to produce particular sequences. There
are basically two types:
• Ring Counter
• Johnson Counter
Ring Counter
A ring counter is basically a shift register counter in which the output of the
first flip-flop is connected to the next flip-flop and so on and the output of the
last flip-flop is again fed back to the input of the first flip-flop, thus the name
ring counter. The data pattern within the shift register will circulate as long as
clock pulses are applied. The logic circuit given below shows a Ring Counter.

Ring Counter Truth Table

The circuit consists of four D flip-flops which are connected. Since the circuit
consists of four flip-flops the data pattern will repeat after every four clock
pulses as shown in the truth table. A Ring counter is generally used because
it is self-decoding. No extra decoding circuit is needed to determine what state
the counter is in.

Ring Counter
Johnson Counter
A Johnson counter is basically a shift register counter in which the output of
the first flip flop is connected to the next flip flop and so on and the inverted
output of the last flip flop is again fed back to the input of the first flip flop. They
are also known as twisted ring counters. The logic circuit given below shows
a Johnson Counter. The circuit consists of four D flip-flops which are
connected.

Johnson Counter Truth Table

An n-stage Johnson counter yields a count sequence of 2n different states,

thus also known as a mod-2n counter. Since the circuit consists of four flip-
flops the data pattern will repeat every eight clock pulses as shown in the truth
table. The main advantage of the Johnson counter is that it only needs n
number of flip-flops compared to the ring counter to circulate a given data to
generate a sequence of 2n states.
 Johnson Counter

Applications of Shift Registers

• The shift registers are used for temporary data storage.
• The shift registers are also used for data transfer and data manipulation.
• The serial-in serial-out and parallel-in parallel-out shift registers are used
to produce time delay to digital circuits.
• The serial-in parallel-out shift register is used to convert serial data into
parallel data thus they are used in communication lines where
demultiplexing of a data line into several parallel lines is required.
• A Parallel in Serial out shift register is used to convert parallel data to
serial data.

Difference between RAM and ROM

Last Updated : 29 Jul, 2024

•
Memory is an important part of the Computer which is responsible for storing data
and information on a temporary or permanent basis. Memory can be classified into
two broad categories:
• Primary Memory
• Secondary Memory
What is Primary Memory?
Primary Memory is a type of Computer Memory that the Preprocessor directly
accesses. It is used to store data on which computer is currently working. It has
less storage than Secondary Memory. It is basically of two types:
• Random Access Memory (RAM)
• Read Only Memory (ROM)

What is Secondary Memory?

Secondary Memory is a type of Computer Memory which is used to permanently
store the data and information. It has a larger data storage capacity than Primary
Memory. Secondary Memory is not directly accessible from CPU. It is basically of
four types:

• Hard Disk
• Compact Disc (CD)
• Digital Versatile Disk (DVD)
• Floppy Disk

Types of Memory

Primary Memory is classified into two types: RAM and ROM. In this article, we are
going to discuss the differences between RAM and ROM.
Random Access Memory
Random Access Memory (RAM) is used to store the programs and data being used
by the CPU in real time. The data on the random access memory can be read,
written, and erased any number of times. RAM is a hardware element where the
data currently used is stored. It is a volatile memory. It is also called as Main
Memory or Primary Memory. This is user’s memory. The software (program) as
well as data files are stored on the hard disk when the software or those files are
opened. They get expanded into RAM. It is the space where temporary data are
automatically stored until the user saves it into the secondary storage devices.
Types of RAM
• Static RAM: Static RAM or SRAM stores a bit of data using the state of a six-
transistor memory cell.
• Dynamic RAM: Dynamic RAM or DRAM stores a bit of data using a pair of
transistors and capacitors which constitute a DRAM memory cell.
 Types of Primary Memory

Advantages of RAM
• Speed: RAM is much faster than other types of memory, such as hard disk
drives, making it ideal for storing and accessing data that needs to be accessed
quickly.
• Volatility: RAM is volatile memory, which means that it loses its contents
when power is turned off. This property allows RAM to be easily
reprogrammed and reused.
• Flexibility: RAM can be easily upgraded and expanded, allowing for more
memory to be added as needed.
Disadvantages of RAM
• Limited capacity: RAM has a limited capacity, which can limit the amount of
data that can be stored and accessed at any given time.
• Volatility: The volatile nature of RAM means that data must be saved to a
more permanent form of storage, such as a hard drive or SSD, to prevent data
loss.
• Cost: RAM can be relatively expensive, particularly for high-capacity modules,
which can make it difficult to scale memory as needed.
Read Only Memory
Read Only Memory (ROM) is a type of memory where the data has been pre-
recorded. Data stored in ROM is retained even after the computer is turned off i.e.,
non-volatile. ROM is primary non-volatile memory. It is generally used in
Embedded Parts, where the programming requires almost no changes. It is a
permanent CNO4 erasable memory gets initiated when the power is supplied to
the computer ROM is a memory chip fixed on the motherboard at the time of
manufacturing. It stores a program called BIOS (Basic Input/Output System). This
program checks the status of all the devices attached to the computer.
Types of ROM
• Programmable ROM: It is a type of ROM where the data is written after the
memory chip has been created. It is non-volatile.
• Erasable Programmable ROM: It is a type of ROM where the data on this
non-volatile memory chip can be erased by exposing it to high-intensity UV
light.
• Electrically Erasable Programmable ROM: It is a type of ROM where the
data on this non-volatile memory chip can be electrically erased using field
electron emission.
• Mask ROM: It is a type of ROM in which the data is written during the
manufacturing of the memory chip.
• Advantages of ROM
• Non-volatile: ROM is non-volatile memory, which means that it retains its
contents even when power is turned off. This property makes ROM ideal for
storing permanent data, such as firmware and system software.
Advantages of ROM
• Non-volatile: ROM is non-volatile memory, which means that it retains its
contents even when power is turned off. This property makes ROM ideal for
storing permanent data, such as firmware and system software.
• Stability: ROM is stable and reliable, which makes it a good choice for critical
systems and applications.
• Security: ROM cannot be easily modified, which makes it less susceptible to
malicious attacks, such as viruses and malware.
Disadvantages of ROM
• Limited flexibility: ROM cannot be easily reprogrammed or updated, which
makes it difficult to modify or customize the contents of ROM.
• Limited capacity: ROM has a limited capacity, which can limit the amount of
data that can be stored and accessed at any given time.
• Cost: ROM can be relatively expensive to produce, particularly for custom or
specialized applications, which can make it less cost-effective than other types
of memory.
Difference Between RAM and ROM
 Random Access
Difference Memory (RAM) Read Only Memory (ROM)

RAM is a volatile memory

ROM is a non-volatile memory that the
Data- that could store the data as
could retain the data even when the power
Retention long as the power is
is turned off.
supplied.

Read and write operations

Read/Write Only read operations are supported.
are supported.

Used to store the data that It is typically used to store firmware or

has to be currently microcode, which is used to initialize and
Use
processed by CPU control hardware components of the
temporarily. computer.

Speed It is a high-speed memory. It is much slower than the RAM.

CPU CPU can easily access data CPU cannot easily access data stored in
Interaction stored in RAM. ROM.

Size and Large size with higher Small size with less capacity, concerning
Capacity capacity, concerning ROM. RAM.

CPU Cache , Primary

Used as/in Firmware, Micro-controllers.
memory.

The data stored is easily The data stored is not as easily accessible
Accessibility
accessible. as in the concerning RAM.

RAM is more costlier than

Cost ROM is cheaper than RAM.
ROM.

A RAM chip can store only

A ROM chip can store multiple
Chip Size a few gigabytes (GB) of
megabytes (MB) of data.
data.
 Random Access
Difference Memory (RAM) Read Only Memory (ROM)

Used for the temporary

storage of data currently Used to store firmware, BIOS, and other
Function
being processed by the data that needs to be retained.
CPU.

Conclusion
In conclusion, RAM (Random Access Memory) and ROM (Read Only Memory) are
two types of computer memory that are important and have different features.
RAM is high-speed, volatile memory used to store and process temporary data.
ROM, on the other hand, is non-volatile memory used to store lasting data like
firmware. RAM is more flexible, but it costs more, while ROM is more stable and
secure, but it doesn’t have as much freedom. Understanding the differences
between these two types of memory is important for running a computer and
managing files well.
Frequently Asked Questions on Difference Between RAM
and ROM – FAQ’S
What are the types of Random Access Memory (RAM)?
There are two types of RAM:
• Static RAM (SRAM)
• Dynamic RAM (DRAM)

What are the types of Read Only Memory (ROM)?

There are four types of ROM:
• Masked ROM (MROM)
• Programmable ROM (PROM)
• Erasable Programmable ROM (EPROM)
• Electrically erasable programmable ROM (EEPROM)

Analog to Digital Conversion

Last Updated : 24 Jul, 2024

•
Digital Signal: A digital signal is a signal that represents data as a sequence
of discrete values; at any given time it can only take on one of a finite
number of values.
Analog Signal: An analog signal is any continuous signal for which the time
varying feature of the signal is a representation of some other time-varying
quantity i.e., analogous to another time varying signal.
Importance of Analog to Digital Conversion
• The main role of ADC in modern technology development process is the
transition of voice communication systems from outdated analogue signal
processing to the more advanced voice over IP, or VoIP, systems of today
is largely due to the contribution.
• The teletypewriters and other computer input devices needed to be
connected to a modem which was connected to a mainframe or other
front end computer system to communicate with the required computer
systems. In contrast to the ultrahigh-speed networks of today, modem
transmission speeds were modest to process.
• The systems for smaller office applications and the digital private branch
exchange, or PBX, were developed by using ADC technology as the
foundation to process properly.
Techniques of Analog-to-Digital Conversion
The following techniques can be used for Analog to Digital Conversion –
a. PULSE CODE MODULATION
The most common technique to change an analog signal to digital data is
called pulse code modulation (PCM). A PCM encoder has the following three
processes:
1. Sampling
2. Quantization
3. Encoding
Low pass filter : The low pass filter eliminates the high frequency
components present in the input analog signal to ensure that the input signal
to sampler is free from the unwanted frequency components. This is done to
avoid aliasing of the message signal.
1. Sampling – The first step in PCM is sampling. Sampling is a process of
measuring the amplitude of a continuous-time signal at discrete instants,
converting the continuous signal into a discrete signal. There are three
sampling methods: (i) Ideal Sampling: In ideal Sampling also known as
Instantaneous sampling pulses from the analog signal are sampled. This
is an ideal sampling method and cannot be easily implemented. (ii)
Natural Sampling: Natural Sampling is a practical method of sampling in
which pulse have finite width equal to T.The result is a sequence of
samples that retain the shape of the analog signal.
(iii) Flat top sampling: In comparison to natural sampling flat top
sampling can be easily obtained. In this sampling technique, the top of the
samples remains constant by using a circuit. This is the most common
sampling method used.
 Nyquist Theorem: One important consideration is the sampling rate or
frequency. According to the Nyquist theorem, the sampling rate must be
at least 2 times the highest frequency contained in the signal. It is also
known as the minimum sampling rate and given by: Fs =2*fh
2. Quantization – The result of sampling is a series of pulses with amplitude
values between the maximum and minimum amplitudes of the signal. The
set of amplitudes can be infinite with non-integral values between two
limits. The following are the steps in Quantization:
1. We assume that the signal has amplitudes between Vmax and Vmin
 2. We divide it into L zones each of height d where, d= (Vmax- Vmin)/ L

3. The value at the top of each sample in the graph shows the actual
amplitude.
4. The normalized pulse amplitude modulation(PAM) value is calculated
using the formula amplitude/d.
5. After this we calculate the quantized value which the process selects
from the middle of each zone.
6. The Quantized error is given by the difference between quantized
value and normalised PAM value.
7. The Quantization code for each sample based on quantization levels at
the left of the graph.
3. Encoding – The digitization of the analog signal is done by the encoder.
After each sample is quantized and the number of bits per sample is
decided, each sample can be changed to an n bit code. Encoding also
minimizes the bandwidth used. Note that the number of bits for each
sample is determined from the number of quantization levels. If the
number of quantization levels is L, the number of bits is n bit = log 2 L.
b. DELTA MODULATION
Since PCM is a very complex technique, other techniques have been
developed to reduce the complexity of PCM. The simplest is delta
Modulation. Delta Modulation finds the change from the previous
value. Modulator – The modulator is used at the sender site to create a
stream of bits from an analog signal. The process records a small positive
change called delta. If the delta is positive, the process records a 1 else the
process records a 0. The modulator builds a second signal that resembles a
staircase. The input signal is then compared with this gradually made

staircase signal.
We have the following rules for output:
1. If the input analog signal is higher than the last value of the staircase
signal, increase delta by 1, and the bit in the digital data is 1.
2. If the input analog signal is lower than the last value of the staircase
signal, decrease delta by 1, and the bit in the digital data is 0.
Demodulator – The demodulator takes the digital data and, using the
staircase maker and the delay unit, creates the analog signal. The created
analog signal, however, needs to pass through a low-pass filter for
smoothing.
c. ADAPTIVE DELTA MODULATION
The performance of a delta modulator can be improved significantly by
making the step size of the modulator assume a time-varying form. A larger
step-size is needed where the message has a steep slope of modulating
signal and a smaller step-size is needed where the message has a small
slope. The size is adapted according to the level of the input signal. This
 method is known as adaptive delta modulation (ADM).

Applications
• Digital Signal Processing: In this process, the systems for processing,
storing, or transporting almost any analogue signal into digital format
require ADCs to perform well. Let’s an example, in TV tuner cards this is
use as fast video analog-to-digital converters.
• Recording Music System: The modern digital audio workstation-based
sound recording and music reproduction technologies both are basically
rely heavily on analog-to-digital converters.
• Scientific Instruments or Projects: The digital imaging systems are
normally use analog-to-digital converters for digitizing the instruments and
projects pixels.

Digital to Analog Conversion

Last Updated : 12 Mar, 2024

•
Digital Signal –
A digital signal is a signal that represents data as a sequence of discrete values; at
any given time it can only take on one of a finite number of values.
Analog Signal –
An analog signal is any continuous signal for which the time varying feature of
the signal is a representation of some other time varying quantity i.e., analogous
to another time varying signal. The following techniques can be used for Digital
to Analog Conversion:
1. Amplitude Shift keying –
Amplitude Shift Keying is a technique in which carrier signal is analog and data
to be modulated is digital. The amplitude of analog carrier signal is modified to
reflect binary data. The binary signal when modulated gives a zero value when
the binary data represents 0 while gives the carrier output when data is 1. The
frequency and phase of the carrier signal remain constant.

Advantages of amplitude shift Keying –

• It can be used to transmit digital data over optical fiber.
• The receiver and transmitter have a simple design which also makes it
comparatively inexpensive.
• It uses lesser bandwidth as compared to FSK thus it offers high bandwidth
efficiency.
Disadvantages of amplitude shift Keying –
• It is susceptible to noise interference and entire transmissions could be lost
due to this.
• It has lower power efficiency.
2. Frequency Shift keying –
In this modulation the frequency of analog carrier signal is modified to reflect
binary data. The output of a frequency shift keying modulated wave is high in
frequency for a binary high input and is low in frequency for a binary low input.
The amplitude and phase of the carrier signal remain constant.

Advantages of frequency shift Keying –

• Frequency shift keying modulated signal can help avoid the noise problems
beset by ASK.
• It has lower chances of an error.
• It provides high signal to noise ratio.
• The transmitter and receiver implementations are simple for low data rate
application.
Disadvantages of frequency shift Keying –
• It uses larger bandwidth as compared to ASK thus it offers less bandwidth
efficiency.
• It has lower power efficiency.
3. Phase Shift keying –
In this modulation the phase of the analog carrier signal is modified to reflect
binary data.The amplitude and frequency of the carrier signal remains constant.
It is further categorized as follows:
1. Binary Phase Shift Keying (BPSK): BPSK also known as phase reversal
keying or 2PSK is the simplest form of phase shift keying. The Phase of the
carrier wave is changed according to the two binary inputs. In Binary Phase
shift keying, difference of 180 phase shift is used between binary 1 and binary
0. This is regarded as the most robust digital modulation technique and is
used for long distance wireless communication.
2. Quadrature phase shift keying: This technique is used to increase the bit
rate i.e we can code two bits onto one single element. It uses four phases to
encode two bits per symbol. QPSK uses phase shifts of multiples of 90
degrees. It has double data rate carrying capacity compare to BPSK as two bits
are mapped on each constellation points.
Advantages of phase shift Keying –
• It is a more power efficient modulation technique as compared to ASK and
FSK.
• It has lower chances of an error.
• It allows data to be carried along a communication signal much more
efficiently as compared to FSK.
Disadvantages of phase shift Keying –
• It offers low bandwidth efficiency.
• The detection and recovery algorithms of binary data is very complex.
• It is a non coherent reference signal.
•
 Difference Between Digital And Analog System
Last Updated : 21 Aug, 2024

•
Analog and digital signals are used to transmit information (such as any audio or
video), usually through electric signals. In digital technology, the translation of
information is into binary format (either 0 or 1) and information is translated into
electric pulses of varying amplitude in analog technology.
What is a Digital System?
A digital system is one whose signal has a finite number of discrete values. So, the
digital system works on digital signals and is limited to binary values 0 or 1. Digital
systems are used to process information in digital form. The digital system has
wide applications in digital instruments like calculators, computers, Telephones,
etc.

Digital Signal used in Digital System

Features of Digital Systems

• Uses Binary Code: Digital systems use binary code, which is a combination of
zeros and ones, to represent information.
• Accuracy: Digital systems are more accurate than analog systems because the
information is represented in a precise and consistent manner.
• Processing Speed: Digital systems are capable of processing large amounts
of data quickly and accurately.
• Noise Immunity: Digital systems are immune to noise and interference,
which means that the transmitted information is less likely to be corrupted.
What is Analog System?
Analog system is one that uses continous time signal or analog signal which is
a sinusoidal waveform. Analog system transmits the output in their raw form
reducing the time of translation. The amplitude of the signal varies continuously
with the time. Analog signals are used to represent sound, temperature, light
intensity etc.

Features of Analog Systems

• Uses Continuous Signals: Analog systems use continuous signals to
represent information, such as electrical voltages or sound waves.
• Real-World Representation: Analog systems are better suited for
representing real-world phenomena such as sound and light, which are
continuous in nature.
• Smooth Transitions: Analog systems provide smooth and continuous
transitions between different values, which can be important in certain
applications such as music or video.
• Complexity: Analog systems can be more complex than digital systems due to
the need for additional circuitry to process and transmit the signals.
Similarities Between Digital and Analog Systems
• Both can be used to process and transmit information.
• Both can be used in a variety of applications such as audio, video, and
telecommunications.
• Both can be used in combination with each other to achieve certain goals,
such as using digital signal processing to enhance analog signals.
• Both require some level of circuitry or hardware to function.
Difference Between Digital And Analog System
Analog System Digital System

Analog signal represents Digital signals are discrete and

Signal
physical measurements. generated by digital modulation.

Waves Sine Waves Square Waves

Continuous range of values to Uses discrete values to represent

Representation
represent information information

Samples analog waveforms into a

Records waveforms as they
Technology limited set of numbers and then
are.
records them.

Affected by noise during

Data Noise-immune during transmission
transmission and write/read
transmissions and write/read cycle.
cycle.

Response to
More likely to get affected Less likely to get affected
Noise

Flexibility Hardware is not flexible. Hardware is flexible.

More bandwidth to carry out the

Bandwidth Less bandwidth.
same information

Stored data in the form of Stored data in the form of binary

Memory
wave signal bit

Power Consumes large power Consumes negligible power

 Analog System Digital System

Best suited for audio and video Best suited for Computing and
Uses
transmission. digital electronics.

Cost Cost is low Cost is high

Human voice in air, analog

Example Computers, CDs, DVDs,
electronic devices.

LMN – Digital Electronics

• Note: NAND and NOR gates are called UNIVERSAL GATES because all other
gates can be constructed from any of them.
K-map example of 3 variables: : F(A,B,C)=π(0,3,6,7)

From red group we find terms

A B C’
Taking complement of these two
A’ B’ C
Now sum up them
(A’ + B’ + C)
From green group we find terms
B C
Taking complement of these two terms
B’ C’
Now sum up them
(B’+C’)
From brown group we find terms
A’ B’ C’
Taking complement of these two
A B C
Now sum up them
(A + B + C)
We will take product of these three terms :Final expression (A’ + B’ + C) (B’
+ C’) (A + B + C)

Number of NAND or NOR gate required to implement other GATE:

Combinational circuits: In combinational circuits, output depends on

present input only; it does not require any feedback and memory.

Multiplexer : It selects the input from one of many input lines and sends it
single output line. The input line chosen from output is based upon set of
selection lines.For 2n input lines, there will be n select lines and 1 output
lines.
Note: No. of mux required to implement n x 1 mux using m x 1 mux is ceil(n-
1 / m-1)A⊕B.
No. of mux required to implement 16 x 1 mux using 4 x 1 mux is ceil(15/3)=5.
Demultiplexer: It selects the input from one input line and sends it to one
out of many output lines. The output line chosen is based upon set of
selection lines. For 1 input lines, there will be n select lines and 2 n output
lines.
Note: No. of mux required to implement 1 x n mux using 1 x m mux is ceil(n-
1 / m-1)A⊕B.
No. of mux required to implement 1 x 16 mux using 1 x 4 mux is ceil(15/3)=5.
Encoder: For 2n input lines, it has n output. It can be used to convert octal or
hexadecimal to binary data.
Decoder: For n input lines, it has either 2 n outputs or less then that. It can be
used to convert binary data to other codes like octal or hexadecimal.
Code Converter: Code converters are used to convert one type of code to
others.
• BCD to Excess-3: It will add 0011(value 3) to binary code.
Function:
4 bit Input(ABCD) with A as MSB and 4 bit output(WXYZ) with W as MSB,
O/P is
Z=D’
Y=CD + C’D’
X=B’D + B’C + BC’D’
W=A + BC + BD
• Binary to Gray Converter
Function:
4 bit Input(B3B2B1B0) with B3 as MSB and 4 bit output(G 3G2G1G0) with G3 as
MSB, O/P is
G3=B3
G2=B3⊕ B2
G1=B2⊕ B1
G0=B1⊕ B0
• Gray to Binary Converter
Function:
4 bit Input(G3G2G1G0) with G3 as MSB and 4 bit output(B3B2B1B0) with B3 as
MSB, O/P is
B3=G3
B2=B3⊕G2
B1=B2⊕G1
B0=B1⊕G0
Flip-Flops: Flip-Flop are sequential circuits where O/P depends on present input as
well as previous output.
S-R Flip-Flops:

Characteristics equation: Qn = S + R̄ Qn
J-K Flip-Flops:

Characteristics equation: Qn = J Q̄n + R̄ Qn

D Flip-Flops:

Characteristics equation: Qn+1 = D

T Flip-Flops:

Characteristics equation: Qn+1 = T Q̄n + T̄ Qn

Counters is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal.
Counters are basically divided into two types:
Asynchronous counter: In asynchronous counter we don’t use universal clock, only
first flip flop is driven by main clock and the clock input of rest of the following
counters is driven by output of previous flip flops.
Synchronous counter: Unlike the asynchronous counter, synchronous counter has one
global clock which drives each flip flop so output changes in parallel. The one
advantage of synchronous counter over asynchronous counter is, it can operate on
higher frequency than asynchronous counter as it does not have cumulative delay
because of same clock is given to each flip flop.
Important point: Number of flip flops used in counter are always greater than equal
to (log2 n) where n=number of states in counter.