Combinational

Logic
For Students, Professionals
and Beyond
eBook 21

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 Combin ation a l Logic

TABLE OF
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 Combin ation a l Logic

1. Boolean Algebra – This forms the algebraic expression showing the operation
1. Introduction of the combinational circuit for each input variable either true or false which will
result in a logical-1 (HIGH) output condition.
The operation of digital circuits is based around the various laws of Boolean Algebra using
digital logic functions such as AND, OR and NOT. As such, these three logical functions 2. Truth Table – A truth table defines the function of the circuit by providing a
are the basic building blocks of all digital circuits which themselves, can be combined or concise list that shows all the output states in tabular form for each possible
connected together to form much more complex switching circuits. combination of input variable which could be encountered.

Each AND, OR, or NOT switching element can have one or more input variables but 3. Logic Diagram – This is a graphical representation of a logic circuit which shows
generally, only one single output. Thus the operation of each element or logic gate can be the wiring and connections of each individual logic gate, represented by a specific
presented by a truth table listing all the possible combinations of input variables and its graphical symbol, that implements the logic circuit.
resulting output state as a direct result of its input conditions. All three of these logic circuit representations are shown in Figure 1.
These three switching elements can therefore be classed as combinational devices, since
Figure 1. Combinational Logic Circuit
their output state depends only on the current state of their inputs. Note that the input
variables come from external sources, while the corresponding output state is produced Logic Gates
internally by the combinational logic circuit itself. A (AB) Boolean Expression
External B Q = (AB)(A+B)C
Then a Combinational Logic Circuits output is Inputs
Combinational logic circuits C C
dependant at all times on the combination of its Output (Q)
output is dependent only on
inputs meaning that it is memoryless. That is, it has
the state of its actual inputs
no knowledge of any previous events. C B A Q
since it has no feedback loops (A+B)
0 0 0 0
So if the condition of an input changes state, from Logic Diagram 0 0 1 0
0-1 or 1-0, so too will the resulting output since by default, combinational circuits have no 0 1 0 0
memory or feedback loops within their design. Typical 0 1 1 0
Truth Table 1 0 0 1
Thus combinational (or non-regenerative) logic circuits have the property that at any 1 0 1 0
point in time, their output is directly related to their current input condition following 1 1 0 0
some Boolean expression since they use digital logic gates. 1 1 1 0

By combining together different digital logic gates, we can create an endless number of Since combinational logic circuits are made up from individual logic gates only, they
possible combinations depending on the application. As a result, combinational logic can also be considered as being “decision making circuits”. Combinational logic is about
circuits can be very simple or very complicated circuits with the three main ways of combining logic gates together to process two or more input signals in order to produce
specifying the function of any combinational logic circuit given as follows: at least one output state according to the logical function of each logic device.

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 Combin ation a l Logic

Common combinational circuits made up from individual logic gates that carry So if a 2-to-4-line decoder has two inputs, it will choose or select one of its four (22)
out a desired application can include: multiplexers (selectors) and de-multiplexers outputs depending upon which input combination is present. An example of a 2-to-4-line
(distributors), encoders and decoders, adders and subtractors, and/or comparators, etc. decoder along with its truth table is given in Figure 3.

Figure 3. A 2-to-4 Binary Decoder

2. The Binary Decoder A B A B
AND Gate
Decoding is the process of converting some form of digital code, where the input and Inverter
A Q0 = AB
output codes are different, such as Binary, BCD, or Hexadecimal into a singular active
output representing its numeric value. Then, decoders translate or decode digital
information from one format into another based upon a given combination of actual Binary Q1 = AB
inputs and as such, are a commonly used combinational logic circuit. Inputs Decoded
Outputs
The basic Binary Decoder is nothing more than a simple combinational circuit made Q2 = AB
B
using standard AND, OR and NOT gates to convert binary information from n-bit input
lines to a maximum of 2n individual output lines, one for each element of information.
Q3 = AB
For example, a 74LS138, 3-to-8-line (3-to-23) decoder will have three inputs and eight
output lines. While the 74LS154, 4-to-16-line (4-to-24) decoder will have four inputs and Data Lines
sixteen individual output lines, etc. as shown in Figure 2.
Truth Table
Inputs Outputs
Figure 2. A 3-to-8 and 4-to-16 Decoder Block Diagram B A Q0 Q1 Q2 Q3
A Q0
0000 0000 0 D0
2-to-4 Q1 0 0 1 0 0 0
0001 A 20 0 D0 0001 A 20 B Binary
1 D1 Q2 0 1 0 1 0 0
0010 1 1 D1 0010
2 D2 Decoder
0011 B 2 2 D2 0011 B 21 Q3 1 0 0 0 1 0
0100 0100 3 D3
C 22
3 D3 C 22 4 D4 1 1 0 0 0 1
0101 0101
0110 4 D4 0110 3 5 D5
D 2
0111 74LS138 5 D5 0111 6 D6
1000 3-to-8 6 D6 1000 7 D7 Figure 3. shows that a basic binary decoder can be easily implemented using four 2-input
1001 8 D8
Decoder 7 D7 1010 AND gates and two NOT gates. If the input is 00 (A = 0 and B = 0), output Q0 would be
9 D9
1011
10 D10 present. If the input is 01 (A = 0 and B = 1), output Q1 would be present and so on.
1100
1101 11 D11
1111 74LS154 12 D12 Thus, for any combination of inputs, only one output will be HIGH (assuming positive
4-to-16
13 D13 logic) at any one time while all the other outputs will be LOW (logic level-0).
14 D14
Decoder 15 D15

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 Combin ation a l Logic

Since NAND gates are cheaper to make than AND gates (require fewer transistors to If we want to display these numbers using a seven-segment display, we need a decoder
implement), NAND based decoders can also be constructed which produce a LOW output which will light up the appropriate segments of the display. The input to the BCD to
that corresponds to the actual input condition while all the other outputs will be HIGH as 7-segment decoder uses 4-bits in a binary-coded-decimal (BCD) format, where decimal
shown in Figure 4. 0 is represented by the four binary functions ABCD = 0000. Decimal 1 is represented
by ABCD = 0001, 2 by 0010, 3 by 0011, and so on through to 9 = 1001. Note that other
Figure 4. A NAND 2-to-4 Binary Decoder decimal codes are also possible.
A B A B
NAND Gate Thus BCD to 7-segment decoders such as the TTL 74LS47 or 74LS48, have 4 BCD inputs
Inverter and 7 output lines, one for each LED segment. The 74LS47 decoder/driver for driving
A Q0 = AB common-anode displays. While its cousin, the 74LS48 is used for driving common-
Truth Table cathode displays.
Binary Q1 = AB B A Q0 Q1 Q2 Q3
Inputs
Figure 5 shows a block diagram of a typical decoder, the display element, and the way the
0 0 0 1 1 1
segments should be driven to represent the appropriate digit along with the truth table.
0 1 1 0 1 1
B Q2 = AB 1 0 1 1 0 1 Figure 5. BCD to 7-segment Display Decoder
1 1 1 1 1 0
a a
Q3 = AB A
BCD B b
Input BCD c Truth Table
Data Lines f b
Signal C to
d g
D 7-Segment D C B A a b c d e f g
Decoder e
The NAND gate decoder’s outputs are classed as active-low and are commonly used for e 0 0 0 0 1 1 1 1 1 1 0
f c 0 0 0 1 0 1 1 0 0 0 0
microprocessor address decoding since most memory and microprocessor peripheral d
g 0 0 1 0 1 1 0 1 1 0 1
chips use active-low enable signals.
0 0 1 1 1 1 1 1 0 0 1
a a a 0 1 0 0 0 1 1 0 0 1 1
Then as we have seen, a digital decoder selects only one output at a time and are used in b b f b
f b b 0 1 0 1 1 0 1 1 0 1 1
applications such as data multiplexing, display and memory address decoding. g g g 0 1 1 0 0 0 1 1 1 1 1
e c c c c c 0 1 1 1 1 1 1 0 0 0 0
2.1 BCD to 7-segment Display Decoders d d d 1 0 0 0 1 1 1 1 1 1 1
a a a a a 1 0 0 1 1 1 1 1 0 1 1
7-segment displays can be used for displaying a single binary digit, or connected together
f f b f b f b
to display whole numbers. An LED display consists of seven light emitting diode (LED) g g g g
segments producing each of the 10 decimal digits, 0 through 9. Depending on the type c e c c e c c
of display, common-cathode or common-anode, each segment (a through g) can be d d d d
activated by either a HIGH or LOW voltage level.
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 Combin ation a l Logic

(logic-1) simultaneously, the resulting output from the encoder is neither at 01 or at 10,
3. The Binary Encoder but instead will be at 11 which does not represent either binary 1 or binary 2. Also, an
output code of all logic level 0’s can be generated when all of its inputs are at 0, or when
Encoding is the opposite process of decoding. An encoder is a combinational circuit used
input D0 is equal to one.
to generate a coded output (such as BCD, binary or HEX) from a singular active numerical
input line. That is, a Binary Encoder takes the logical state of ALL of its input lines and One simple way to overcome this problem is to “Prioritise” the level of each input pin. So
converts them into a single encoded representation of these inputs on its output lines. if there is more than one input at logic level-1 at the same time, the actual output code
would only correspond to the input with the highest designated priority. Then this type of
Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes, etc. depending
digital encoder is known commonly as a Priority Encoder.
upon the number of data input lines to be converted. So, an “n-bit” binary encoder will
have 2n input lines resulting in n-bit output lines. Common types of digital encoders 3.1 Priority Encoders
include 4-to-2, 8-to-3 and 16-to-4 line configurations.
The TTL 74LS148 is a 8-to-3 line decimal to binary Priority Encoder which means that
For example, a 10-to-4 decimal to binary encoder of Figure 6. takes a 10-digit (0 to 9) if two or more inputs are present, the highest numeric input will have priority and be
input combination and outputs a 4-bit code representing the bit state of the input signal encoded to the output. In other words, it produces a BCD output according to highest-
line which is HIGH (assuming positive logic). order decimal digit present on the input as shown in Figure 7.
Figure 6. 4-bit Decimal to Binary Encoder Figure 7. 3-bit Decimal to Binary Priority Encoder
Lowest Priority BCD Decimal Inputs Outputs
D0 Output D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
D1 Q0 0 0 0 0 0 0 0 1 0 0 0
D2 8-to-3 Q1 0 0 0 0 0 0 1 x 0 0 1
D3 Priority 0 0 0 0 0 1 x x 0 1 0
Q2 0 0 0 0 1 x x x 0 1 1
D4 Encoder
74LS148 0 0 0 1 x x x x 1 0 0
D5 0 0 1 x x x x x 1 0 1
D6 0 1 x x x x x x 1 1 0
D7 1 x x x x x x x 1 1 1
Highest Priority X = dont care

Thus, if input lines D2, D3 and D5 are applied simultaneously the output code would be for
input D5 (101), since this has the highest numerical value from the 3 inputs. Once input D5
One of the main disadvantages of standard digital encoders is that only one input can had been removed the next highest output code would be for input D3 (011), and so on
be active at any given time, or else it will generate the wrong output code when there is until one of the inputs between D4 to D7 takes priority.
two or more logic level-1 inputs present. For example, if we make inputs D1 and D2 HIGH

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Priority encoders such as the 74HC923, is a 20-key encoder for use in microprocessor, In digital electronics, multiplexers are also referred to as Data Selectors because they
micro-controller and computer systems to handle keyboard and peripheral interrupt can “select” each input line. They are commonly constructed from individual MOSFET
signals responding to the highest priority pending interrupt request (IRQ). Positional switches encased in a single IC package.
Encoders are another form of priority encoder used for the positional control of robotic Generally, the selection of each input line in a multiplexer is controlled by an additional
arms or steering mechanisms, etc. set of inputs called control or select lines to determine which input data line should
be connected directly to the output. We can build a simple 2-line to 1-line (2-to-1)
4. The Multiplexer multiplexer using basic logic NAND gates as shown in Figure 9.
Figure 9. Basic 2-input Multiplexer Using NAND Gates
Multiplexing is the generic term used to describe the operation of sending one or more
Input I0
analogue or digital signals over a common transmission line at different times or speeds. I0 NAND
The electronic device used to do this is called a Multiplexer, or MUX. Gates
A
The multiplexer is a combinational logic based fast acting multiple position rotary switch Select Output
connecting or controlling multiple input lines called channels. It is designed to select one A Q
of several input lines, one at a time, and channel the data through to a single common A
output line. That is, a multiplexer may have 2n data input lines, but only one output. Input Inputs
I1
The most basic example of multiplexing is that of a one-way rotary switch as shown in I1 A I1 I0 Q
Figure 8. 0 0 0 0
Truth
SPDT Table
0 0 1 0
Figure 8. Basic Multiplexing Switch I0
0 1 0 1
Q 0 1 1 1
I1 1 0 0 0
I0 Single-pole
Double-throw 1 0 1 1
I1 A 1 1 0 0
Multiple Data Switch Analogy
I2 Q 1 1 1 1
Input Lines
One Single
Data Output Line
Input A of this simple 2-1 line multiplexer circuit is used to control which input (I0 or I1)
I(n) gets passed to the output at Q.
The truth table of Figure 9, shows that when the data select input, A is LOW, input I1 is
Data Selection
connected to the output, while input I0 is blocked. When the data select A is HIGH, the
(Rotary Switch)
reverse happens and now input I0 is connected to the output while input I1 is blocked.
In the example of Figure 8. the rotary switch can select any one of the individual data or So by the application of either a logic-0 or a logic-1 at A, we can select the appropriate
signal lines from I0 to I(n) connecting the input directly to the output. input, I0 or I1 with the circuit acting a bit like a single-pole double-throw (SPDT) switch.
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 Combin ation a l Logic

Since we only have only one control line (A), we can only switch 21 inputs to the common Figure 10. shows that at any one instant in time only ONE of the four input lines A to D
output. Thus producing a 2-to-1-line multiplexer and we can confirm this using the is connected to the single output at Q. As to which switch is closed depends upon the
following Boolean expression. addressing input code on lines “a” and “b“. So for this example to select input B to the
Q = A.I1 + A.I0 output at Q, the binary input address would need to be: select a = logic-1 and b = logic-0.
Then we can show the selection of the data through the multiplexer as a function of the
If we increase the number of data inputs to be selected by simply following the same data select bits as given in Figure 11.
procedure, larger multiplexer circuits can be implemented using a 2-to-1 multiplexer as
their basic building blocks. So for example, a 4-input multiplexer we would require two Figure 11. Multiplexer Input Line Selection
data select lines as 4-inputs represents 22 data control lines give a circuit with four inputs, A A A A
I0, I1, I2, I3 and two data select lines A and B as shown in Figure 10. B Q B Q B Q B Q
C C C C
Figure 10. 4-channel Multiplexer Circuit D b a D b a D b a D b a
A 0 0 0 1 1 0 1 1

NAND Clearly, adding more control address lines, (n) will allow the multiplexer to control more
Gates inputs such as the TTL 74LS151 8-to-1 or the TTL 74LS153 Dual 4-to-1 line multiplexer.
B
But remember, each control line configuration will only connect ONE input to the output.
Data
Inputs Q = abA + abB + abC + abD Multiplexers are not just limited to switching 2n input lines or channels to one common
C single output. There are also types that can switch their inputs to multiple outputs and
Select Inputs Output have arrangements or 4-to-2, 8-to-3 or even 16-to-4 line configurations.
b a D C B A Q
D 0 0 x x x 1 1 5. The Demultiplexer
0 1 x x 1 x 1
b 1 0 x 1 x x 1 The Demultiplexer, or DeMUX is another combinational logic based multiple positional
b 1 1 1 x x x 1 switch used to route analogue or digital signals, and is by design, the exact opposite of
Channel Truth Table the previous multiplexer circuit.
Select A
a B The demultiplexer, also known as a Data Distributor takes one single input data line
a Q and switches it to one of a number of individual output lines one at any one time, in
C Switch Analogy accordance with the binary number applied to the channel select lines.
D (4PST)
That is, a demultiplexer connects a single input line to one of 2n output lines , depending
ab
on the values of n select lines.
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 Combin ation a l Logic

The most basic example of demultiplexing is that of the switching circuit in Figure 12. As with the previous multiplexer, the individual solid state switches are selected by the
binary input address code on the output select pins a and b as shown in Figure 14.
Figure 12. Basic Demultiplexer Switch
Figure 14. Demultiplexer Output Line Selection
A

B A A A A
Common Data F B F B F B F B
Input
F Outputs C C C C
C
b a D b a D b a D b a D
D
0 0 0 1 1 0 1 1
Channel a Switch
Select b Control Standard Demultiplexer IC packages available are the TTL 74LS138 1-to-8 demultiplexer,
the TTL 74LS139 Dual 1-to-4 demultiplexer or the CMOS CD4514 1-to-16 demultiplexer.
The implementation of the of the above circuit can be achieved using individual AND and
NOT logic gates as shown in Figure 13. Another type of demultiplexer is the 24-pin, 74LS154 which is a 4-bit to 16-line
demultiplexer and decoder. Here the individual output positions are selected using a 4-bit
Figure 13. 4-channel Demultiplexer Circuit
binary coded input. Like multiplexers, they can also be cascaded together to form higher
Switch Analogy
(4PST)
A order devices and by adding more channel select inputs it is possible to switch more
B outputs giving a 1-to-2n data line outputs.
a a F
C
b
D 6. The Binary Half-Adder
b AND Gate ab
F Combinational logic circuits can also be configured to perform arithmetic and logical
A = abF operations such as Binary Addition which can be implemented using basic logic gates.
Truth Table In conventional mathematics, two or more decimal or denary (base-10) numbers can be
Select Outputs B = abF added together to give their sum value. For example, consider the addition of the two
b a D C B A numbers in Figure 15.
0 0 x x x 1 Figure 15. Addition of Two Denary Numbers
0 1 x x 1 x C = abF
1 0 x 1 x x 123 A (Augend) Here, number A (the augend) value of 12310 is added to
1 1 1 x x x 45610 (the addend) value of number B to produce the
D = abF + 456 B (Addend) SUM value of 57910. We add together starting from the
579 SUM right hand side knowing that each digit has a weighted
Note, if input F is permanently connected to a logic level-1, can be used as a decoder. value depending upon its position within the columns.

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 Combin ation a l Logic

A Carry or carry-over number is generated if the addition of a column results in a number But you may have noticed something else with regards to the addition of these two
equal to, or greater than 10 (the Base number). This carry number is automatically added bits, the resulting sum of their binary addition 0, 1, 1, 0, matches the output state of an
to the numbers within next column. Then the addition of denary numbers is simply, add Exclusive-OR gate as shown in Figure 18.
the numbers and produce a carry.
Figure 18. 2-input Exclusive-OR gate and Truth Table
The adding of binary numbers is exactly the same idea as that for adding together two or
more decimal (denary) numbers except in binary there are only two digits with the largest Symbol Truth Table
digit being 1. When adding binary numbers, a carry or carry-over is generated when the B A S
SUM value of any column is equal to, or is greater than 2, (the base number of binary).
A 0 0 0
The addition of two base-2 digits is relatively simple since the addition of: 0 + 0 = 0, 0 + 1 B
=1 S
0 1 1
= 1, 1 + 0 = 1, resulting in either a 0 or a 1 until we get to the addition of 1 + 1 in which the
sum is equal to 10 (1,0 NOT TEN). That is: 1 + 1 = 10, which is a base-2 (102 = 210) value. 1 0 1
2-input Ex-OR Gate Symbol
1 1 0
But the number two does not exist in binary only 0 and 1. However, 2 in binary is equal
to 10, a zero for the sum plus an extra carry bit. In other words, 1 + 1 creates a “CARRY” as An Exclusive-OR gate only produces a logic-1 output when EITHER inputs are at logic-1.
shown in Figure 16. Then we need an additional output to produce the required CARRY bit when BOTH inputs
A and B are at logic-1. One digital logic gate that fits the bill perfectly producing a logic-1
Figure 16. Binary Addition of Two Bits
output when both of its inputs are HIGH (1) is the standard AND Gate.
0 0 1 1 By combining the Exclusive-OR gate with an AND gate results in a simple digital binary
+0 +1 +0 +1 adder circuit known commonly as a Half Adder circuit as shown in Figure 19.
0 1 1 (carry) 1 ← 0 Figure 19. 2-input Half-adder and Truth Table
Then the operation of a simple adder requires two data inputs producing two individual Symbol Truth Table
outputs, the Sum (S) of the equation and a Carry (C) bit as shown in Figure 17.
B A SUM CARRY
A
Figure 17. Binary Adder Block Diagram B
=1 Sum 0 0 0 0
Inputs Outputs Note that for the simple 1-bit addition 0 1 1 0
problem above, the resulting carry bit
A SUM (S) & Carry 1 0 1 0
Binary could be ignored if not needed.
Adder 1 1 0 1
B CARRY (C)

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 Combin ation a l Logic

From the truth table of the half adder in Figure 19. we can see that the SUM (S) output is Since the full-adder circuit of Figure 20. is basically two half-adders connected together,
the result of the Exclusive-OR gate and that the CARRY (C) is the result of the AND gate. the truth table for the full-adder includes an additional column to take into account the
Then the Boolean expression for the Half Adder circuit of Figure 19. is given as: Carry-in input as well as the SUM output, (S) and the Carry-out bit as shown in Figure 21.

For the SUM bit: SUM (S) = A XOR B = A ⊕ B Figure 21. Full-adder and Truth Table

For the CARRY bit: CARRY (C) = A AND B = A.B Symbol Truth Table

One major disadvantage of the half-adder circuit when used for binary addition, is that Carry-In B A SUM Carry-Out
while it can produce a Carry-out (C-out) bit. There is no provision for a Carry-in from a 0 0 0 0 0
previous circuit when adding together multiple data bits. One simple way to overcome
A 0 0 1 1 0
this problem is to use what is called a Full Adder for binary addition.
B SUM
CIN
0 1 0 1 0
7. The Binary Full-Adder 0 1 1 0 1
COUT
1 0 0 1 0
The Full Adder is a combinational logical circuit that performs binary addition on its
inputs. A full-adder has three inputs. The same two single bit data inputs A and B as
1 0 1 0 1
before plus an additional Carry-in (C-in) input to receive the carry bit from a previous 1 1 0 0 1
stage, and just like the half-adder, it produces a carry-out bit to the next addition column.
1 1 1 1 1
Then in many ways, the full-adder circuit can be thought of as two half-adders connected
together, with the first half-adder passing its carry to the second half adder as shown in Then the Boolean expression for a Full-adder of Figure 21 is given as follows:
Figure 20.
For the SUM bit: SUM = CIN XOR (A XOR B) = CIN ⊕ A ⊕ B
Figure 20. Full-Adder Representation
For the CARRY-OUT bit: COUT = CIN(A XOR B) OR (A AND B) = CIN(A ⊕ B) + A.B
Half Adder Half Adder Then, Binary Adders are combinational logic circuits which can be used to “add” together
A⊕B CIN⊕(A⊕B) Sum
A SUM SUM two binary numbers producing a SUM and Carry-out bits. 4-bit full-adder circuits with
CIN(A⊕B) carry look ahead features such as the TTL 4-bit binary adder 74LS83 or the 74LS283 are
B A.B
CARRY CARRY available as standard IC packages to add together two 4-bit binary numbers and generate
the required SUM and a CARRY bits.
COUT
CIN
Full Adder

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 Combin ation a l Logic

However, we need an additional output to produce the required borrow bit when the
8. The Binary Half-Subtractor inputs are: X = 0 and Y = 1. Unfortunately there is no standard logic gate which could
If we can use combinational logic circuits to “add” together two or more binary digits, we produce an output for this particular combination of X and Y inputs.
must also be able to “subtract” two or more binary digits, and we can. Binary Subtractors But we know that a logic AND gate produces a logical-1 output when both of its inputs
are another decision making combinational logic circuit which can subtract two (or more) are HIGH (1). So if we use an inverter or NOT gate to complement input X before it is fed to
binary numbers from each other. For example, A – B. the AND gate. Then we could actually produce the required borrow output with the input
Whereas before the binary adder found the sum of two numbers, the binary subtractor conditions of X = 0 and Y = 1 as shown in Figure 23.
will produce the difference between the two numbers. Similar to the previous adder
circuit, the subtractor also produces two outputs. One called the DIFFERENCE and the Figure 23. Borrow Bit Creation
other called the BORROW (carry in the case of the adder). There are commonly two types NOT Gate AND Gate
of binary subtractor. The Half Subtractor and the Full Subtractor. X Boolean Expression
X
Inputs B = X.Y
Y
Binary Subtraction can take many forms but the rules for subtraction are the same Y Borrow
whichever process you use. As binary notation only has two digits, subtracting a “0” from Output
a “0” or a “0” from a “1”, leaves the result unchanged as 0-0 = 0 and 1-0 = 1. However,
subtracting a 1 from a 1 would result in a 0, but subtracting a 1 from a 0 would require a So by combining an Ex-OR gate to generate the Difference, with a NOT-AND combination
BORROW bit as shown in Figure 22. to generate the Borrow results in a simple digital binary subtractor circuit known
commonly as the Half Subtractor (HS), as shown in Figure 24.
Figure 22. Binary Subtraction of Two Bits
Figure 24. 2-input Half-subtractor and Truth Table
0 1 1 (borrow) 1 → 1 0
-0 -0 -1 -1 Symbol Truth Table
0 1 0 1 Y X DIFFERENCE BORROW
X
Difference 0 0 0 0
Y
Again, the operation of a simple subtractor requires two data inputs and two individual 0 1 1 0
outputs, the Difference (D) of the equation and a Borrow (B) bit. Note that to prevent
any confusion between a binary subtractor input labelled, B and the resulting borrow bit Borrow 1 0 1 1
output also being labelled, B. We shall now refer to the two data input bits as being X for 1 1 0 0
the minuend, and Y for the subtrahend.
Since the difference between the two input bits is only a logic-1 when the two inputs are We can see from the truth table of the half subtractor circuit of Figure 24. that the
not equal, and a logic-0 when equal. This gives us again the expression for our familiar DIFFERENCE (D) output is the result of the Exclusive-OR gate and the BORROW (B) is the
Exclusive-OR Gate which we can use for the DIFFERENCE output bit. result of the NOT-AND combination.

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 Combin ation a l Logic

Then the Boolean expression for a half subtractor is given as follows. Figure 26. Full-Subtractor Representation
For the DIFFERENCE bit: DIFFERENCE (D) = X XOR Y = X ⊕ Y Half Subtractor Half Subtractor
X⊕Y BIN⊕(X⊕Y) Difference
For the BORROW bit: BORROW (B) = not-X AND Y = X.Y X DIFFERENCE DIFFERENCE

X.Y BIN(X⊕Y)
Note that if we compare the Boolean expressions of the half subtractor with that of the Y BORROW BORROW
half adder, we can see that the two expressions for the SUM (adder) and DIFFERENCE
(subtractor) are exactly the same because of the Exclusive-OR gate function. BOUT
BIN
Full Subtractor
Also, the two Boolean expressions for the binary subtractors BORROW bit is very similar
to that for the adders CARRY. Then all that is needed to convert a half adder to a half Since the full subtractor circuit represents two half-subtractors cascaded together, the
subtractor is the inversion of the minuend input X. That is, X-Y = X+(2’s complement of Y). truth table for a full subtractor will have eight different input combinations. As there are
three input variables, two data bits and the Borrow-in bit as shown in Figure 27.
As before, one major disadvantage of the Half Subtractor circuit when used as a binary
subtractor, is that there is no provision for a “Borrow-in” from a previous circuit. Then we Figure 27. Full-subtractor and Truth Table
need to produce what is called a Full Binary Subtractor circuit.
Symbol Truth Table
9. The Binary Full-Subtractor Borrow-In Y X DIFF. Borrow-Out
0 0 0 0 0
A Full Subtractor circuit has three inputs. The two single bit data inputs X (minuend) and
Y (subtrahend) the same as before plus an additional Borrow-in (B-in) input to receive the X 0 0 1 1 0
borrow generated by the subtraction process from a previous stage as shown in Figure 25. Y DIFF
BIN
0 1 0 1 1
Figure 25. Binary Subtractor Block Diagram 0 1 1 0 0
X Difference Thus, the circuit of a full subtractor (FS) BOUT 1 0 0 1 1
D
Y Full performs the operation of subtraction on 1 0 1 0 0
Subtractor Borrow Out three binary bits producing outputs for the
BIN
BOUT difference D and borrow B-out. 1 1 0 0 1
1 1 1 1 1
Just like the binary adder circuit, the full subtractor can also be thought of as two half
subtractors connected together, with the first half subtractor passing its borrow to the
second half subtractor as shown in Figure 26. Then we can see that the full subtractor circuit of Figure 27. subtracts the two input bits
while taking into account the borrow bit.

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 Combin ation a l Logic

Then the Boolean expression for a full subtractor is as follows. The basic identity comparator evaluates two binary bits and outputs a 1 (HIGH) if they
are exactly equal. The easiest way to compare the equality of two binary bits is to use an
For the DIFFERENCE bit: DIFFERENCE (D) = BIN XOR (X XOR Y) = BIN⊕(X ⊕ Y) Exclusive-NOR (Ex-NOR) gate of Figure 28.

For the BORROW bit: BORROW (B) = not-X AND Y OR BIN.not-(X XOR Y) Figure 28. Exclusive-NOR Gate
= X.Y + BIN(X⊕Y) A Thus according to an Exclusive-NOR gates truth
S table, if both input bits are equal, either 0 - 0 or 1 - 1,
As with the binary adder, we can also have n number of 1-bit full binary subtractors B then it outputs a logic-1.
cascaded together to subtract two parallel n-bit numbers from each other. For example
two 4-bit binary numbers. So if we wanted to compare two (or more) data
bits, we would need additional Ex-NOR gates, with the output of all of them must be 1.
Since the only difference between a full adder and a full subtractor is the 1’s complement For example, to design a comparator to evaluate two data sets, A1 B1 with A2 B2, we can
inversion of one of its data inputs. We could use a 4-bit full-adder IC such as the 74LS283 connect the two Ex-NOR outputs into a 2-input AND gate as shown in Figure 29.
to perform subtraction since X – Y is basically the same as saying, X + (-Y) which is
effectively X plus the two’s complement of Y. Figure 29. Basic 2-bit Identity Comparator
A1 = 0 1 A1 = 1 1
10. The Digital Comparator B1 = 0
S=1
B1 = 1
S=1

A2 = 0 A2 = 1
If we can both add and subtract two binary numbers, we must also be able to compare B2 = 0 1 B2 = 1 1
them to see if they are equal. For example, is the value of input A greater than, smaller
than, or equal to the value at input B, and we can do this using a digital comparator. Thus if all four inputs (A1, B1, A2, B2) are either at logic 0 or logic 1, then the Ex-NOR outputs
The Digital Comparator is another arithmetic logic circuit that uses standard AND, NOR are 1’s, and the AND gate output is a 1 (HIGH), indicating equality. That is A1 = A2 and B1 =
and NOT gates to compare the digital signals present at its input terminals, producing an B2. Any other combination of inputs would result in the AND gate outputting a 0 (LOW).
output result depending upon the condition of those inputs. The Magnitude Comparator not only produces an output if A equals B but can produce
There are two main types of Digital Comparator available we can use and these are: two more outputs if A is greater than B, or A is less than B. This is useful if we want to
compare two variables and want to produce an output when any of the above three
1. Identity Comparator – an Identity Comparator is a digital comparator with only conditions are met.
one output terminal for when A = B, either A = B = 1 (HIGH) or A = B = 0 (LOW)
Thus, a simple 2-bit comparator which has two inputs (A, B) will have three outputs
2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which corresponding to: A <B, A =B, or A >B as sho wn in Figu re 30.
has three output terminals, one each for equality, A = B greater than, A > B and
less than A < B

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 Combin ation a l Logic

Figure 30. Basic 2-bit Magnitude Comparator comparator circuits to be “cascaded” together in order to compare binary words larger
than 4-bits with magnitude comparators of 8, 16 or even 32-bit words being produced.
A
A
C = AB A<B

End of this Combinational Logic eBook

D = AB+AB A=B
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Then the logical operation of a 2-bit digital comparator is given in Table 1.

Table 1. Magnitude Comparator Truth Table With the completion of this Combinational Logic eBook you should have gained a good
and basic understanding and knowledge of the various combinational logic circuits which
Inputs Outputs
can be constructed using AND, OR, NOT and Ex-OR gates. The information provided here
B A A>B A=B A<B should give you a firm foundation for continuing your study of electronics and electrical
0 0 0 1 0 engineering as well as the study of digital logic circuits.
0 1 1 0 0
For more information about any of the topics covered here please visit our website at:
1 0 0 0 1
1 1 0 1 0 www.electronics-tutorials.ws
Digital comparators commonly use Exclusive-NOR gates within their design for comparing
their respective pairs of bits. When we are comparing two binary or BCD values against Main Headquarters Central Europe/EMEA
each other, we are comparing the “magnitude” of these values, a logic-0 against a logic-1 245 Main Street Frankfurter Strasse 211
which is where the term Magnitude Comparator comes from. Cambridge, MA 02142 63263 Neu-Isenburg, Germany
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As well as comparing individual bits, we can also design larger multi-bit comparators by
cascading together n of these and produce a n-bit comparator. Multi-bit comparators can
be constructed to compare whole binary or BCD words to produce an output if one word
is larger, equal to or less than the other.
Commercially available digital comparators such as the TTL 74LS85 or CMOS 4063
4-bit magnitude comparators have additional input terminals to allow more individual

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