Roll Number:

KIET Group of Institutions

(Department of Computer Science & Engineering/Computer Science)
B.Tech, 3rd Semester
Pre-University Examination-1, (2020-21) Odd Semester
(Computer Organization and Architecture) (KCS-302)
Duration: 3 hrs Max. Marks: 100

Note: - Attempt all the Questions.

Section-A (10X2=20)
Q. No. Question Marks CO BL
a Draw Tri state buffer and tell the output states in accordance with input states. 2 1 2
b Define push and pull in stack organization. 2 2 1
c Which two are most popular method of binary division. 2 2 2
d How 2.5D is different from 2D memory organization. 2 4 1,2
e What is CAM? 2 4 1
f Calculate 128X8 RAM chips, needed to provide memory capacity of 2048 bytes. 2 3 3
1.
g Illustrate the term arithmetic pipeline. 2 3 3
h Determine infix notation from the given reverse polish notation: 2 2 4
A B C DE*/-+
i Design an array multiplier that multiplies two 2-bit numbers. Use AND 2 3 6
gate and binary adders.
j Convert decimal number 215.5 to base 8, and base 16 2 2 4

Section-B (5X6=30)
Q. No. Question Marks CO BL
Analyse flow chart for addition and subtraction for signed magnitude data.
2 OR 6 1 1,2
Describe various methods of Bus arbitration with their advantages and disadvantages.
Explain Carry look ahead adder with its block diagram.
OR 6 2 2,4
3
Draw the flow chart of Booth’s Algorithm for multiplication and show the multiplication
process using Booth’s Algorithm for (-7) *(+3). Use 6-bit register.
Describe the following organizations of cache memory: (i). Associative mapping
(ii). Direct Mapping (iii). Set associative mapping 6 4 2
4
OR
Explain Virtual Memory. Discuss, why is it necessary to implement virtual memory?
Compare complex instruction set computer and reduced instruction set computer.
6 3 3
5 OR
Compare horizontal microprogramming and vertical microprogramming.
Outline the block diagram of DMA controller. Illustrate, why are the read and write
control lines in a DMA controller bidirectional?
6 OR 6 5 2,4
Discuss types of Communication. List some difference between serial and parallel
communication.

Section-C (5X10=50)
Q. No. Question Marks CO BL
Discuss the various types of address mapping used in cache memory.
7 OR 10 4 2,4
Illustrate all the phases of instruction cycle.
Explain the concept of overflow, normalisation and biasing in floating point numbers.
Show (146.125)10 in single precision and double precision format.
OR
8 A bus-organized CPU which has 16 registers with 32 bits in each, an ALU, and a 10 2 2,4
destination
decoder. Solve the following:
a. How many multiplexers are there in the A bus, and what is the size of each
• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student learning
Page 1 of 2
 multiplexer?
b. How many selection inputs are needed for MUX A and MUX B?
c. How many inputs and outputs are there in the decoder?
d. How many inputs and outputs are there in the ALU for data, including input and output
carries?
e. Formulate a control word for the system assuming that the ALU has 35 operations
What is micro programmed control unit? Give the basic structure of micro programmed 1,2
control unit. Also discuss the microinstruction format and the control unit organization
for a typical micro programmed controller using suitable diagram. 10
9 3
OR
Explain the difference between vectored and non-vectored interrupt. Explain stating
examples of each.
A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer
system needs 2K bytes of RAM, 4K bytes of ROM and 4 interface units, each with 4
registers. A memory mapped configuration is used. The two highest order bits of the
address bus are assigned 00 for RAM, 01 for of the ROM and 10 for interface registers.
Evaluate the following-
(i) How many RAM and ROM chips are needed?
(ii) Memory address map for the system.
10 4 5
10 (iii) The address range in hexadecimal for RAM, ROM and interface.
OR
A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The
cache uses direct mapping with block size of four words. Evaluate the following-
(i). Number of bits in tag, index, block and word fields of the address format.
(ii). Number of bits in each word of cache, and how they are divided into functions?
Include a valid bit.
(iii). No of blocks can the cache accommodate
(i)Discuss the design of a typical input or output interface. 2,4
(ii)What are interrupts? how they are handled?
11 5
OR 10
Discuss different types of auxiliary memories.

• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student learning
Page 2 of 2
 Roll Number:
KIET Group of Institutions
(Department of Computer Science & Engineering/Computer Science)
B.Tech, 3rd Semester
Pre-University Examination-1, (2020-21) Odd Semester
(Computer Organization and Architecture) (KCS-302)
Duration: 3 hrs Max. Marks: 100

Note: - Attempt all the Questions.

Section-A (10X2=20)
Q. No. Question Marks CO BL
a Draw Tri state buffer and tell the output states in accordance with input states. 2 1 2
b Define Computer architecture. 2 2 1
c Which two are most popular method of binary division. 2 2 2
d How 2.5D is different from 2D memory organization. 2 4 1,2
e What is Associative memory? 2 4 1
f Calculate 128X8 RAM chips, needed to provide memory capacity of 4096 bytes. 2 3 3
1.
g Illustrate the term arithmetic pipeline. 2 3 3
h Determine infix notation from the given reverse polish notation: 2 2 4
A B C DE*/-+
i Design an array multiplier that multiplies two 2-bit numbers. Use AND 2 3 6
gate and binary adders.
j Convert decimal number 215.5 to base 8, and base 16 2 2 4

Section-B (5X6=30)
Q. No. Question Marks CO BL
Analyse flow chart for addition and subtraction for signed magnitude data.
2 OR 6 1 1,2
Describe various methods of Bus arbitration with their advantages and disadvantages.
Explain Carry look ahead adder with its block diagram.
OR 6 2 2,4
3
Draw the flow chart of Booth’s Algorithm for multiplication and show the multiplication
process using Booth’s Algorithm for (-7) *(+3). Use 6-bit register.
Describe the following organizations of cache memory: (i). Associative mapping
(ii). Direct Mapping (iii). Set associative mapping 6 4 2
4
OR
Explain Virtual Memory. Discuss, why is it necessary to implement virtual memory?
Compare complex instruction set computer and reduced instruction set computer.
6 3 3
5 OR
Compare horizontal microprogramming and vertical microprogramming.
Outline the block diagram of DMA controller. Illustrate, why are the read and write
control lines in a DMA controller bidirectional?
6 OR 6 5 2,4
Discuss types of Communication. List some difference between serial and parallel
communication.

Section-C (5X10=50)
Q. No. Question Marks CO BL
Discuss the various types of address mapping used in cache memory.
7 OR 10 4 2,4
Illustrate all the phases of instruction cycle.
Explain the concept of overflow, normalisation and biasing in floating point numbers.
Show (146.125)10 in single precision and double precision format.
OR
8 A bus-organized CPU which has 16 registers with 32 bits in each, an ALU, and a 10 2 2,4
destination
decoder. Solve the following:
a. How many multiplexers are there in the A bus, and what is the size of each
• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student learning
Page 1 of 2
 multiplexer?
b. How many selection inputs are needed for MUX A and MUX B?
c. How many inputs and outputs are there in the decoder?
d. How many inputs and outputs are there in the ALU for data, including input and output
carries?
e. Formulate a control word for the system assuming that the ALU has 35 operations
What is micro programmed control unit? Give the basic structure of micro programmed 1,2
control unit. Also discuss the microinstruction format and the control unit organization
for a typical micro programmed controller using suitable diagram. 10
9 3
OR
Explain the difference between vectored and non-vectored interrupt. Explain stating
examples of each.
A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer
system needs 2K bytes of RAM, 4K bytes of ROM and 4 interface units, each with 4
registers. A memory mapped configuration is used. The two highest order bits of the
address bus are assigned 00 for RAM, 01 for of the ROM and 10 for interface registers.
Evaluate the following-
(i) How many RAM and ROM chips are needed?
(ii) Memory address map for the system.
10 4 5
10 (iii) The address range in hexadecimal for RAM, ROM and interface.
OR
A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The
cache uses direct mapping with block size of four words. Evaluate the following-
(i). Number of bits in tag, index, block and word fields of the address format.
(ii). Number of bits in each word of cache, and how they are divided into functions?
Include a valid bit.
(iii). No of blocks can the cache accommodate
(i)Discuss the design of a typical input or output interface. 2,4
(ii)What are interrupts? how they are handled?
11 5
OR 10
Discuss different types of auxiliary memories.

• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student learning
Page 2 of 2
 Format for 2nd Year Roll Number:
KIET Group of Institutions
(Department of Computer Science & Engineering/Computer Science)
B.Tech, 3rd Semester
Pre University Examination, (2019-20) Odd Semester
(Computer Organization and Architecture) (KCS-302)
Duration: 3 hrs Max. Marks: 100

Note: - Attempt all the Questions.

Section-A (10X2=20)
Q. No. Question Marks CO BL
a Define various registers in Computer Organization. 2 1 1
b Define Bus system. Describe the architecture of Bus system. 2 1 1
c Examine the conditions for divide overflow. 2 2 3
d Determine floating point representation for binary numbers. 2 2 3
e Illustrate vertical microprogramming. 2 3 3
1.
f Describe RISC and CISC instruction set architectures. 2 3 1
g Calculate 128X8 RAM chips, needed to provide memory capacity of 2048 bytes. 2 3 3
h Describe various mapping techniques used in Cache memory. 2 4 1
i illustrate interrupt. 2 5 3
j Describe auxiliary memory. 2 5 1

Section-B (5X6=30)
Q. No. Question Marks CO BL
Discuss stack organization. Explain the following in details-
(i) Register stack
2 (ii) Memory stack 6 1 2
OR
Explain General Register Organization with the help of suitable diagram.
Explain Carry look ahead adder with its block diagram.
3 OR 6 2 2
Explain the concept of overflow, normalisation and biasing in floating point numbers.
Differentiate between hardwired control and micro-programmed control unit.
4 OR 6 3 2
Differentiate between horizontal and vertical microprogramming.
Describe the following organizations of cache memory: (i). Associative mapping
(ii). Direct Mapping (iii). Set associative mapping
5 6 4 2
OR
Explain Virtual Memory. Discuss, why is it necessary to implement virtual memory?
Describe I/O interface
OR
6 6 5 2
Describe in detail about programmed Input/output with neat diagram.

Section-C (5X10=50)
Q. No. Question Marks CO BL
Illustrate bus arbitration with its types.
7 OR 10 1 3
Illustrate memory transfer with different registers associated with it.
Draw the flow chart of Booth’s Algorithm for multiplication and show the multiplication
process using Booth’s Algorithm for (+15) X (-13). 10
8 2
OR 3
Show (-307.1875)10 in single precision and double precision format.
Show an arithmetic expression X= ( A – B ) * ( ( ( C -D ) / F) / G ) Using a general register
computer with three, two, one & zero address instructions.
9 OR 10 3 3
Illustrate all the phases of instruction cycle.

• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student learning
Page 1 of 2
 A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer
system needs 2K bytes of RAM, 4K bytes of ROM and 4 interface units, each with 4
registers. A memory mapped configuration is used. The two highest order bits of the
address bus are assigned 00 for RAM, 01 for of the ROM and 10 for interface registers.
Evaluate the following-
(i) How many RAM and ROM chips are needed?
(ii) Memory address map for the system.
10 (iii) The address range in hexadecimal for RAM, ROM and interface. 10 5
4
OR
A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The
cache uses direct mapping with block size of four words. Evaluate the following-
(i). Number of bits in tag, index, block and word fields of the address format.
(ii). Number of bits in each word of cache, and how they are divided into functions?
Include a valid bit.
(iii). No of blocks can the cache accommodate.
Outline the block diagram of DMA controller. Illustrate, why are the read and write
control lines in a DMA controller bidirectional?
11 OR 10 5 4
Illustrate asynchronous data transfer. Classify strobe controller and hand shaking
mechanism for asynchronous data transfer.

• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student learning
Page 2 of 2
 KIET Group of Institutions
(Department of Computer Science and Engineering)
B.Tech, 3rd Semester
Pre-University Examination II, (2021-22) ODD Semester
Computer Organization and Architecture (KCS 302)
Duration: 3 hrs Max. Marks: 100
Note: - Attempt all the Questions.
Section-A (10X2=20)
BL/
Q. No. Question Marks CO
KC*
A Explain the term Computer architecture and organization. 2 1 2/C
b Define Burst Stealing. 2 4 1/C
c Define two types of IEEE 754 Formats 2 2 1/F
d Explain restoring method in division algorithm. 2 2 2/C
e Differentiate between linear and non-linear pipeline. 2 3 2/C
1.
f Define control memory ?. 2 3 1/F
g Define the 2D RAM and 2.5D RAM. 2 4 1/F
h Define the term page fault? 2 5 1/C
i Explain registers and its types. 2 1 2/F
j Explain the Cycle Stealing. 2 5 2/C
Section-B (5X6=30)
BL/
Q. No. Question Marks CO
KC*
Explain various methods of Bus arbitration with their advantages and disadvantages.
2 OR 6 1 2/P
Explain Stack Organization. Also discuss register stack and memory stack.
Demonstrate the Block Diagram Carry Look Ahead Adder.
3 OR 6 2 3/C
Demonstrate the working of 4*4 Array Multiplier in detail with the help of an diagram.
Compare the difference between RISC & CISC based Microprocessor.
4 OR 6 3 5/C
Design sequential Arithmetic & Logic unit (ALU) and explain its working
Illustrate the concept of virtual memory. Discuss how paging helps in implementing virtual
memory.
5 6 4 4/P
OR
Illustrate the concept of SRAM and DRAM.
Define the term interrupts? how they are handled?
6 OR 6 5 1/P
Describe the design of a typical input or output interface.
Section-C (5X10=50)
BL/
Q. No. Question Marks CO
KC*
Define different modes of Data Transfer.
7 OR 10 5 1/P
Define different types of auxiliary memories.
A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer
system needs 2K bytes of RAM, 4K bytes of ROM and 4 interface units, each with 4
registers. A memory mapped configuration is used. The two highest order bits of the address 10 4
bus are assigned 00 for RAM, 01 for of the ROM and 10 for interface registers. Evaluate the
8 following- (i) How many RAM and ROM chips are needed? (ii) Memory address map for 5/P
the system. (iii) The address range in hexadecimal for RAM, ROM and interface
OR
Evaluate the page fault for the given string with the help of LRU & FIFO page replacement
algorithm, Size of the frames = 4 and string 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
Describe the arithmetic statement X= (A+B) * (C+D) using general register computer with
three address, two address, one address & zero address instruction format a program to
evaluate the expression. 10 3 1/C
9
OR
Define micro program sequencer? With block diagram, explain the working of micro
program sequencer.
• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student’s
learning.
• *Knowledge Categories (KCs): F-Factual, C-Conceptual, P-Procedural, M-Metacognitive
 Explain IEEE standard for floating point representation. Represent the number
(-124.1875)10 in single and double precision format. 10 2 2/P
10
OR
Explain the multiplication process of (-19) *(+20) using Booth’s Algorithm
Define the term Addressing Mode? Also discuss its various types
OR 10 1
A bus-organized CPU has 16 registers with 32 bits in each. an ALU, and a destination
decoder.
a) How many selection Inputs are needed for MUX A and MUXB? 1/P
11
b) How many inputs and outputs are there in the ALU for data, including input and output
carries?
c) Calculate a control word for the system if the ALU has 35 operations.
d) How many inputs and outputs are there in the decoder?
e) How many multiplexers are there In the A bus, and what is the size of each multiplexer?

• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student’s
learning.
• *Knowledge Categories (KCs): F-Factual, C-Conceptual, P-Procedural, M-Metacognitive
 KIET Group of Institutions
(Department of Computer Science and Engineering)
CSE/ B.Tech., 3rd Semester
Pre-University Examination, (2021-22) ODD Semester
Computer Organization and Architecture (KCS 302)
Duration: 3 hrs Max. Marks: 100
Note: - Attempt all the Questions.
Section-A (10X2=20)
BL/
Q. No. Question Marks CO
KC*
a Define Computer organization and architecture 2 1 1/F
b Illustrate the working of Tristate buffer 2 1 3/C
c Produce postfix expression of given infix expression: A*(B+C-D) +E/F 2 2 3/P
d Compare register stack and memory stack. 2 2 2/F
e State two types of IEEE 754 Formats 2 3 1/F
1.
f Match which computer organization is associated with which address format instruction. 2 3 1/C
g Differentiate how 2.5D is different from 2D memory organization. 2 4 2/C
h Tell how many 128X8 RAM chips, needed to provide memory capacity of 2048 bytes. 2 4 1/P
i Name few types of interrupts 2 5 1/F
j Explain the difference between multiplexor and selector 2 5 2/C
Section-B (5X6=30)
BL/
Q. No. Question Marks CO
KC*
Demonstrate 2-bit Bus system using Multiplexer
2 OR 5 1 2/C
Demonstrate 2-bit Bus system using Tri-state Buffer
Show the working mechanism of 4-Bit Binary Parallel Adder Subtractor
3 OR 5 2 3/F
Demonstrate Carry Look Ahead Adder working mechanism
Analyse One Address Instructions and Zero Address Instructions with one example of
each.
4 5 3 4/P
OR
Explain the working of One Stage of Arithmetic and Logic Unit.
Explain the following organizations of cache memory: (i). Associative mapping
(ii). Direct Mapping (iii). Set associative mapping
5 5 4 2/F
OR
Summarize the Virtual memory implementation of Segmentation and Paging
Demonstrate the design of a typical input or output interface.
6 OR 5 5 2/F
Explain What are interrupts? how they are handled?
Section-C (5X10=50)
BL/
Q. No. Question Marks CO
KC*
Illustrate all Bus Arbitration methods. 10 1 3/F
7 OR
Illustrate General register Organization.
Evaluate Multiplication of two numbers 17 and -7 by using the Booth's multiplication 10 2 5/P
algorithm.
8
OR
Evaluate division of 15 by 6 using restoring division Algorithm method
Reframe (-923.125)10 into single precision representation and double precision. 10 3 5/P
OR
9
Evaluate the addition of any two floating point numbers. Define Overflow and Underflow
Conditions
A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer 10 4 5/P
system needs 2K bytes of RAM, 4K bytes of ROM and 4 interface units, each with 4
10/
registers. A memory mapped configuration is used. The two highest order bits of the
address bus is assigned 00 for RAM, 01 for of the ROM and 10 for interface registers.
• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student’s
learning.
• *Knowledge Categories (KCs): F-Factual, C-Conceptual, P-Procedural, M-Metacognitive
 Evaluate the following-
(i) How many RAM and ROM chips are needed?
(ii) Memory address map for the system.
(iii) The address range in hexadecimal for RAM, ROM and interface.
OR
A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The
cache uses direct mapping with block size of four words. Evaluate the following-
(i). Number of bits in tag, index, block and word fields of the address format.
(ii). Number of bits in each word of cache, and how they are divided into functions?
Include a valid bit.
(iii). No of blocks can the cache accommodate
Show the block diagram of DMA controller. Illustrate, why are the read and write control 10 5 3/F
lines in a DMA controller bidirectional?
11
OR
Illustrate all three types of Modes of Transfer.

• CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the
course successfully.
• Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student’s
learning.
• *Knowledge Categories (KCs): F-Factual, C-Conceptual, P-Procedural, M-Metacognitive