Small-Signal (AC) Analysis

BJT Transistor Modelling : Approximate Hybrid Equivalent Model

Common-Base Configuration (pnp)

ie ic
e c
1
hib h fb ie
hob

ib
b
CB Hybrid Equivalent Circuit

hi : Small-Signal Input Resistance

hf : Small-Signal Current Gain
ho : Small-Signal Output Admittance
212
veb  hib ie
ie ic
ic  h fb ie  hob vcb e c
1
h fb   ac   dc hib h fb ie
hob
T
hib  ib
I EQ b

kT
T   26 mV at room temperature
q

I CQ
hob 
VA

213
CE Hybrid Equivalent Model (npn)
ib ic
b c
1
hie h fe ib
hoe

vbe  hie ib ie
e
ic  h fe ib  hoe vce
hoe is dependent Early Voltage, VA
h fe   ac   dc
IC
T
hie 
I BQ

I CQ VA VCE
hoe 
VA 214
CE Hybrid Equivalent Model (npn)

vbe  r ib
c
h fe   ac   dc
b

e T
r  hie 
I BQ
b c
+ 1 VA
r g m vbe ro ro  
vbe hoe I CQ
 e I BQ
g m  h fe
T

215
Example: CB Amplifier

Find Ai, Av, Avs, Zin and ZO.

iin RS C1 C2
iO
+ +
RE RC
vS Vin + RL vO
VCC
 VEE +

Zin ZO

216
Small Signal Analysis
 C1 and C2 are short circuit.
 Setting all DC voltage sources to zero and replacing them by a short
circuit equivalent.

RS iin e ie ic iO
+ c +
hib 1
vS vin RE h fb ie RC RL vO
hob
 b 
Zin ZO

217
 RS iin e ie ic iO
+ c +
hib 1
vS vin RE h fb ie RC RL vO
hob
 b 
Zin ZO

vO
Voltage Gain, AV 
v in
 1  
vO  RL iO   RC RL  h fb ie  RX ie
 hob  
 vO RX
RX    AV
 vin hib
vin  hib ie 

218
 RS iin e ie ic iO
+ c +
hib 1
vS vin RE h fb ie RC RL vO
hob
 b 
Zin ZO
iO
Current Gain, Ai 
iin

iO  h fb ie
RC  1 hob 
RC 1 hob   RL
ie   RE  hib  RE   iin
iO h fb RE RC 1 hob 
  Ai
iin hib  RE RC 1 hob   RL
219
 RS iin e ie ic iO
+ c +
hib 1
vS vin RE h fb ie RC RL vO
hob
 b 
Zin ZO

v in
Input Impedance, Z in 
iin

vin vin
Z in   RE
iin ie
 RE hib

220
 RS iin e ie ic iO
+ c +
hib 1
vS vin RE h fb ie RC RL vO
hob
 b 
Zin ZO
vO
Overall Voltage Gain, AVS 
vs
vS  RS iin  vin  RS iin  Z in iin   RS  Z in  iin

vS   RS  Z in  iin vS RS  Z in
 
vO  RL iO vO RL Ai

RL Ai
AVS 
RS  Z in
221
Output Impedance, ZO  vT iT
Setting vS = 0, and test voltage, vT, is connected to the output.
RS e i e
iT
c
+
hib 1
RE h fb ie RC vT
hob
b
ZO
vT
iT   h fb ie and ie  0
1
RC
hob
vT
iT 
1
RC
hob
vT 1
 Z O  RC
iT hob 222
Example: CE Amplifier
VCC

RB RC
C2 vo
RS C1
+ RL
vS Vin

 Zin ZO

Small Signal Analysis

 C1 and C2 are short circuit.
 Setting all DC voltage sources to zero and replacing them by a short
circuit equivalent.

223
 iin RS b ib ic iO
+ c +
hie 1
vS vin RB h fe ib RC RL vO
hoe
 e 
Zin ZO

vO
Voltage Gain, AV 
v in

 1  
vO    RC RL  h fe ib 
 hoe   vO  h fe  1 
   RC RL   AV
 vin hie  hoe 
vin  hie ib 

224
 iin RS b ib ic iO
+ c +
hie 1
vS vin RB h fe ib RC RL vO
hoe
 e 
Zin ZO

iO
Current Gain, Ai 
iin

iO   h fe ib
RC  1 hoe 
RC 1 hoe   RL
ib   RB  hie  RB   iin
iO h fe RE RC 1 hoe 
  Ai
iin hie  RE RC 1 hoe   RL
225
 iin RS b ib ic iO
+ c +
hie 1
vS vin RB h fe ib RC RL vO
hoe
 e 
Zin ZO

v in
Input Impedance, Z in 
iin

vin vin
Z in   RB
iin ib
 RB hie

226
 iin RS b ib ic iO
+ c +
hie 1
vS vin RB h fe ib RC RL vO
hoe
 e 
Zin ZO

vO
Overall Voltage Gain, AVS 
vs
vS  RS iin  vin  RS iin  Z in iin   RS  Z in  iin

vS   RS  Z in  iin vS RS  Z in
 
vO  RL iO vO RL Ai

RL Ai
AVS 
RS  Z in
227
Output Impedance, ZO  vT iT
Setting vS = 0, and test voltage, vT, is connected to the output.
RS b ib c iT

1 +
hie
RB h fe ib RC vT
hoe
e

vT ZO
iT   h fe ib and ib  0
1
RC
hoe
vT
iT 
1
RC
hoe
vT 1
 Z O  RC
iT hoe 228
 5V

Example: Find the small signal voltage gain of the circuit. 2k

VA=100V, VBE(on)=0.7V, β=100

C1 C2 vO

DC Analysis (Capacitors are open circuit.)

vin 100k
5V  100kI B  VBE  on   5kI E  0 5k C3

5V  0.7V 5V
I BQ   7.1 A
100k  101  5k 5V

I CQ  100  7.1 A  0.71mA 2k

h fe    100
T 26mV
hie    3662
I BQ 7.1 A
100k
1 VA 100V 5k
   140k
hoe I CQ 0.71mA 5V 229
Small Signal Analysis (ac analysis)
 C1, C2 and C3 are short circuit.
 Setting all DC voltage sources to zero and replacing them by a short
circuit equivalent.

RC
2k vO
vO
+ + RC
RB RB 2k
vin vin
100k 100k

230
 ib
+ vO
RB hie 1 RC
vin h fe ib
100k hoe 2k

 1 
v0   h fe ib  RC 
 hoe 
vin  hie ib
v0 h fe  1  100
 AV    RC     2k 140k   53.8
vin hie  hoe  3662

The minus sign in the voltage gain expression represents 180 degree
phase shift.
231
 vin

vin  VM sin  t t
iB
IBQ
iB  I BQ  ibm sin  t
t
iC

iC  I CQ  icm sin  t ICQ

t
vCE
vCE  VCEQ  VCEm sin  t
VCEQ

vO  VOm sin  t vO
t

t
232
 AC load line dI 1
 
dV Rac

v ce  VCEQ   Rac iC  I CQ 
When iC  0; v ce  VCEQ  Rac I CQ
VCEQ
IC When v ce  0; iC  I CQ 
Rac
iC ac load line

ib

ICQ
Q
IBQ

dc load
line
VCE
VCEQ vCE VCC
233
Example: a) Find Z in , Z o , AV and Ai .
b) Draw the dc and ac load lines and find Q point.
c) Find the maximum symetrical swing at the output.

  100, VBE (on )  0.7 and V A  

12V

2.2k
400k vo
iin C1 iO
C2
+ 2.2k
vin
C
Zin 0.5k
ZO

234
DC Analysis (Capacitors are open circuit.)
Applying KVL to the input;

12V VCC  RB I B  VBE  RE I E  0

2.2k VCC  RB I B  VBE  RE 1    I B  0

400k
VCC  VBE  on 
I BQ 
RB  1    RE
0.5k 12V  0.7V
=  25  A
400k  101  0.5 k
I CQ  100  25  A  2.5 mA  I EQ
Applying KVL to the output;

VCC  RC I C  VCE  RE I E  0  dc load line 

VCE  VCC   RC  RE  I C  12  2.7  2.5  5.25V
235
AC analysis: Capacitors are short circuit, setting dc voltage source to
zero and replacing it by a short circuit equivalent.

h fe    100
T 26mV
hie    1040
I BQ 25  A
1 VA 
  
hoe I CQ I CQ

2.2k vO
400k vO

2.2k 2.2k 2.2k

+ +
vin
vin 400k

236
 ib iC
vO
+ RB RC RL
vin hie
400k h fe ib 2.2k 2.2k
ZO
Zin
Rac
Input impedance, Z in
Z in  RB hie  400 k 1040  1037 

vO
Voltage Gain, AV 
vin
v0   h fe ib  RC RL 
vin  hie ib
v0  h fe 100
 AV   RC RL    2.2k 2.2k   105
vin hie 1040 237
 iin ib iC
vO
+ iO
RB hie RC RL
vin 400k h fe ib 2.2k 2.2k
ZO
Zin
Rac
iO
Current Gain, Ai 
iin
 h fe ib 
iO  RC 
RC  RL  iO  h fe RC RB
 
iin  iin RC  RL RB  hie
ib  RB
RB  hie 

100  2.2 400k

Ai   50
2.2  2.2 400 k  1040
238
Output Impedance, Z O  vT iT

Setting vin = 0, and test voltage, vT, is connected to the output.

ib iC iT

RB hie RC
v
+
400k h fe ib 2.2k T

ZO

vT
iT   h fe ib and ib  0
RC
vT
 Z O  RC  2.2k
iT
239
 I C ( mA)
dc and ac load line 7.27 ac load line

VCC   RC  RE  IC  VCE  0
4.44

When IC  0  VCE  12V Q

2.5 IBQ
12
When VCE  0  IC   4.4mA
2.7k dc load
line
VCE
5.25 8 12

Rac  RC RL  2.2k 2.2k  1.1k

 vce  VCEQ   Rac  iC  I CQ 

dI 1

dV Rac
When iC  0  vce  VCEQ  Rac I CQ  5.25V  1.1  2.5  8V
VCEQ 5.25V
When vce  0  iC  I CQ   2.5    7.27 mA
Rac 1.1k
240
 Max. Symmetrical swing at the output
I C ( mA)
 2   8  5.25   5.5V
7.27

ac load line
4.44
2.75
max. input peak
  26.19mV
AV
Q
2.5 IBQ

dc load
line
VCE(V)
5.25 8 12

if vin = 26x10-3sinωt,
vO = -2.73sinωt

if vin = 30x10-3sinωt,
vO = -3.15sinωt ??? 241
Unbypassed Emitter Bias 12V
Example: Find Ai, Av, Zin and ZO.
2.2k
400k vo
iin C1 iO
C2
+ 2.2k
vin
0.5k
Zin ZO

DC Analysis (Capacitors are open circuit.)

h fe    100
  100  I BQ  25  A  T 26mV
  hie    1040
VBE  0.7V  I CQ  2.5mA  I BQ 25  A
 
VA   VCEQ  5.25V  1 VA 
   
hoe I CQ I CQ
242
AC analysis: Capacitors are short circuit setting dc voltage source to
zero and replacing it by a short circuit equivalent.

ib iC iO
vO
+ RB RC RL
vin hie
400k h fe ib 2.2k 2.2k

RE
0.5k ZO
Zin Z in'

vin hie ib  RE ie hie ib  RE 1  h fe  ib

Z in 
'
   hie  1  h fe  RE
ib ib ib
 51.54 k

Z in  Z in' RB  45.66k 
243
 ib iC
vO
+ RB RC RL
vin hie
400k h fe ib 2.2k 2.2k

RE
0.5k

v0
Voltage gain, AV 
vin
vO   h fe ib  RC RL 

vin  hie ib  RE 1  h fe  ib

vO  h fe  RC RL  100  1.1k
   2.14
vin hie  RE 1  h fe  51.54 k
244
 iin ib iC iO
vO
+ RB RC RL
vin hie
400k h fe ib 2.2k 2.2k

RE
0.5k

i0
Current gain, Ai 
iin

 h fe ib 
i0  RC 
RC  RL  i0  h fe RC RB 100  2.2 k  400 k
    44.3
iin  iin RC  RL RB  Z in 4.4k   400 k  51.54 k 
'

ib  RB
RB  Z in
' 

245
Output Impedance, Z O  vT iT

Setting vin = 0, and test voltage, vT, is connected to the output.

ib iT

RB RC
v
hie +
400k h fe ib 2.2k T

RE
0.5k ZO

vT
iT   h fe ib and ib  0
RC
vT
 Z O  RC  2.2k
iT
246
 12V

2.2k
400k vO
iin C1 iO
C2
+ ZO 2.2k
vin
Zin 0.5k C

Bypassed Emitter Bias Unbypassed Emitter Bias

Av -105 -2.14

Ai -50 -44.3

Zin 1.037kΩ 45.66kΩ

Zo 2.2kΩ 2.2kΩ
247
HW: a) Find Z in , Z o , AV and Ai .
b) Draw the dc and ac load lines and find Q point.
c) Find the maximum symetrical swing at the output.

  100, VBE  0.7 and VA  

12V

2.2k
400k vO
iin C1 iO
C2
+ 2.2k
vin ZO
0.1k
Zin

0.4k C3

248
Collector Feedback
Example: Find Av, Zin and ZO.

+VCC RC  RL  2k 
RB  100 k 
RC
RB C2 vO
  100
C1
RL
VA  
+ hie  1k 
vin ZO hoe  0
Zin

249
Small Signal Analysis (ac analysis)
 C1 and C2 are short circuit.
 Setting DC voltage source to zero and replacing it by a short circuit
equivalent.

RB I

iin ib iC iO
vO
+
vin
hie h fe ib RC RL

Zin ZO

250
Voltage Gain, Av RB I
Applying KCL to output iin ib iC iO
vO
vO
 h fe ib  I  0 +
hie h fe ib RC RL
RC RL vin

vin vO  vin
ib  , I Zin ZO
hie RB
vO vin vO  vin
 h fe   0,
RC RL hie RB
vO  1 h fe   hie  h fe RB 
 vin     vin  
RC RL RB  RB hie   hie RB 
vO  hie  h fe RB 
  RC RL RB     AV  AV  99
vin  hie RB  251
 RB I
Input impedance
iin ib
vO
vin
Z in  +
hie
iin vin h fe ib RC //RL

Zin
Applying KCL to input

vO  vin vin
iin  I  ib  0  iin   0
RB hie
vO vin AV  vin vin
iin   = 0  iin   0
RB RB hie RB RB hie
iin 1  AV 1 1
   
vin Z in RB RB hie 500
252
 Output Impedance, Z O  vT iT

Setting vin =0, and test voltage, vT, is connected to the output.
RB I

ib iT


hie h fe ib RC + vT

ZO

vT vT vT
iT   h fe ib  
RC RB RB RC
vT
 Z O  RB RC  1.96 k
iT
253
Emitter Follower (voltage follower)
Example: Find Ai, Av, Zin and ZO.

VCC
RB  100 k 
RB RE  RL  2 k 
C1
+ C2 vO hie  1k 
vin
hoe  0
RE RL h fe  100
Zin
ZO

254
 Small Signal Analysis

iin ib

+
vin RB hie
h fe ib

vO
iO
Zin Z '
RE
in RL

ZO

 hie  1  h fe   RE
vin
Z 
'
in RL   1k   101  1k   102k 
ib
Z in  RB Z in'  100 k 102k  50.5 k
255
 iin ib
Voltage Gain, Av
+
vO vin RB hie
AV  h fe ib
vin
vO
iO
Zin Z '
RE
in RL

vO   RE RL  ie   RE RL  1  h fe  ib ZO

vin  hie ib   RE RL  ie   hie  1  h fe   RE RL   ib

vO  RE RL  1  hfe  1k  101
AV     0.99  1
vin hie  1  h fe   RE RL  1k  101  1k

256
 iin ib

+
io vin RB hie
Current Gain, Ai  h fe ib
iin
vO
iO
Zin Z '
RE
in RL

iO 
ie
 RE 
 1  h fe  ib
 RE ZO
RE  RL RE  RL
iin
ib   RB
RB  Z in
'

iO RE RB  1  h fe  2k  100k  101
Ai     25

iin  RE  RL  RB  Z in '
 4k  100k  102k 

257
  vT 
Output Impedance, Z O  RE  
 iT 
ib

RB hie
h fe ib
iT

+ v
T

vT  hie ib
iT  iE  1  h fe  ib
vT hie 1k
 
iT 1  h fe 101
v   1k 
Z O  RE  T   2k    9.85
 iT   101 
258
Example: Find Z in , Z o , AV and Ai .
  120, VBE (on)  0.7 and VA  

12

iin C1
C2
Vin Vo
390k iO
5.6k
Zin
8 ZO

259
DC Analysis (Capacitors are open circuit.)

Applying KVL to the input;

12

8  390k  I B  VBE  5.6k  I E  0

390k 8  0.7
5.6k
IB 
390k  121  5.6 k

8 I BQ  6.84  A

T 26mV
hie    3.8k 
I BQ 6.84  A

260
Small Signal Analysis

iin ib

+
Vin 390k hie
h fe ib

iO VO
Zin Z in' 5.6k
ZO

 hie  1  h fe  RL  3.8k  121  5.6k  681.4k 

Vin
Z 
'
in
ib
Z in  RB Z in'  390k 681.4k  248k 

261
Voltage Gain, Av
iin ib

+
Vin 390k hie
h fe ib

iO VO
5.6k

VO  5.6k  iO  5.6k  1  h fe  ib

Vin   hie  5.6k  1  h fe   ib

VO 5.6k  121
  0.994  1
Vin 3.8k  121  5.6 k
262
 iin ib

+
io Vin 390k hie
Current Gain, Ai  h fe ib
iin
iO VO
Zin Z in' 5.6k

iO  ie  1  h fe  ib

iin
ib   RB
RB  Z in
'

iO RB 1  h fe  390k  121
Ai     44
iin RB  Z in
'
390k  681.4k

263
  VT 
Output Impedance, ZO  RE / /  
 iT 
ib

RB hie
h fe ib
iT

+ V T
VT  hie ib


iT  i E  1  h fe ib 
VT hie 3.8k
   31.4
IT 1  h fe 121

 VT 
Z O  RE    5.6k  31.4  31.2
 IT  264
Harmonic Distortion

If an input sinusoidal signal becomes too large, the output signal may
no longer be a pure sinusoidal signal because of nonlinear effects. A
nonsinusoidal output signal may be expanded into a Fourier series and
written in the form

VO (t )  VO  V1 sin t  1   V2 sin 2t  2   

    
DC desiredlinearoutput 2 nd harmonicdistortion

The signal at the frequency ω is the desired linear output signal for a
sinusoidal input signal at the same frequency.

IS  v BE T  I S VBEQ  vbe  T I S VBEQ T T T

iB  e  e  e e vbe  I BQ e vbe
  
I BQ
265
If the vbe signal is assumed to be sinusoidal, but if its magnitude becomes
too large, then the output signal will no longer be a pure sinusoidal
voltage but will become distorted and contain harmonics.
T
Expanding the exponential function e vbe into a Taylor series,

2 3
x x
ex  1 x   
2 6
where x  vbe T . If we assume the input signal is a sinusoidal funtion,

then we can write

vbe Vm
x  sin  t
T T

266
The exponential function can then be written as
2 3
Vm 1  Vm  1  Vm 
e  1
x
sin  t    sin 2
 t    sin 3
t  (1)
T 2  T  6  T 
From trigonometric identities, we can write

sin 2  t 
1
2
 
1  sin 2 t  90 0  (2)

 3 sin  t  sin  3 t  
1
sin 3  t  (3)
4
Substituting Equations (2) and (3) into Equation into (1), we obtain
 1  V 2  V  1  V 2 
e vbe T
 1   m    m 1   m   sin  t
 4  T   T  8  T  
2 3
1  Vm  1  Vm 
  
 sin 2 t  90  
4  T 

 sin  3 t  
24  T  267
We see that as (Vm/ΦT) increases, the second and third harmonic terms
become non-zero. In addition, dc and first harmonic coefficients also
become nonlinear. A figure of merit is called the percent total harmonic
distortion (THD) and is defined as


 n
V 2

THD 00  2
 100 0 0
V1
Considering only the second and third harmonic terms, the THD is
plotted in the figure.
THD The distortion can be reduced when feedback
15
circuits is used.
10
5 A THD rating < 1% is considered to be in high-
0 5 10 15 Vm(mV)
fidelity and inaudible to the human ear.
268