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ERACAN: Defending Against an Emerging CAN Threat Model

Conference Paper · October 2024

DOI: 10.1145/3658644.3690267

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 ERACAN: Defending Against an Emerging CAN Threat Model
Zhaozhou Tang Khaled Serag Saman Zonouz
Georgia Institute of Technology Qatar Computing Research Institute Georgia Institute of Technology
Atlanta, USA Doha, Qatar Atlanta, USA
[email protected] [email protected] [email protected]

Z. Berkay Celik Dongyan Xu Raheem Beyah

Purdue University Purdue University Georgia Institute of Technology
West Lafayette, USA West Lafayette, USA Atlanta, USA
[email protected] [email protected] [email protected]

Abstract 1 Introduction
The Controller Area Network (CAN) is a pivotal communication Since its introduction in the 1980s, the Controller Area Network
protocol extensively utilized in vehicles, aircraft, factories, and di- (CAN) has solidified its position as the primary in-vehicle net-
verse cyber-physical systems (CPSs). The extensive CAN security work and extended its influence to diverse cyber-physical systems
literature resulting from decades of wide usage may create an im- (CPSs), allowing hundreds of electronic control units (ECUs), which
pression of thorough scrutiny. However, a closer look reveals its govern various sensors, actuators, and CPS control functions, to
reliance on a specific threat model with a limited range of abilities. communicate. Decades of widespread adoption have spurred sub-
Notably, recent works show that this model is outdated and that stantial security research. Initially, accessing the bus was believed
a more potent and versatile model could soon become the norm, viable only through physical access, typically granted to autho-
prompting the need for a new defense paradigm. Unfortunately, the rized users. However, increased ECU connectivity challenged this
security impact of this emerging model on CAN systems has not assumption, allowing malicious attackers to exploit wireless chan-
received sufficient attention, and the defense systems addressing it nels such as WiFi, cellular, and Bluetooth to remotely compromise
are almost nonexistent. In this paper, we introduce ERACAN, the ECUs [8, 40, 45, 46, 68]. This shift ushered in a once-deemed unre-
first comprehensive defense system against this new threat model. alistic threat model: remote attackers.
We first begin with a threat analysis to ensure that ERACAN com- From an OSI standpoint, the standard outlines the communica-
prehensively understands this model’s capabilities, evasion tactics, tion rules of the physical and data link layers for a broadcast-based
and propensity to enable new attacks or enhance existing ones. bus and leaves the upper layers open to allow flexibility for various
ERACAN offers versatile protection against this spectrum of threats, use cases. Typical ECUs connect to the bus through a CAN protocol
providing attack detection, classification, and optional prevention controller and a transceiver, which enforce the specification rules
abilities. We implement and evaluate ERACAN on a testbed and a for the data link and physical layers, respectively. The existing lit-
real vehicle’s CAN bus to demonstrate its low latency, real-time erature assumed that remote attackers could control the ECU but
operation, and protective capabilities. ERACAN achieves detection not the controller or transceiver, effectively leaving the data link
rates of 100% and 99.7%+ for all attacks launched by the conven- and physical layers intact. This meant that they could only read or
tional and the enhanced threat models, respectively. write entire messages assembled by an unbroken CAN controller.
With these two capabilities, many works have shown that attackers
CCS Concepts could launch a plethora of attacks, including fake message injec-
• Security and privacy → Network security. tion, masquerading, flooding, error injection, and suspending other
ECUs [2, 4, 8, 9, 33, 39, 40, 45, 46, 58, 59, 68, 69].
Keywords As a response, researchers proposed several defense approaches.
Some explored protecting against certain attack types (e.g., mas-
Automotive Security; Controller Area Network; Intrusion Detection
querade) using techniques such as MACs or secret numbers to
ACM Reference Format: provide source authentication. However, due to limitations in-
Zhaozhou Tang, Khaled Serag, Saman Zonouz, Z. Berkay Celik, Dongyan cluding message length, busload, key management, and the lim-
Xu, and Raheem Beyah. 2024. ERACAN: Defending Against an Emerging ited processing powers of most ECUs, intrusion detection systems
CAN Threat Model. In Proceedings of the 2024 ACM SIGSAC Conference on
(IDSs) [10, 13, 19, 30–32, 52, 56, 57, 61, 72] gained more traction.
Computer and Communications Security (CCS ’24), October 14–18, 2024, Salt
Lake City, UT, USA. ACM, New York, NY, USA, 15 pages. https://doi.org/10.
These approaches, which contain a super-node handling the bulk
1145/3658644.3690267 of the security work, are more suitable for CAN systems due to
their performance-friendliness. The node monitors traffic and de-
This work is licensed under a Creative Commons Attribution- tects anomalies leveraging features, including message frequency,
NonCommercial International 4.0 License. payload, timing, and physical signal characteristics.
Despite the ostensible maturity of CAN security research, recent
CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA developments suggest otherwise. While the literature assumes that
© 2024 Copyright held by the owner/author(s).
ACM ISBN 979-8-4007-0636-3/24/10
https://doi.org/10.1145/3658644.3690267
CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA Zhaozhou Tang, et al.

remote attackers cannot control the link layer, recent works indi- S ID R Control Data CRC ACK EOF
cate that this assumption may be obsolete. Techniques including O T
F 11b R 6b 0-64b 16b 2b 7b
manipulating peripheral clock gating or remapping transceivers’
IO ports allow attackers substantial link layer control on many
ECUs [6, 14, 34, 63]. Unlike the Conventional Remote Attacker Figure 1: Format of a standard CAN data frame.
Model (CRAM), where only two basic abilities–sending and receiv-
ing entire messages through an intact controller–enabled various
attacks, the Enhanced Remote Attacker Model (ERAM) possesses ex- attaching a single monitor node. To help the research community
pansive capabilities, including injecting pulses, incomplete frames, build on ERACAN, we open source our FPGA design.1
and edge control. These boosted abilities introduce more advanced For inclusivity, we evaluate the performance and security of
attacks whose security implications are not fully investigated. Re- ERACAN on a testbed and a real vehicle’s CAN bus. ERACAN achieves
search demonstrates that the ERAM abilities may improve existing 100% detection for CRAM attacks, 99.7%-100% detection for ERAM
attacks [34, 43, 48], enable new attacks [64, 73], and circumvent attacks, and an attack classification accuracy of 98.8%-100%. Overall,
current defense systems. Surprisingly, no defense systems address- we make the following contributions:
ing this threat model are proposed, and a comprehensive analysis • We introduce ERACAN, the first defense system against the ERAM
of its security impact remains absent. model, offering real-time detection, classification, and optional
In response to this critical gap, we introduce ERACAN, the first prevention abilities for CRAM as well as ERAM attacks.
comprehensive defense system against ERAM attackers. ERACAN • We systematically threat-analyze ERAM to understand its features,
provides detection for all ERAM and CRAM attacks, with optional defense evasion tactics, and the attacks it enables or improves,
prevention where feasible. As ERAM spans various attacks, ERACAN as a basis for ERACAN and future ERAM defenses to build on.
also provides attack classification, making clear the specific type of • We propose a new autonomous surveillance mechanism for in-
attack it is reacting against. Defending against ERAM poses major tricate link layer events by delegating it to a configurable FPGA
challenges. C1: First, a thorough analysis needs to identify the full controller (ERACAN controller) to ensure parallel execution and
range of ERAM abilities, attacks, and security implications, which real-time performance. Additionally, we introduce a smart check-
is absent from prior works. C2: Second, confronting an attacker ing approach for physical layer features. Finally, we provide open
able to manipulate low-level events requires monitoring features access to our FPGA controller design to support further research.
spanning both the physical and link layers. A complete feature set • We offer a performance analysis as well as a security analysis of
covering all ERAM attacks is difficult to find due to the extensive ERACAN against various ERAM attacks and evasion tactics.
ERAM capabilities. Existing defenses focus on single feature cate- • We demonstrate ERACAN’s feasibility, real-time abilities, perfor-
gories, hindering the detection of most ERAM attacks. For example, mance, and protective capabilities by evaluating it on a testbed
defenses that identify message senders and check if they are legit- and a real vehicle’s CAN bus and achieve excellent results.
imate using voltage features cannot detect messages transmitted
by a legitimate sender using ERAM techniques to achieve malicious 2 Background
goals [64, 73]. C3: Finally, detection must ensure reliability and 2.1 CAN Basics
abide by deadlines for effective incident response (e.g., destroying
malicious messages before they are received). Crafting a monitoring Bit Encoding. CAN uses differential voltage between CANH and
strategy satisfying both goals presents another significant obstacle. CANL to encode bits. A positive (dominant) voltage denotes 0 and
Current sender identification approaches cannot detect attacks in- zero (recessive) voltage denotes 1. When two nodes send a 1 and 0
jecting short pulses. Similarly, using the GPIO to surveil the link concurrently, all nodes read a 0. If five identical bits are transmitted
layer is unreliable and computationally expensive. consecutively, a stuff bit of the opposite value is inserted.
We first address C1 by thoroughly analyzing the ERAM model Frame Format. Fig. 1 shows the various message fields. The ID
to understand its capabilities and security impacts through litera- determines the priority of a message, with lower IDs indicating a
ture review and extrapolation. We then identify the needed feature higher priority. When two nodes start transmission at the same
set including bit timing, voltage, and link layer events to cover all time, they perform arbitration. Each node sends one bit at a time.
ERAM attacks and address C2. Finally, to monitor these features and The first node to transmit a 1 yields. A message terminates with the
meet the requirements of C3, ERACAN uses a dedicated monitor End of Frame (EOF) field (seven 1s). The next consecutive message
node adopting a dual-faceted delegation, and smart checking strat- is separated by at least three additional Inter Frame Space bits (IFS).
egy. It deploys a customized FPGA controller (ERACAN controller) Error Handling. The CAN standard defines five kinds of errors:
for autonomous link layer surveillance to ensure reliability, cus- bit, stuff, form, CRC, and acknowledgement errors. Upon detecting
tomizability, and parallel execution. For the physical layer, ERACAN an error, nodes signal with an error frame. A CRC error is signaled
deviates from traditional sender identification. It mainly uses fea- after the ACK field. Other errors are signaled at the next bit after
tures to model valid message properties with simple equations and where they are detected.
performs checks selectively based on attack scenarios. This reduces Error States. Every node keeps a Transmit Error Counter (TEC)
complexity and simplifies processing to meet deadlines. ERACAN and a Receive Error Counter (REC) to keep track of errors encoun-
is cost-efficient and requires minimal hardware changes, merely tered during transmission or reception, respectively. If TEC or REC

1 https://tinyurl.com/5n77avxu
ERACAN: Defending Against an Emerging CAN Threat Model CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA

exceeds 127, nodes enter the error-passive state, where stricter er- CPU
ror signaling and transmission rules are enforced. If TEC or REC
exceeds 255, they enter the bus-off state and stop communicating. Data Clock
Sampling. CAN controllers divide a single bit into four segments of GPIO … CAN Controller … SPI
configurable durations: synchronization, propagation delay segment,
and the phase buffer 1 and 2 segments. Controllers interpret the bit Select
value at the sample point at the end of the phase buffer 1 segment. ECU Peripherals
Synchronization. A node expects 1→0 edges from other nodes TX RX
within the the synchronization segment. If it observes the edge CAN Transceiver
outside the synchronization segment, it resynchronizes either by
lengthening phase buffer 1 or shortening phase buffer 2 segment. CAN Bus

2.2 Conventional Remote Attacker Model Figure 2: Typical Architecture of an ECU.

2.2.1 Basic Abilities. CRAM attackers possess three basic abilities:
Valid Message Reception. They can read data or remote frames
or sender authenticity only using secret tokens embedded in mes-
after they are fully received and validated by the CAN controller.
sages [25, 27, 70]. Researchers have made progress in making these
Valid Message Transmission. They can only transmit valid data
approaches more lightweight, but these improvements are still not
or remote frames using the CAN controller and need to abide by
enough to enable wide adoption.
all protocol rules, such as arbitration.
Secret Delay Approaches. These approaches embed authentica-
Simultaneous Transmission. This is a crucial technique to inject
tion information in secret delays between messages instead of their
collisions. The attacker transmits a message with the same ID as the
payloads [22, 23, 57, 71]. Among them, ZBCAN additionally detects
victim at the same time but with a different payload, so they both
and prevents error-handling attacks. However, it does not protect
win arbitration and gain bus access. To synchronize the messages,
against ERAM attackers (Sec. 4.3). Furthermore, approaches using
the attacker needs to predict when the victim’s message arrives,
secret delays require changing message schedules and could lead
inject one or more preceded messages with a higher-priority ID
to bus load increases and priority inversions.
slightly earlier, and then transmit a message with the target ID.
Physical Signal Approaches. These approaches identify mes-
2.2.2 Possible Attacks. Two primary attack categories are possible: sage senders with ECUs’ physical signal features, such as volt-
Masquerading Attacks. Since CAN does not provide authentica- age [10, 12, 13, 19, 31, 32], bit timing [47, 56, 74], and time dif-
tion, a CRAM attacker can masquerade as other ECUs by transmit- ference of arrival [44, 52, 55]. They offer good security against
ting messages under their IDs to forge or replay messages and alter masquerading attacks but do not detect other attacks, except for
system functions the victim is in charge of. VoltageIDS [13] which detects some error-handling attacks. More-
Error-Handling Attacks. With simultaneous transmission, attack- over, researchers have demonstrated poisoning attacks against some
ers can inject errors in a victim’s message to exploit CAN error of these defenses [4]. Finally, they only consider CRAM attacks and
handling rules. They can destroy messages, push victims to the error- are vulnerable under ERAM in several ways (Sec. 4.3).
passive state to map the network [58], or push them to the bus-off Hardware Approaches. Some defenses use gateways or relays
state to achieve targeted DoS [9]. They can also inject collisions to to isolate attackers [24, 29]. Although very effective against some
corrupt messages’ physical signals, poison the retraining process of attacks, they require significant hardware modifications and are
physical signal based defenses, and render them ineffective [4]. too expensive to be adopted for all nodes on the bus.

3 Related Work 4 The ERAM Threat Model

Timing Based Approaches. These approaches use message tim- Fig. 2 shows the architecture of a typical ECU with several periph-
ing features such as clock skews and message intervals to detect erals to facilitate various functions. During normal operation, it
anomalies [11, 53, 61, 72]. Despite being lightweight, some of them connects to the bus through a CAN controller and a transceiver. Pre-
may not extend their protection to non-periodic messages. Evasion viously, it was assumed that attackers could not change the path to
tactics for some approaches already exist under CRAM [54] and new the bus or influence the controller operation in any way. However,
ERAM tactics further undermine their security (Sec. 4.3). recent work [34] showed that, by manipulating peripheral clock
Payload Inspection Approaches. These approaches inspect mes- gating, the attacker could partially control the controller. Another
sage payloads, extract statistical features, and use machine learning recent work [14] showed that, by re-mapping the IO ports of the
to check their plausibility [1, 38, 67]. Although they are good at transceiver, they could completely disconnect the controller and
detecting injection attacks, some may only detect anomalies consist- instead connect it to other peripherals, such as the GPIO, SPI, UART,
ing of message flows and could allow low-level attacks to pass unno- or others depending on the ECU’s architecture.
ticed. Under CRAM, researchers have demonstrated evasion attacks In this paper, we assume a strong Enhanced Remote Attacker
that reduce the performance of some of these systems. [7]. More- Model (ERAM). We assume the attacker can connect the transceiver
over, ERAM presents new evasion tactics against them (Sec. 4.3). to any other peripheral of the ECU and the ECU has all the com-
Cryptographic Approaches. Some researchers proposed provid- monly used peripherals. This means the attacker has full control
ing sender and content authenticity using MACs [21, 26, 49, 50, 66], over the data link layer and the layers above it, but still abides by
CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA Zhaozhou Tang, et al.

the physical layer’s rules as it uses the transceiver. In this section, Victim ID True Data Passive Error Frame
we first identify ERAM attackers’ capabilities and the features they
unlock. Then, by thoroughly reviewing and extrapolating existing Attacker Fake Data CRC
literature on link layer attacks [14, 43, 62], we analyze their secu- CAN Bus ID True Data Passive Fake
ErrorData
Frame CRC
rity impacts on aspects such as enabling new attacks, improving
True Data
existing ones, and circumventing existing defenses.
Figure 3: Frame hijacking attack.

4.1 Main Capabilities and Features

In addition to all the capabilities of the conventional CRAM model, 4.2 ERAM Attacks
ERAM possesses more sophisticated ones, each unlocking various 4.2.1 New Attacks. Besides all CRAM attacks (Sec. 2.2.2), ERAM
features as discussed below. attackers can launch many completely new attacks.
Ubiquitous Link Layer Visibility. In CRAM, only valid frames Frame Hijacking. As demonstrated by [17, 62], ERAM attackers
received, assembled, and checked by the controller are visible to could push a victim to the error-passive state and hijack frames
the attacker. However, an ERAM attacker can read the bus level mid-transmission. As shown in Fig. 3, the attacker flips a recessive
through the transceiver at any point in time. This unlocks several bit into a dominant one and then continues transmission including
previously unattainable features, such as: a valid CRC. The victim detects a bit error and sends a passive error
Real-time bit inspection: ERAM attackers could read all message flag consisting of six 1s. However, it is overwritten by the attacker’s
bits in real-time, without waiting for the controller to assemble payload and not visible to other nodes. Other nodes receive the
them first. This includes the ID [14], payload, or the various pro- attacker’s forged data and a valid CRC and treat it as a valid message
tocol fields, such as the CRC. This ability has several uses, such as from the victim. This could be very useful if the beginning portion
attacking messages with specific IDs or content. of the message is used for authentication or anomaly detection.
Timing bus events: The attacker can accurately time various bus Double Receive. As shown in [64], an ERAM attacker could flip
events, such as the start of a frame, the transmission of a particular the last bit of EOF from 1 to 0. The receiver treats the message as
ID [14] or field value, and many others. This is crucial for accurate valid as it contains no errors up to the second-to-last bit of EOF [20].
attack timing, such as injecting signals at a specific message field. However, the sender detects a bit error and retransmits the message,
Atypical event visibility: ERAM visibility spans all events, including causing the receiver to get the same message twice. This could cause
valid but rare ones, such as error or overload frames, and invalid problems in several scenarios. For example, the receiver may act
ones, such as pulses, incomplete, and invalid data frames. This on the same message twice when messages do not use sequence
ability has various uses, such as helping the attacker track the numbers, or nodes may lose synchronization when they need to
errors a specific ECU encounters. agree on message counters.
Omnipotent Link Layer Write-Ability. CRAM attackers can only Freeze Doom Loop. As proposed by [64], an ERAM attacker can
inject entire frames, assembled and checked by the CAN controller send an overload frame at the first bit of IFS to falsely indicate
and abide by all bus access rules, such as arbitration. Contrastingly, that a node needs more time to process the received message. This
ERAM attackers can directly inject signals onto the bus at any time. cannot be done under CRAM because CAN controllers cannot be
The nature of the signals could vary from pulses to complete frames. programmed by software to generate overload frames. On receiving
This unlocks several previously unattainable features, such as: an overload frame, other nodes also send overload frames and bus
Arbitrary frame injection: ERAM attackers could inject bits one-by- traffic is delayed. This could repeat indefinitely without increasing
one to form any complete frame at any time. Beyond valid data any ECUs’ error counters, making it difficult for some IDSs to detect.
frames, this could vary from overload [64] and error frames [14, 34, Unorthodox Frames. Based on the arbitrary frame injection capa-
43, 48], to invalid frames, such as frames with a wrong CRC. bility, we find that the attacker could forge and inject frames that
Arbitrary non-frame injection: ERAM attackers could inject non- do not fully comply with the CAN standard, such as a message with
frames, such as pulses, bits [43], and partial frames [17, 29, 62]. This a data field longer than 8 bytes, or a remote frame with data. This
feature is significant as it allows the attacker to flip bits of valid could achieve various purposes such as causing errors or discover-
frames, overwrite frames, or cause synchronization problems. ing implementation mismatches between different CAN controllers
Arbitrary edge and width control: ERAM attackers can control the of insufficiently defined parts of the standard.
edges or widths of their injected signals [43, 64]. This could allow Arbitration Denial. By flipping a 1 to a 0 in the ID field of a
attackers to force nodes to resynchronize or exploit sample point message in [14, 29, 43], the victim loses arbitration and the message
differences among different CAN controllers. is delayed, potentially missing its deadline. The attacker could
Link Layer Rule Non-Compliance. The attacker’s control over perform this repeatedly to prevent the victim from ever gaining bus
the link layer extends to all its rules, such as arbitration, error states, access. To cover his tracks, the attacker can continue transmitting
and acknowledgment. The attacker may completely ignore the rules a frame after winning arbitration so other nodes see a valid data
or apply their own rules. For example, they may continue sending a frame and do not detect errors.
frame after being interrupted by an error frame, not transition to the Synchronization Disruption. When a victim transmits a 1, the at-
error-passive or bus-off states, or acknowledge their own frames. tacker can inject a 0 pulse after the synchronization segment [14, 43].
This could help them in many scenarios, such as circumventing The sender and receivers see a 1→0 edge outside synchronization
defense systems that rely on link layer rules (Sec. 4.3). segments and resynchronize (Sec. 2.1). Depending on their bit time
ERACAN: Defending Against an Emerging CAN Threat Model CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA

1 Receiver1 1
Sender Receiver parts of the frame to change the system’s definition of a valid signal.
sample point Receiver2 sample point Transmitting messages with GPIO, the attacker may also directly
sample point
0 sample point 0 control bit timing of his messages to emulate the characteristics of
other ECUs and evade bit timing based approaches [47, 56, 74].
(a) Janus frame. (b) Counterfeit frame. On Error Handling Defenses. Some defenses attempt to prevent
CRAM error-handling attacks by making it difficult for the attacker
Figure 4: Attacks exploiting sample point differences. to transmit a message simultaneously with the victim. This is done
by randomizing the message’s transmission time or parts of its ID.
ERAM’s ability to time attacks accurately and inject errors arbitrarily
settings, they may adjust their bit durations differently, lose syn- bypasses any of these defenses as it could launch the attack once
chronization, and experience communication errors. the message or the fixed part of its ID appears.
Janus Frames. In Fig. 4a, when two nodes have different sample On Cryptographic Approaches. Some cryptographic approaches
points and an attacker sends a bit with a 1→0 or 0→1 transitions embed secret tokens in fields such as the ID to provide sender
between their sample points, they read different values. The attacker authentication [25, 70]. They are not secure under ERAM because
can send a carefully chosen frame with such transitions so two attackers can wait after these tokens are transmitted and then hi-
nodes receive different contents and do not detect errors [64, 73]. jack the frame. Further, approaches that keep message or freshness
Counterfeit Frames. Extrapolating the Janus frame idea, we de- counters between senders and receivers [26, 50, 66] may be vulner-
duce and verify that an attacker can flip bits from 1 to 0 in a sender’s able to the double receive attack (Sec. 4.2.1) as it could cause the
message without causing errors. For example in Fig. 4b, when the legitimate transmitter to send a message with the same counter
sender sends a 1, the attacker injects a 0 pulse after the sender’s twice. Finally, for content authentication defenses that use a cen-
sample point that lasts after the receiver’s sample point. The sender tral authenticator [35], Janus and counterfeit frame attacks (Sec.
samples a 1 and does not detect bit errors, while the receiver sam- 4.2.1) could be used to falsify a legitimate frame to keep it looking
ples a 0. The attacker can flip bits in both the data and CRC fields to valid for the authenticator but containing false data for some or all
modify a message received by the receiver without causing errors. receivers, depending on their sample points.
On Timing Based Approaches. Defenses using message timings
4.2.2 Improved Attacks. ERAM abilities can improve certain CRAM to assess authenticity, such as natural intervals [53, 61, 72] or secret
attacks and provide more stealth, reliability, and flexibility. delays [57, 71] between messages, are vulnerable under ERAM. At-
ERAM Error Injection. While CRAM attackers can inject errors tackers can hijack or counterfeit messages to modify their contents
by simultaneous transmission which usually involves injecting without changing their transmission time, evading such defense.
preceded messages to synchronize two messages (Sec. 2.2.1), an On Payload Inspection Approaches. Since these approaches only
ERAM attacker could inject an error directly, making it stealthier process application layer information, they cannot detect low-level
and more deterministic [14, 34, 43, 48]. Further, while CRAM has ERAM attacks, as noted by [14]. Moreover, they may be vulnerable
limited control over the location or type of the error, ERAM attackers to Janus and counterfeit frames posturing a benign message to them
have substantial control over both by injecting bits or error frames while containing malicious data for other receivers.
at any location of their choosing in a victim message. On Using Link Layer Rules for Defense. Some approaches
Physical Fingerprint Corruption. Building on voltage corrup- use certain link layer rules for defense purposes. For example, re-
tion attacks proposed by Bhatia et al. [4], we conceive an improved searchers suggest identifying a message’s sender by pushing it to
physical fingerprint corruption attack. Bhatia’s technique involves the error passive state [58], which some defenses use to identify
causing several errors, transitioning a node into the error-passive attackers [60]. Other papers suggest pushing attacker nodes to the
state, cooperating between two attacking ECUs, and other require- bus-off state [57]. Due to the non-compliance capability (Sec. 4.1),
ments. In the improved attack, however, ERAM attackers directly none of these techniques could be used against ERAM attackers.
inject pulses that overlap with parts of a victim’s message to corrupt Notably, CopyCAN [37] calculates ECUs’ error counters by moni-
their physical characteristics without any such needs, making it toring the link layer and reading error frames. Although it could
stealthier and more convenient. limit some ERAM attacks that cause errors (e.g., frame hijacking), it
could not detect attacks that do not or distinguish genuine errors.
4.3 Impacts on Existing Defenses
On Physical Signal Based Approaches. ERAM abilities are prob- 5 ERACAN Design
lematic to systems using physical signals to identify attackers or
detect intrusions. For example, many approaches use physical sig- 5.1 Architecture and Operation Overview
nal features from a specific part of the message to check authentic- ERACAN consists of a single node that connects to the bus and com-
ity [12, 32, 55, 56]. ERAM attackers could manipulate these systems prehensively monitors the data link and physical layers. It extracts
in several ways. For example, attackers could leave such parts of the specific features to detect and classify all ERAM attacks (Sec. 4.2).
message intact, but hijack the frame after they elapse. For systems For certain attack types, ERACAN offers an attack prevention option
that take several samples all over the message with online updates to be enabled or disabled by the system administrator. To address
[10], they only detect spoofing of entire messages and struggle with performance challenges of such ubiquitous monitoring, ERACAN
ERAM attacks that only require injecting short pulses, as [14] points adopts a dual approach of delegation and smart checking. It delegates
out. Moreover, the attacker may gradually corrupt or hijack small all link layer surveillance to a customized CAN controller (ERACAN
CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA Zhaozhou Tang, et al.

Monitor Software
ECU Monitor 2 3 4 5
Hardware Start TDC Poll Timestamps Check Msg Validity & Authenticity Update Bit
Msg Edge & ADC Extract Bit Timing Authenticity, GPIO, Edge Count & No Timing
CAN Bus Timestamp Features Asymmetry Checks Model
TDC ID IRQ Attack
1 Attack
ERACAN ID, Wait for Msg has error Injected
Controller Interrupt Check Injected Error Error Attack Classification & 6
Anomaly Stop TDC
Asymmetry Check Optional Prevention
ADC & ADC
ECU Pulse Injection Check Legitimate Error
Voltage Anomaly

Figure 5: ERACAN monitor node architecture, workflow, and deployment on a CAN bus.

controller). For the physical layer, it uses a time-to-digital converter Asymmetry is an ECU’s unique physical fingerprint and depends
(TDC) to monitor time events, and an analog-to-digital converter on its transceiver switching characteristics [28, 56], signal reflec-
(ADC) to monitor voltage levels. However, they are monitored us- tion [36, 65], and load between the ECU and measuring unit [28, 56].
ing smart checking and only checked selectively based on attack Modeling Legitimate Bit Timing. We compute bit period and
scenarios. This greatly reduces the processing overhead. Below, we asymmetry measurements using all edges between a message’s
further describe these components and smart checking. ID and ACK fields. We model each ECU’s expected bit period and
ERACAN Controller. This customized CAN controller can be con- asymmetry using normal distributions 𝑁 (𝜇𝑇 , 𝜎𝑇2 ) and 𝑁 (𝜇𝐴 , 𝜎𝐴2 ).
figured to autonomously monitor certain link layer events. It stores Bit Timing Model Recreation. Bit timing models are recreated
information in registers and interrupts the software once events when a CAN bus is turned on after a period of inactivity. ECUs
occur. The software then queries and clears them after each inter- send calibration messages and ERACAN uses them to compute their
rupt. Moreover, if attack prevention is enabled, ERACAN controller distribution parameters and bit period variance within a message.
can inject errors to destroy malicious frames. Securing Model Recreation. ERACAN needs a cryptographic
TDC. ERACAN uses this to measure the timestamps of 1→0 and scheme that guarantees source authenticity and obfuscates the
0→1 edges of the signal from the transceiver. They are used to payload so attackers cannot predict it. Any scheme meeting these
extract and model two features: bit-period and asymmetry. We requirements can be used. In Appendix A, we explain an example
discuss their definition, extraction, and modeling in Sec. 5.2. lightweight scheme adopted from [57] for this step.
ADC. ERACAN uses this to measure the differential voltage levels Bit Timing Model Online Updates. If a message contains no
of the bus, which it uses to check for attackers’ error injections. errors and fails no legitimacy checks, ERACAN uses it to perform
Smart Checking Workflow. Fig. 5 shows ERACAN’s workflow. online updates to account for feature drift due to environmental
During operation, ERACAN controller continuously watches for sus- conditions. With each new measurement 𝑥, ERACAN updates distri-
picious link layer events and reads the ID of messages that appear bution parameters using Equations 3 and 4:
on the bus. TDC and ADC measurements are started only when a
𝜇𝑛 = 𝑤 𝜇𝑛−1 + (1 − 𝑤)𝑥 (3)
message’s ID field completes transmission. Initially, only TDC mea-
surements are used to extract the frame’s bit period and asymmetry
𝜎𝑛2 = 𝑤 [𝜎𝑛−1
2
+ (1 − 𝑤)(𝑥 − 𝜇𝑛−1 ) 2 ] (4)
in real-time. When its ACK field starts, ERACAN checks the mes-
sage’s bit period and asymmetry for validity and authenticity. If all A smaller 𝑤 gives new measurements a higher weight and helps
checks pass, ERACAN updates a model for these features. However, the model adapt to changes faster. For large environmental varia-
if a message is interrupted with an error, ERACAN checks if the error tions or low-frequency messages whose bit timing can accumulate
is legitimate or injected by the attacker. ERACAN checks bit timing substantial changes between messages, 𝑤 should be reduced.
first, and if no anomalies are found, only then does it process and Voltage Levels. Unlike sender identification approaches, ERACAN
check ADC measurements. When an attack is detected, ERACAN does not use voltage to achieve fine distinctions between ECUs, but
performs attack classification, and prevention if it is optionally only to distinguish between normal voltage levels and anomalies
enabled. We explain these procedures in detail in this section. caused by attacks. It uses a single feature in two scenarios: voltage
level variance to check for attack when a message contains errors
5.2 Feature Extraction and Modeling Details (Sec. 5.3), and mean voltage level to confirm if an attack is launched
by simultaneous transmission (Sec. 5.4). Since such distinctions
Bit Period: Equation 1 calculates an ECU’s bit period 𝑇 from the
are far more significant than differences among ECUs or under
time 𝑡 ↓↓ between consecutive 1→0 edges with 𝑛 ↓↓ bits in between:
environmental variations, fixed detection thresholds enable reliable
𝑡 ↓↓ performance (Sec. 8). Thus, ERACAN measures voltage levels once in
𝑇 = (1)
𝑛 ↓↓ a secure setting (e.g., during manufacturing). It records the expected
mean and variance of ECUs’ stable dominant voltage levels and
Asymmetry: Equation 2 computes an ECU’s asymmetry 𝐴 using
uses these to set fixed detection thresholds.
the time 𝑡 ↓↑ and the number of bits 𝑛 ↓↑ between a 1→0 edge and
Link Layer Information. We configure ERACAN controller to
the next 0→1 edge and its bit period 𝑇 :
report the following information: message IDs after their ID fields
𝐴 = 𝑡 ↓↑ − 𝑛 ↓↑𝑇 (2) terminate, the edge count between ID and ACK fields, errors and
ERACAN: Defending Against an Emerging CAN Threat Model CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA

Algorithm 1 Message Authenticity Check 1 1

Input: Mean asymmetry in CRC field (𝐴), ¯ authorized sender (𝑒) 0 0

Output: true if the message is authentic, false if not (a) During consecutive 1s. (b) At a 0→1 transition.
1: 𝜇𝐴 ← {𝜇𝐴1 , 𝜇𝐴2 , ..., 𝜇𝐴𝑛 } ⊲ Sorted list of ECUs’ asymmetries
2: 𝜎𝐴 ← {𝜎𝐴1 , 𝜎𝐴2 , ..., 𝜎𝐴𝑛 } ⊲ Created after model recreation Figure 6: Two possible locations of pulse injection.
3: if 𝐴¯ > 𝜇𝐴𝑒 + 5𝜎𝐴𝑒 or 𝐴¯ < 𝜇𝐴𝑒 − 5𝜎𝐴𝑒 then
4: return false

Voltage / V
5: end if 2
6: 𝑧𝑒 ← |(𝐴¯ − 𝜇𝐴𝑒 )/𝜎𝐴𝑒 |
7: 𝑧𝑒 −1 ← |(𝐴¯ − 𝜇𝐴𝑒 −1 )/𝜎𝐴𝑒 −1 | Attacker-injected bit
8: 𝑧𝑒+1 ← |(𝐴¯ − 𝜇𝐴𝑒+1 )/𝜎𝐴𝑒+1 | 0
9: return 𝑧𝑒 < 𝑧𝑒 −1 and 𝑧𝑒 < 𝑧𝑒+1 0 10 20 30 40 50 60 70 80
Samples

their types, overload frames, discrepancies in sampled bits, and Figure 7: Voltage of pulse injection at a 0→1 transition.
abnormal frame formats. These can be expanded or customized
based on security requirements and identified attack vectors.
could inject a 0 when the victim is transmitting multiple 1s (Fig. 6a).
5.3 Legitimacy Checks Since the attacker’s pulse is not transmitted based on the victim’s bit
Authenticity Check. ERACAN computes the mean asymmetry of period, its 1→0 edge is not aligned with the expected bit boundary.
the CRC field to determine if a message is authentic using Algo- ERACAN checks all edges up to the start of an error frame for this
rithm 1. ERACAN maintains a sorted list of all ECUs’ expected asym- anomaly (If the error is a CRC error, the start of the error frame
metries. It first compares if a message’s asymmetry deviates too is not checked because it is signaled by receivers). It calculates bit
much from the authorized sender. If not, it computes the distance period 𝑇 with all pairs of consecutive 1→0 edges using Equation 1.
to the authorized sender and two ECUs with the closest asymmetry. It considers the message suspicious if any 𝑇 satisfies Equation 6,
It then checks if the distance to the authorized sender is the closest. where 𝑛 is the same threshold as asymmetry check:
A message is authentic only if it passes both checks. |𝑇 − 𝜇𝑇𝑉 | > 𝑛𝜎𝑇𝑉 (6)
Optional Additional Authentication. For systems experienc-
ing high environmental variations where ECUs’ asymmetries may Pulse Injection Check Using Voltage. If pulse injection check
change abruptly, an optional check is added to eliminate any possi- using bit timing does not find anomalies, ERACAN further checks
ble false positives. If a message fails Algorithm 1, ERACAN compares voltage. This accounts for the attacker injecting a pulse at a victim’s
its asymmetry with the last message from the authorized sender 0→1 transition (Fig. 6b). Due to imperfect bus termination and
and two ECUs with the closest asymmetry. It is deemed illegitimate signal reflections [65], voltage level oscillates after the victim’s
if the difference with the authorized sender is not the smallest. falling edge. Such oscillations are superposed on the injected pulse,
GPIO Check. This detects if a message is transmitted using GPIO, causing distortions in Fig. 7. They increase voltage level variance
the most convenient and flexible link layer manipulation technique. by orders of magnitude. Fig. 8 shows where ERACAN looks for
These messages’ bit timing is not derived from the ECU’s oscillator abnormal voltage levels. After the attacker injects a 0, the sender
but programmed by software. The variance of bit periods within the transmits an error frame at the next bit. Depending on where the
message multiplies due to greater uncertainty of software timing. bit is injected, receivers transmit an error frame at the next bit or
ERACAN considers a message suspicious if its intra-message bit pe- until they detect a stuff error after six consecutive 0s. Up to twelve
riod variance is greater than the expected variance of its authorized consecutive 0s are observed [20]. The receivers transmit the last
sender by at least twice. six bits, while voltage level anomalies are within the previous bits.
Asymmetry Check. This detects simultaneous transmission and Therefore, ERACAN finds bits before the last six in superposed error
pulse injection near edges in a message, which inevitably increases flags (highlighted in Fig. 8), extracts voltage samples in a 500ns
asymmetry (Sec. 6). ERACAN considers a message suspicious if any window around every bit boundary, and computes the variance
of its asymmetry measurements satisfies the following equation: within each window. An anomaly is detected if the variance within
any window is larger than the expected variance of the victim’s
𝐴 > 𝜇𝐴𝑒 + 𝑛𝜎𝐴𝑒 (5) stable dominant voltage levels by at least ten times.
𝑛 is a configurable threshold. Increasing 𝑛 to cover a larger part Overload Frames Check. ERACAN controller signals to software
of the distribution increases both false negative and false positive if an overload frame is observed. On modern networks they must
rates. Its setting is optimal when false positive and false negative be transmitted by an attacker as modern CAN controllers do not
rates are equal and should be determined empirically for each ECU. initiate overload frames and only react to them [64]. For legacy net-
Edge Count Check. ERACAN checks if the TDC measures more works where legitimate overload frames could arise, as the standard
timestamps than the expected edge count acquired by ERACAN specifies at most two consecutive overload frames can be gener-
controller, in case additional edges are injected by an attacker. ated [20], ERACAN controller alerts if additional ones are observed.
Pulse Injection Check Using Bit Timing. This checks if an error Last EOF Bit Check. ERACAN controller signals to software if a
in a message is caused by an attacker’s pulse injection. An attacker message’s last EOF bit is 0 but other fields are valid. The 0 could
CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA Zhaozhou Tang, et al.

Attacker injects a 0
Monitor Victim Attacker
Sender Tx 0 0 1 0 0 0 0 0 0 1 1 1 ttrM ttrV ttrA
Receivers Tx 1 1 1 1 1 1 0 0 0 0 0 0 tpV→M tpA→V
CAN Bus 0 0 0 0 0 0 0 0 0 0 0 0
Start of sender’s error flags Start of receivers’ error flags
Figure 9: An example bus layout and propagation delays.

Figure 8: Error flags caused by error injection. identification using asymmetry in the CRC field and the first asym-
metry measurement of the message. It chooses the node with the
closest expected asymmetry to the measurements as the sender. If
the senders are different, the attack is frame hijacking since the first
only be transmitted by an attacker because no CAN controllers
asymmetry measurement should match the legitimate sender but
should send a 0 in this field if all previous message fields are valid.
the CRC field matches the attacker. Otherwise, it is a masquerading
Sampled Bits Discrepancies Check. ERACAN controller has two
attack as the entire message is sent by the attacker.
sets of sampling logic with different sample points. Their sampled
Attacks Failing Asymmetry or Edge Count Checks Only.
bits are compared in real-time. Any discrepancies indicate an attack
These could only be bit timing poisoning using pulse injection or
and ERACAN controller signals to software. To ensure discrepancies
simultaneous transmission. ERACAN again leverages voltage levels
in sampled bits between any nodes are visible, ERACAN controller’s
to distinguish each technique.
sample points could be set to the earliest (55.6%) and latest (90.9%)
allowed sample points according to protocol specifications [20]. 5.4.1 Attack Prevention Options. By default ERACAN only detects
Frame Format Check. ERACAN controller signals to software if and classifies attacks. Since ERACAN detects attacks with low false
a message does not fully comply with the CAN standard. This is positive rates in real-time, it can translate detection into prevention
an unorthodox frame from an attacker. Depending on their CAN for attacks compromising message integrity, including masquerad-
controller designs, legitimate ECUs could transmit certain kinds of ing, frame hijacking, Janus, and counterfeit frame attacks. ERACAN
unorthodox frames. Since ERACAN controller is implemented using offers prevention options for them that can be enabled per attack.
an FPGA, check policies can be customized based on what frame If enabled, ERACAN destroys messages with error frames if relevant
formats are not expected to be transmitted normally. checks fail (authenticity check for masquerading / frame hijacking
CRC Errors Check. ERACAN controller signals to software if a or sampled bits discrepancies check for Janus / counterfeit frames).
message is properly acknowledged by receivers but a CRC error is
signaled. This means the message is valid. The sender is operating 6 Security Analysis
correctly, and the CRC error could be injected by an attacker. Here we consider how ERACAN detects each ERAM attack, an at-
tacker’s potential evasion tactics, and ERACAN’s mitigations.
5.4 Attack Classification Masquerading and Frame Hijacking. Both attacks require the
If any check fails, ERACAN determines the attack type as follows. attacker to transmit the entire CRC field and fail authenticity check
Attacks Failing Controller Checks. Freeze doom loop, double using its asymmetry. If an attacker controls messages’ bit timing to
receive, Janus / counterfeit frame, and unorthodox frame attacks are emulate a victim by transmitting with GPIO, he fails GPIO check
classified based on the respective controller check they fail. even if he passes authenticity check.
Attacks Causing Errors. ERACAN distinguishes between synchro- Arbitration Denial. First, authenticity check confines an attacker
nization disruption, simultaneous transmission, or ERAM error injec- to launch the attack with his own ID. Then, since he must bypass
tion. Injecting pulses to disrupt synchronization causes additional the CAN controller, it is detected by GPIO check.
edges. Simultaneous transmission increases voltage levels after the ERAM Error Injection. ERACAN controller CRC errors check de-
ID field. ERACAN uses edge count and voltage levels to distinguish tects injecting CRC errors after the ACK field. Pulse injection check
them. Otherwise, ERAM error injection is the remaining possibility. detects injecting bit errors. A smart attacker could attempt to evade
Attacks Failing GPIO Check. ERACAN distinguishes between pulse injection check by accurately timing his injection to fall within
arbitration denial and bit timing poisoning. Bit timing poisoning the bound in Equation 6. The key difficulty is to accurately account
could also fail GPIO check if the attacker injects pulses near 1→ 0 for signal propagation delays through cables 𝑡𝑝 and transceiver
edges, changes a message’s bit period, and increases its variance. delays 𝑡𝑡𝑟 to translate the differential voltage into digital signals.
ERACAN confirms the attack is arbitration denial if none of the We consider an example bus layout in Fig. 9. The victim starts trans-
message’s asymmetry measurements match the legitimate sender mission at 𝑡 0 . The monitor and attacker each see the victim start
since the message is transmitted with another peripheral whose bit transmission at 𝑡 1 (Equation 7) and 𝑡 2 (Equation 8). The attacker
timing does not resemble its CAN controller. Otherwise, the attack then delays Δ𝑡 to inject a pulse at the mth bit in the message and
is bit timing poisoning since asymmetry measurements not altered the pulse arrives at the monitor at 𝑡 3 (Equation 9):
by the attacker still match the sender. 𝑡 1 = 𝑡 0 + 𝑡𝑡𝑟𝑉 + 𝑡𝑝𝑉 →𝑀 + 𝑡𝑡𝑟 𝑀 (7)
Attacks Failing Authenticity Check. If an attack fails authen-
ticity but not GPIO check, ERACAN distinguishes between mas- 𝑡 2 = 𝑡 0 + 𝑡𝑡𝑟𝑉 + 𝑡𝑝𝐴→𝑉 + 𝑡𝑡𝑟𝐴 (8)
querading attacks and frame hijacking. ERACAN performs sender 𝑡 3 = 𝑡 0 + 𝑡𝑡𝑟𝑉 + 2𝑡𝑝𝐴→𝑉 + 2𝑡𝑡𝑟𝐴 + 𝑡𝑝𝑉 →𝑀 + 𝑡𝑡𝑟 𝑀 + Δ𝑡 (9)
ERACAN: Defending Against an Emerging CAN Threat Model CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA

1 1 Checks & Online Updates

Timestamp Processing TC + TU
0 0
ID Payload ACK EOF IFS ID
(a) Advance a 1→0 edge. (b) Delay a 0→1 edge. TTP / Timestamp TAC Authenticity Check

Figure 10: Manipulating bit timing by injecting pulses. Figure 11: Processing by ERACAN in each message field.

Equation 10 derives the value of 𝑇 the monitor uses for pulse injec-
tion check based on Equation 1. Substituting it into Equation 6, the and stuff bits for feature calculation since the attacker can predict
attacker must satisfy Equation 11 to evade detection: them by reading the preceding content. A message is not used if it
is retransmitted after an error. This is in case the attacker learns
𝑡 3 − 𝑡 1 2𝑡𝑝𝐴→𝑉 + 2𝑡𝑡𝑟𝐴 + Δ𝑡 a message’s content, injects an error, and then poisons bit timing
𝑇 = = (10)
𝑚 𝑚 in the retransmitted message. We choose the scheme in Appendix
2𝑡𝑝𝐴→𝑉 + 2𝑡𝑡𝑟𝐴 + Δ𝑡 A as it is lightweight and meets both requirements. Any schemes
| − 𝜇𝑇𝑉 | ≤ 𝑛𝜎𝑇𝑉 (11) meeting both requirements, such as [27, 49], can also be used.
𝑚
The attacker must accurately estimate 𝑡𝑝𝐴→𝑉 and 𝑡𝑡𝑟𝐴 and adjust Attacks Detected by Controller Checks. Freeze doom loop, double
Δ𝑡. This is not possible without physical access and direct mea- receive, Janus / counterfeit frames, and unorthodox frames are de-
surements. He could use the typical 5ns/m to estimate 𝑡𝑝 [18] and tected by ERACAN controller overload frames, last EOF bit, sampled
obtain reference 𝑡𝑡𝑟 from the transceiver’s datasheet, but these esti- bits discrepancies, and frame format checks respectively (Sec. 5.3).
mates are highly inaccurate due to environmental conditions and
manufacturing variations. Thus, an attacker has minimal chances 7 Performance Analysis
to evade detection and inject a single error. To inject more errors
7.1 Performance Deadlines
and change the victim’s error state, the probability of consistently
evading detection decreases exponentially. Fig. 11 shows ERACAN’s mandatory processing steps for every
Synchronization Disruption. An attacker must inject a pulse message (steps 1 to 6 in Fig. 5). Other processing is only required
after the synchronization segment in a sender’s recessive bit. Since after an error or attack. They have the following deadlines.
the synchronization segment is at least 1/25 of a bit time [20], the Timestamp Processing. After a message’s ID field completes,
attacker’s pulse is at least 1/25 of a bit time after a bit boundary and ERACAN takes 𝑇𝑇 𝑃 to retrieve and process each edge timestamps.
can always be detected by pulse injection check using Equation 6. This must finish before the next edge arrives, in the worst case
Attacks Using Simultaneous Transmission. This technique is within one bit time (2𝜇s on 500kbps bus). As we show in Sec. 8.4, this
used to inject errors or poison bit timing. When two nodes transmit can often finish well within the deadline and provide opportunities
simultaneously, they do not see the end of the preceded message to leverage the idle time before the next edge for other processing.
at the same time due to propagation delays [51]. They do not start Authenticity Check. After the ACK field starts, ERACAN performs
transmission at exactly the same time. Their misaligned pulses over- authenticity check in 𝑇𝐴𝐶 . It must finish before the last EOF bit to
lap, increasing pulse width and asymmetry. This fails asymmetry enable attack prevention using error frames. The deadline is (2 bit
check. The attacker could not evade detection since the increase in ACK field + 6 bit EOF) = 8 bit time (16𝜇s on 500kbps bus). ERACAN
asymmetry depends on propagation delays outside his control. calculates a message’s mean asymmetry in the CRC field iteratively
Poisoning Attacks on Bit Timing. To manipulate bit timing using each new measurement during timestamp processing. This
measurements, an attacker could inject small pulses into the vic- adds to 𝑇𝑇 𝑃 but helps authenticity check meet its deadline because
tim’s message to introduce extra timestamps. This is detected by ERACAN only has to run Algorithm 1 after the ACK field.
edge count check. Alternatively, he could inject pulses close to vic- Legitimacy Checks and Online Updates. Besides authenticity
tim’s edges to advance a 1→0 edge (Fig. 10a) or delay a 0→1 edge check, ERACAN also performs GPIO, edge count, and asymmetry
(Fig. 10b). According to Equation 2, both increase asymmetry and checks, in a time totaling 𝑇𝐶 . It then performs online updates in 𝑇𝑈 .
are detected by asymmetry check. Similar to error injection, evad- They must finish before the next message’s ID field completes. In the
ing asymmetry check requires accurate timing and has low success worst case assuming 100% bus load and no bit stuffing, the deadline
rates. Moreover, even if the attacker succeeds, he can only increase is (2 bit ACK field + 7 bit EOF + 3 bit IFS + 1 bit SOF + 11 bit ID) =
a single asymmetry measurement to at most 𝜇𝐴 + 5𝜎𝐴 . The change 24 bit time (48𝜇s on 500 kbps bus). ERACAN computes a running
to 𝜇𝐴 modeled by ERACAN is bounded. To significantly change 𝜇𝐴 , bit period variance for GPIO check and performs asymmetry check
the attacker must inject multiple pulses in the same message to once a measurement is acquired. This amortizes the cost and leaves
poison a large portion of measurements. All of them need to evade more time for the most time-consuming online updates.
detection, and the chance of success decreases exponentially.
Securing Model Recreation. A cryptographic scheme providing 7.2 Memory Overhead
source authenticity and payload obfuscation is required to prevent ERACAN’s arithmetic operations use 4-byte floating point numbers.
spoofing and bit timing poisoning. Since attackers cannot predict For each ECU, ERACAN stores 5 model parameters: 𝜇𝐴 , 𝜎𝐴 , 𝜇𝑇 , 𝜎𝑇 ,
the payload, they cannot poison bit timing by preparing the same and intra-message bit period variance. For 𝑁 ECUs, this requires
message for simultaneous transmission or anticipating edge posi- (20×𝑁 ) bytes. ERACAN also needs to buffer a message’s timestamps,
tions and injecting pulses. Moreover, we do not use the CRC fields bit period, and asymmetry measurements until they are used by
CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA Zhaozhou Tang, et al.

Table 1: Testbed setup for CRAM experiments. Table 2: Experiments results of CRAM attacks on the testbed.

Node MCU Transceiver Distance To Monitor Attack Masquerading Bus-Off Bit Timing Poisoning
Detection Rate 100% 100% 100%
ECU1 Arduino Due TJA1051 40cm
False Positive 0% 0.02% 0.02%
ECU2 Arduino Due TJA1051 60cm
ECU3 STM32F334 SN65HVD230 110cm

Proportion / %

Proportion / %
ECU4 STM32H755 TJA1051 170cm 75 ECU1 60 ECU1 / 2
ECU2 ECU1 & 2
ECU5 STM32F334 SN65HVD230 200cm ECU3
50 ECU4 40
ECU5
25 20

online updates. If bits alternate between 1 and 0 in the data and 0 0

CRC fields of an 8-byte message, it contains 84 timestamps, and 84 −100 −50 0 0 100 200
measurements accordingly. No valid messages could contain more Asymmetry / ns Asymmetry / ns
timestamps. To be conservative, ERACAN needs enough memory to (a) In the absence of attacks. (b) Under error handling attacks.
buffer this amount of data (84 × 4 = 336 bytes).
Figure 12: Proportion of ECUs’ asymmetry per range.
8 Evaluation
We implement ERACAN to evaluate its security and performance
on a testbed and a real vehicle (2011 Chevy-Impala). start at 25°C (77°F), heat the room to 28°C (82°F), cool it down to 18°C
Implementation. We use a PYNQ-Z2 board as the monitor node. (64°F), and bring the temperature back to 25°C (77°F). We collect
PYNQ-Z2 offers an SoC with FPGA fabric and a 650MHz dual-core 550000 messages in three hours. As mentioned in Sec. 5.2, 𝑤 should
ARM Cortex-A9 processor. It supports security features such as be reduced in this scenario. To evaluate its impact, we first test three
TrustZone, key storage, and secure boot. Following prior work [52], values: 0.99975 (default 𝑤 for other experiments), 0.994875, and 0.99
we implement the TDC in the FPGA fabric based on [5]. We design without enabling the optional additional authentication (Sec. 5.3).
ERACAN controller by adding features to an open-source Verilog We get 7, 4, and 3 misclassifications respectively. Next, we enable
CAN controller design [42]. They interact with the ARM proces- the additional authentication. This eliminates all misclassification
sor using interrupts and memory-mapped interfaces. To evaluate for all three 𝑤, reducing the false positive rate to 0%.
ERACAN’s security, we collect TDC measurements, ERACAN con- Error-Handling Attacks. We use one ECU to launch bus-off
troller information, and acquire voltage using a PicoScope 5244D (Sec. 2.2.2) and bit timing poisoning (Sec. 6) attacks on another
oscilloscope at a sampling rate of 20MS/s and a resolution of 8 bit. ECU using simultaneous transmission. We test all attacker-victim
We further implement bit timing features extraction, modeling, and pairs. For each pair we collect 2500 messages from each ECU and
checks on the ARM processor to evaluate its performance. 2500 messages under attack. We achieve 100% detection and a 0.02%
Choosing 𝑤. We collect messages, compute a moving average of false positive rate. Fig. 12b shows an example of ECU1 attacking
asymmetry in the last 1 second, and exhaustively search between ECU2. Asymmetries of all attacked messages are larger than normal
0.9 and 1 for a 𝑤 in Equation 3 that best approximates this value. 𝑤 ones from any single ECU by a significant margin.
are 0.99975 and 0.99972 for the testbed and vehicle respectively.
Choosing Detection Threshold. To choose the threshold 𝑛 in 8.2 ERAM Security Evaluation on Testbed
Equations 5 and 6, we run error injection attack and search for the We build a 500kbps testbed with an attacker, a transmitter, and a
value that yields equal false positive and negative rates. The chosen listener. The attacker and transmitter both transmit normal mes-
threshold is 4.8 and 4.5 respectively for the testbed and vehicle. sages every 10ms. The attacker launches ERAM attacks (Table 3) on
some of the transmitter’s messages using GPIO. For each attack,
8.1 CRAM Security Evaluation on Testbed we record all bus traffic until we collect 2500 attacked messages.
We set up a 500kbps testbed with 5 ECUs configured according to Arbitration Denial. We compare the intra-message bit period
Table 1 to test ERACAN against CRAM attacks in Table 2. variance of attacked messages from the attacker’s GPIO to messages
Sender Identification. We let each ECU transmit 8-byte messages from its CAN controller, and observe at least a four-fold increase.
with random data every 10ms. We collect 50000 messages and use With GPIO check, we achieve 100% detection and no false positives.
the first 100 messages from each ECU for model creation. As shown Detecting Error Injection Using Bit Timing. We test two cases.
in Fig. 12a, ECUs have distinct asymmetries. Therefore we identify First, we estimate delays and accurately time the attacker’s pulse
senders of all messages with 100% accuracy. injection according to Equation 11. Second, we do not estimate
Masquerading Attacks. We let each ECU transmit 10000 messages, delays. We achieve 99.9% and 99.8% detection respectively and
1/5 of which are under the ID of each ECU. Thus, bus traffic contains a 0.04% false positive rate. Estimating delays does not help the
legitimate messages and masquerading attacks for every attacker- attacker evade detection since estimations are far from accurate.
victim pair. We achieve 100% detection and no false positives. Detecting Error Injection Using Voltage. We observe that at-
Environmental Impacts. We reduce message periods to 100ms tacks increase voltage level variance by at least 12 times. We achieve
and repeat sender identification under temperature variations. We 100% detection and no false positives.
ERACAN: Defending Against an Emerging CAN Threat Model CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA

Table 3: Experiments results of ERAM attacks on the testbed.

Frame Error Arbitration Synch. Janus Counterfeit Freeze Double Unorthodox Bit Timing
Attack
Hijacking Injection Denial Disruption Frame Frame D. Loop Receive Frame Poisoning
Detection Rate 100% 99.8-100% 100% 100% 100% 100% 100% 100% 100% 99.9-100%
False Positive 0% 0-0.04% 0% 0.04% 0% 0% 0% 0% 0% 0.02%
Percent

False Negative Table 4: Attack prevention results.

0.25 False Positive

0.00 Frame Janus Counterfeit

Attack Masquerading
3.0 3.5 4.0 4.5 5.0 5.5 6.0 Hijacking Frame Frame
Detection Threshold Prevention 100% 100% 100% 100%

Figure 13: Influence of detection threshold.

Attack Prevention. We let the attacker launch each attack in Ta-

ble 4 2500 times. ERACAN detects and destroys all attacked messages
Synchronization Disruption. We set different bit segments for with error frames, achieving 100% prevention.
the transmitter and listener so they adjust bit timing differently Attack Classification. We launch seven attacks on a 5-ECU testbed:
when resynchronizing. We let the attacker inject pulses when the masquerading, error-handling attacks using simultaneous trans-
transmitter sends recessive bits and confirm the attack succeeds mission, synchronization disruption, ERAM error injection, frame
when the listener raises a CRC error. We achieve 100% detection hijacking, arbitration denial, and bit timing poisoning with pulse
and a 0.04% false positive rate. injection. Other attacks are not tested because they can be easily
Janus and Counterfeit Frames. We set the listen’s sample point classified using ERACAN controller checks. Each attack is launched
to 88.9%, and adjust the transmitter’s sample point until attacks 2500 times. We achieve a 99.8% overall classification accuracy. We
succeed reliably when set to 77.8%. The attacker transmits Janus misclassify attack types only in two scenarios. 0.3% of masquerad-
frames read differently by the transmitter and listener, and launches ing attacks are misclassified as frame hijacking. This happens when
counterfeit frame attacks on some of the transmitter’s messages. two nodes’ asymmetries are close, and the first asymmetry mea-
Without setting its sample points to the extreme (Sec. 5.3), ERACAN surement in the message matches a node other than the attacker
controller already detects attacks with 100% accuracy and raises no due to its natural variations. 1.2% of arbitration denial attacks are
false positives when its sample points are set to 65% and 90%. misclassified as bit timing poisoning. This happens when some
Unorthodox Frames. We let the attacker transmit two types of asymmetry measurements of the message happen to match the
unorthodox frames: frames with data fields longer than 8 bytes and legitimate sender, although its chance is low, as our results show.
remote frames with data. We implement their detection policies
in ERACAN controller and achieve 100% detection with no false 8.3 Security Evaluation on Real Vehicle
positives. For other kinds of unorthodox frames, ERACAN controller Our test vehicle has four ECUs on a 500kbps CAN bus. We connect
can be conveniently extended with respective detection policies. ERACAN monitor node and an attacker node to its OBD-II port and
Bit Timing Poisoning. We let the attacker corrupt the transmit- perform experiments in Table 5.
ter’s bit timing with pulse injection. The detection rate is 99.9% if Sender Identification. We collect ECUs’ bit timing over four days
four measurements in a message are altered, and tends to 100% if with varying weathers and temperatures. We identify message
more are altered. The false positive rate is 0.02%. In our test vehicle senders with 100% accuracy. This translates to 100% detection for
a message contains 18.6 measurements on average. Attackers can masquerading attacks by in-vehicle ECUs and no false positives.
only poison a small part of a single message, and the chance to Frame Hijacking. We achieve 100% detection. CRC fields of at-
poison a large portion of ERACAN training set is negligible. tacked messages contain bit timing of the attacker. Although ERA-
Frame Hijacking, Freeze Doom Loop, and Double Receive. CAN has never modeled the attacker’s bit timing before, it can still
All these attacks are detected 100% with no false positives. distinguish them from in-vehicle ECUs.
Detection Threshold Impacts. To evaluate the impact of the Detecting Error Injection Using Bit Timing. We achieve 99.7%
detection threshold, we test thresholds from 3 to 6 for error injection. detection. We observe that ECUs’ bit periods have very small varia-
As shown in Fig. 13, its impact on false positives is far greater. tions (maximum 𝜎𝑇 is 672ps). According to Equation 6, it is unreal-
Increasing the threshold from 3 to 5 increases the coverage of istic for a remote attacker to evade detection since he must inject
the normal bit timing distribution from 99.7% to 99.9999% and an error in a window shorter than 7ns.
reduces false positives by orders of magnitude. Conversely, when Detecting Error Injection Using Voltage. We measure the vari-
the threshold increases, the allowed time window for attackers to ance of ECUs’ stable dominant voltage levels on the first day and
inject a pulse without being detected (Equation 11) only increases set a fixed detection threshold. We launch attacks on the following
by a few nanoseconds. Their chance of evading detection, and two days. We achieve 100% detection on both days using the fixed
consequently the false negative rate, does not change significantly. threshold despite changes in ECUs’ voltage features across days.
CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA Zhaozhou Tang, et al.

Table 5: Real vehicle experiments results.

Experiment Sender Identification Frame Hijacking Error Injection Synch. Disruption Freeze D. Loop Double Receive
Accuracy 100% 100% 99.7-100% 100% 100% 100%
Asymmetry / ns

Asymmetry / ns
Reference Reference Table 6: ERACAN average authenticity check latency.
120 Poisoned 61.4 Poisoned
100
61.2 𝑁𝐸𝐶𝑈 5 6 7 8 9 10
80
Latency / 𝜇s 0.263 0.250 0.250 0.256 0.265 0.265
60 61.0

0 5000 0 5000
Messages Messages Table 7: ERACAN operation latencies.
(a) Without asymmetry check. (b) With asymmetry check.
Processing Stage Average Worst-Case Deadline
Figure 14: Asymmetry learned from online updates. Timestamp Processing 0.72𝜇s 1.34𝜇s 2𝜇s
Authenticity Check 0.26𝜇s 0.81𝜇s 16𝜇s
Checks & Online Updates 4.77𝜇s 21.4𝜇s 48𝜇s
Bit Timing Poisoning. We let the attacker poison bit timing using
pulse injection on one ID of an ECU. The attacker starts by cor-
rupting a small portion of a message, then gradually increases the messages is at maximum (Sec. 7.2), online updates take 32.8𝜇s. This
amount of corruption. We perform online updates on the IDs not most pessimistic estimate is still within the 48𝜇s deadline.
poisoned by the attacker and use this as a reference for the victim’s Real-Time Capability. We calculate the average and worst-case
true bit timing. We then perform online updates using all mes- latencies of each processing stage and compare them with the
sages including poisoned ones, with or without asymmetry check deadlines in Table 7. To calculate online updates latency, we use
enabled, and compare the learned asymmetry with the reference. our profiling results and the average and maximum number of
Without asymmetry check, the attacker successfully tricks ERACAN measurements per message from our test vehicle (18.6 and 26). All
into gradually learning a larger asymmetry as in Fig. 14a. With operations meet deadlines. Therefore, ERACAN can operate on a
asymmetry check the attack fails. The ECU’s asymmetry learned 500kbps CAN bus loaded up to 100% and guarantee all detected
by ERACAN closely resembles the reference as in Fig. 14b. masquerading and frame hijacking attacks can be prevented.
Double Receive, Freeze Doom Loop, and Synch. Disruption. Memory Footprint. We measure the code and data size of our
We achieve 100% detection for all of these attacks using ERACAN implementation and find them to be 16.7kB and 1.44kB, respectively.
controller checks or pulse injection check. As many recent commercial automotive-grade FPGAs offer at least
256kB on-chip memory [3], this overhead is reasonable.
8.4 Performance Evaluation
To test ERACAN’s feasibility and abilities to operate in real-time, 9 Benchmark Comparison
we connect it to a testbed with 5 ECUs operating at 500kbps and ERACAN is designed for ERAM attacks which other defenses do not
profile its latency as it processes 20000 messages. protect from, so it is hard to compare its performance with other
Timestamp Processing. ERACAN takes 0.4𝜇s on average to re- defenses on the same attack set. Instead, we compare ERACAN with
trieve one TDC timestamp and another 0.21𝜇s to calculate bit pe- separate defense categories, followed by its performance on CRAM
riod or asymmetry. This is well within the 2𝜇s deadline. Therefore, attacks that other systems also defend against.
ERACAN uses the remaining time for other processing, such as asym- Compared to Cryptography and Secret Delay IDS. As shown
metry checks. Adding them brings the processing time to 0.72𝜇s in Table 8, these approaches guarantee message authenticity under
on average and 1.34𝜇s in the worst case, still within the deadline. CRAM. They do not protect against error-handling attacks except
Authenticity Check. For 5 ECUs, authenticity check takes 0.26𝜇s for ZBCAN [57]. Under ERAM, all secret delay approaches and some
on average and 0.81𝜇s in the worst case. We experiment with up to cryptographic approaches lose their security guarantees (Sec. 4.3).
10 ECUs and show their average latency in Table. 6. The latency is Furthermore, they offer no security against the wide range of new
almost constant and it only takes 0.27𝜇s with 10 ECUs. Deadlines ERAM attacks (Sec. 4.2). ERACAN detects both CRAM attacks as
are always met despite the different number of ECUs on the testbed. well as all ERAM attacks. It is the first to offer attack classification,
GPIO and Edge Count Checks. GPIO check takes 33.8ns on aver- enabling intrusion responses to build on its output. Furthermore,
age and 70.8ns in the worst case. Edge count check takes 0.20𝜇s on ERACAN does not increase busload or reschedule bus traffic, which
average and 0.22𝜇s in the worst case. is required for some of these approaches.
Online Updates. It takes 0.23𝜇s on average and 0.78𝜇s at most to Compared to Physical Signal IDS. As shown in Table 8, they
process one asymmetry and bit period measurement. If every update only detect CRAM masquerading attacks but not error-handling
takes the worst-case 0.78𝜇s and the number of measurements in attacks, except for VoltageIDS [13]. However, some are evadable
ERACAN: Defending Against an Emerging CAN Threat Model CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA

Table 8: How ERACAN compares with other defense systems.

Attacks Features Cost

Spoofing Error Handling ERAM Single-Msg Classify Increase Modify
Defense Approach
CRAM ERAM CRAM ERAM Attacks Detection Attacks Busload Traffic
Cryptography [25, 35, 49, 50] G
# # # # ✓ X ✓ X
Secret Delay IDS [57, 71] # G
# # # ✓ X X ✓
Physical Signal IDS [13, 32, 52, 56] G
# #
G # # ✓ X X X
Interval / Clk-Skew IDS [11, 53, 72] # # # # X X X X
Payload Inspection IDS [1, 38, 67] # # # # X X X X
ERACAN ✓ ✓ X X

Table 9: Benchmarking ERACAN authenticity check latency. Table 10: Performance comparison on masquerading attacks.

EASI [32] ASSASSIN [56] SPARTA [55] ERACAN Defense System Detection Prevention Deployment Cost

1.02𝜇s*𝑁𝐸𝐶𝑈 0.94𝜇s*𝑁𝐸𝐶𝑈 1.15𝜇s 0.26𝜇s EASI [32] 99.66% - 1 Monitor Node

ASSASSIN [56] 99.02% - 1 Monitor Node
1 Monitor Node +
EdgeTDC [52] 100% -
Double Cable Length
under ERAM and they do not detect any new ERAM attacks. ERACAN 1 Monitor Node +
ZBCAN [57] 98.5% 98.5%
offers stronger security by detecting all CRAM and ERAM attacks. Reschedule Bus Traffic
ERACAN 99.99%+ 99.99%+ 1 Monitor Node
Compared to Interval and Payload Inspection IDS. As Table 8
shows, these approaches only detect CRAM message injection but
can be evaded by ERAM tactics. ERACAN protects against the full
range of CRAM and ERAM attacks. Furthermore, ERACAN offers injection) and bit timing poisoning attacks. Specifically, for error-
single message detection to ensure no low-level attacks can pass handling attacks, there is a 0-0.04% chance ERACAN treats a genuine
unnoticed, which some of these defenses do not offer. error as an attack. These misclassifications only relate to whether
Operation Latency. Table 9 compares ERACAN’s average message errors (uncommon on a healthy bus) are malicious and do not affect
authenticity check latency with three recent lightweight defenses, normal messages. We can build on CopyCAN’s [37] idea of reading
assuming all systems use a 650MHz processor. For a fair comparison, error frames and tracking ECUs’ error counters to further reduce
we exclude the time to take measurements and extract features. false alarms. Namely, ERACAN can alert only when an ECU’s error
The remaining processing steps are performed by the CPU and counter reaches a threshold and a large portion of its past errors
their latency does not depend on the measuring equipment used. are suspicious, instead of for single errors, because it is much less
ERACAN’s latency is the lowest. Compared to EASI and ASASSIN, likely that multiple genuine errors are all classified as malicious.
ERACAN’s latency is independent of the number of ECUs and allows Finally, ERACAN does not take any intrusive actions against error-
it to scale to a CAN bus with more ECUs. handling attacks. As such, the consequences of misclassifications
Masquerading Attacks. Table 10 compares ERACAN’s perfor- are limited to raising an alarm. For bit timing poisoning attacks, the
mance on masquerading attacks with four latest defenses offering false positive rate is 0.02%. The only aim of this attack is to poison
single message detection. ERACAN’s detection rate beats all systems the online updates process, not to falsify data or impersonate other
except for EdgeTDC, whose high performance comes at the cost ECUs. Consequently, ERACAN does not destroy these messages and
of significant hardware changes by doubling the cable length [52]. only excludes them from online updates.
ERACAN offers guaranteed prevention of all detected masquerading Possible Extensions. In Sec. 5.3, authenticity check only uses the
attacks, which only ZBCAN offers [57]. Unlike ZBCAN, ERACAN mean asymmetry of the CRC field. We can extend it with other sta-
achieves this without rescheduling bus traffic. tistical measures to slightly improve its accuracy. We can calculate
both a message’s mean asymmetry and variance and use a t-test to
10 Discussion and Limitations assess if its distribution is the same as its authorized sender. This
Corrupted Payloads. ERACAN mainly aims to fill the research could be more reliable as it accounts for the variability of samples
gap in emerging ERAM attacks. Detecting an ECU corrupting the and remains robust if ECUs’ bit timing is not normally distributed.
payloads of its own messages, an old CRAM tactic, requires payload However, it incurs more processing time. Similarly, ERACAN could
inspection. This is orthogonal to ERACAN’s goal. Good solutions be extended to monitor several buses operating at different security
already exist [1, 38, 67] and can be integrated. ERACAN offers addi- levels as was proposed for other buses [15, 16].
tional security as it cannot be deceived by Janus frames that look Non-GPIO Peripherals. In our evaluations, we focus mainly on
benign to the monitor but malicious to other nodes (Sec. 4.3). the GPIO as it is the most versatile and convenient peripheral.
False Positive Consequences. The only two cases where ERACAN Although ERAM attacks can be launched with other peripherals,
has non-zero false positive rates are with error-handling (e.g., error ERACAN will maintain high detection performance since most of
CCS ’24, October 14–18, 2024, Salt Lake City, UT, USA Zhaozhou Tang, et al.

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