UNIT-3 CONTROL UNIT

Computer Instructions

Computer instructions are a set of machine language instructions that a particular

processor understands and executes. A computer performs tasks on the basis of the
instruction provided.

An instruction details the CPU of "What to Execute?", "Where to Execute?" and "How
to Execute?".

For example, a code written by the programmer as TOTAL = TOTAL + SUBTOTAL is

converted as an instruction(s) that tells the CPU to add the contents of the two
memory locations where the variables TOTAL and SUBTOTAL are stored and put the
result in location TOTAL.
 Instruction format
Every CPU has an Instruction Set and format for the instructions. Essentially an
instruction consists of minimum two components i.e the instruction code (opcode)
and the operand for the instruction.

Task to be performed, called the operation code (Opcode), and the data
to be operated upon, called the operand.

The operands include the input data of the operation and the results
that are produced.
 Types of Instructions in Computer Architecture

A computer’s instructions can be any length and have any number of addresses. The
arrangement of a computer’s registers determines the different address fields in the
instruction format.
The instruction can be classified as three, two, and one address instruction or zero
address instruction, depending on the number of address fields.

1. Zero Address Instructions

In zero address instructions, the positions of the operands are implicitly represented.
These instructions use a structure called a pushdown stack to hold operands. These
instructions do not specify any operands or addresses.
The PUSH and POP instructions need an address field to specify the operand that
communicates with the stack.

To evaluate an expression, it is first converted to reverse Polish Notation i.e. Postfix

Notation.
PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location
 One Address Instructions
These instructions specify one operand or address, which typically refers to a memory
location or register. The instruction operates on the contents of that operand, and the
result may be stored in the same or a different location.

This uses an implied ACCUMULATOR register for data manipulation. One operand is in
the accumulator and the other is in the register or memory location. Implied means that
the CPU already knows that one operand is in the accumulator so there is no need to
specify it.
 Expression: X = (A+B)*(C+D)
AC is accumulator
M[ ] is any memory location
M[T] is temporary location

LOAD A AC = M[A]
ADD B AC = AC + M[B]
STORE T M[T] = AC
LOAD C AC = M[C]
ADD D AC = AC + M[D]
MUL T AC = AC * M[T]
STORE X M[X] = AC
 Two Address Instructions

These instructions specify two operands or addresses, which may be memory locations
or registers. The instruction operates on the contents of both operands, and the result
may be stored in the same or a different location.

For example, a two-address instruction might add the contents of two registers together
and store the result in one of the registers.
 Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[ ] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]
MOV R2, C R2 = M[C]
ADD R2, D R2 = R2 + M[D]
MUL R1, R2 R1 = R1 * R2
MOV X, R1 M[X] = R1
 Three Address Instructions

These instructions specify three operands or addresses, which may be memory locations
or registers. The instruction operates on the contents of all three operands, and the result
may be stored in the same or a different location. For example, a three-address instruction
might multiply the contents of two registers together and add the contents of a third
register, storing the result in a fourth register.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]
MUL X, R1, R2 M[X] = R1 * R2
Instruction Cycle

The execution instructions define the instruction cycle. This is the thorough methodology computer
processors use for executing a given instruction.

Every processor shows a three-step instruction cycle. These three steps of the instruction execution
cycle are,
1.Fetch:
The processor copies the instruction data captured from the RAM.

2. Decode:
Decoded captured data is transferred to the unit for execution.

3. Execute:
Instruction is finally executed. The result is then registered in the processor or RAM (memory
address).
Registers Involved In Each Instruction Cycle:

Memory address registers(MAR) : It is connected to System

Bus address lines. It specifies the address of a read or write
operation in memory.

Memory Buffer Register(MBR) : It is connected to the data

lines of the system bus. It is connected to the system bus
Data Lines. It holds the memory value to be stored, or the last
value read from the memory.

Program Counter(PC) : Holds the address of the next

instruction to be fetched.

Instruction Register(IR) : Holds the last instruction fetched.

Fetch instruction cycle:
The address of the next instruction to execute is in the Program Counter(PC) at the beginning of the
fetch cycle.

Step 1: The address in the program counter is transferred to the Memory Address Register(MAR), as
this is the only register that is connected to the system bus address lines.
Step 2: The address in MAR is put on the address bus, now a Read order is provided by the control
unit on the control bus, and the result appears on the data bus and is then copied into the memory
buffer register. Program counter is incremented by one, to get ready for the next instruction. These
two acts can be carried out concurrently to save time.
Step 3: The content of the MBR is moved to the instruction register(IR).

Instruction fetch cycle consist of four micro-operation:

T1: MAR PC
T2: MBR memory
PC PC + stepsize or length of instruction
T3: IR MBR
Decode instruction cycle:

The next move is to fetch source operands once an instruction is fetched. Indirect addressing (it
can be obtained by any addressing mode, here it is done by indirect addressing) is obtained by
Source Operand. You don't need to fetch register-based operands. If the opcode is executed, it will
require a similar process to store the result in main memory.

Microoperations take place:

T1: MAR IR(address)

T2: MBR Memory
T3: IR(address) (MBR(Address))

Step 1: The instruction address field is passed to the MAR. This is used to fetch the operand's
address.
Step 2: The address field of the IR is updated from the MBR.
Step 3: The IR is now in the state. Now IR is ready for the execute cycle.
Execute instruction Cycle

The initial cycles are predictable and quick. Each requires simple , small, and fixed micro-operation
sequences. The same micro-operation is repeated every time around in each event. Execute
instruction cycle is different from them. Like, there is N different series of micro-operations that
can occur for a computer with different N opcodes.

Example:

ADD R , X

T1: MAR (IR(address))

T2: MBR Memory
T3: R (R) + (MBR)

Step 1: The address portion of IR is loaded into the MAR.

Step 2: The address field of the IR is updated from the MBR, so the reference memory location is
read.
Step 3: Now, the contents of R and MBR are added by the ALU.
MICROOPERATIONS

A microoperation is an elementary operation performed on the information stored in one or more

registers.
• The result of the operation may replace the previous binary information of a register or may be
transferred to another register.
• Examples of microoperations are shift, count, clear, and load.

The micro-operations in computers are classified into the following categories:

1. Register transfer micro-operations: These type of micro operations are used to transfer binary
information from one register to another.

2. Arithmetic micro-operations : These micro-operations are used to perform some arithmetic

operations on numeric data stored in the registers.

3. Logic micro-operations: These micro operations are used to perform bit style operations /
manipulations on non numeric data.

4. Shift micro operations: As their name suggests they are used to perform shift operations in
data store in registers.
1. Register transfer micro-operations

• Information transfer from one register to another is designated in symbolic form by means of a replacement
operator.
• The statement R2← R1 denotes a transfer of the content of register R1 into register R2. It designates a
replacement of the content of R2 by the content of R1. By definition, the content of the source register R 1
does not change after the transfer.
• If we want the transfer to occur only under a predetermined control condition then it can be shown by an if-
then statement.
if (P=1) then R2← R1
P is the control signal generated by a control section.
• We can separate the control variables from the register transfer operation by specifying a Control Function.
Control function is a Boolean variable that is equal to 0 or 1. Control function is included in the statement as
P: R2← R1
Control condition is terminated by a colon implies transfer operation be executed by the hardware only if P=1.
The letter n will be used to indicate any number of bits for the register. It will be replaced by an actual number
when the length of the register is known. Register R2 has a load input that is activated by the control variable P.
2. Arithmetic micro-operations
The basic arithmetic micro-operations are

• Addition
R3 ← R1 + R2
It states that the contents of R1 are added to contents of R2 and sum is transferred to R3.
To implement this statement hardware requires 3 registers and digital component that performs
addition
• Subtraction
Subtraction is most often implemented through complementation and addition.
The subtract operation is specified by the following statement
R3 ← R1 + R2 + 1
Adding the contents of R1 to the 2's complement of R2 is equivalent to R1-R2.

• Increment
D=A+1
Firstly we have a direct transfer from input A to output D, then the value of A is incremented by 1.

• Decrement:
D = A -1 + 1=A, which causes a direct transfer from input A to output D.
3. Logic micro-operations

Logic microoperations specify binary operations for strings of bits stored in registers.
These operations consider each bit of the register separately and treat them as binary variables.
For example, the exclusive-OR microoperation with the contents of two registers R1 and R2 is symbolized by the statement

It specifies a logic microoperation to be executed on the individual bits of the registers provided that the control variable P = 1.

For example, the content of R1 is 1010 and content of R2 is 1100. The logic computation :
1 0 1 0 content of R1
1 1 0 0 content of R2
0 1 1 0 content of R1 after P = 1

There are 16 different logic operations that can be performed with two binary variables.
Shift Microoperations:
➢ Shift microoperations are used for serial transfer of data.
➢ The contents of a register can be shifted to the left or the right.
➢ During a shift-left operation the serial input transfers a bit into the rightmost position.
➢ During a shift-right operation the serial input transfers a bit into the leftmost position.
➢ There are three types of shifts: logical, circular, and arithmetic.
➢ The symbolic notation for the shift microoperations is shown in Table
PROGRAM CONTROL

Instructions are always stored in successive memory locations.

Each time an instruction is fetched from memory, the program counter is incremented so that it contains the
address of the next instruction in sequence.
Specifically, program control instruction when executed may change the address value in program counter and cause the
flow of control to be altered.

The change in the content of the program counter can cause an interrupt/break in the instruction execution. However, the
program control instructions control the flow of program execution and are capable of branching to different program
segments.

Some of the program control instructions are :

Branch BR
Jump JMP
Skip SKP
Call Call
Return RET
Compare (by Subtraction) CMP
 RISC and CISC

RISC and CISC are two different types of computer architectures that are used to design the
microprocessors that are found in computers. The fundamental difference between RISC and
CISC is that RISC (Reduced Instruction Set Computer) includes simple instructions and
takes one cycle, while the CISC (Complex Instruction Set Computer) includes complex
instructions and takes multiple cycles.

RISC (Reduced Instruction Set Computer)

It is a microprocessor architecture with a simple collection and highly customized set of
instructions. It is built to minimize the instruction execution time by optimizing and limiting the
number of instructions. It means each instruction cycle requires only one clock cycle, and each
cycle contains three parameters: fetch, decode and execute.

Characteristics of a RISC Processor

• A RISC processor has a few instructions.
• RISC processor has a few addressing modes.
• In the RISC processor, all operations are performed within the registers of the CPU.
• RISC processor can be of fixed-length.
• RISC can be hardwired rather than micro-programmed control.
• RISC is used for single-cycle instruction execution.
• RISC processor has easily decodable instruction format.
• Pipelining technique
• It uses LOAD and STORE instruction to access the memory location.
 It is a highly customized set of instructions used in
portable devices due to system reliability such as
Apple iPod, mobiles/smartphones

CISC (Complex Instruction Set Computer)

The CISC processor architecture comprises a complex instruction set. A CISC processor has a
variable-length instruction format. In this processor architecture, the instructions that require
register operands can take only two bytes.
In a CISC processor architecture, the instructions which require two memory addresses can take
five bytes to comprise the complete instruction code. Therefore, in a CISC processor, the execution
of instructions may take a varying number of clock cycles. The CISC processor also provides direct
manipulation of operands that are stored in the memory.
Characteristics of a CISC processor architecture

•CISC can have variable-length instruction formats.

•It supports a set of a large number of instructions, typically from 100 to 250 instructions.
•It has a large variety of addressing modes, typically from 5 to 20 different modes.
•CISC has some instructions which perform specialized tasks and are used infrequently.

The CISC architecture helps reduce program code

by embedding multiple operations on each
program instruction, which makes the CISC
processor more complex. The CISC architecture-
based computer is designed to decrease memory
costs because large programs or instruction
required large memory space to store the data,
thus increasing the memory requirement, and a
large collection of memory increases the memory
cost, which makes them more expensive.
 RISC CISC
It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.
It emphasizes on software to optimize the instruction set. It emphasizes on hardware to optimize the instruction set.
It is a hard wired unit of programming in the RISC Processor. Microprogramming unit in CISC Processor.
It requires multiple register sets to store the instruction. It requires a single register set to store the instruction.
RISC has simple decoding of instruction. CISC has complex decoding of instruction.
Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.
It uses a limited number of instruction that requires less time to execute It uses a large number of instruction that requires more time to execute
the instructions. the instructions.
It uses LOAD and STORE that are independent instructions in the It uses LOAD and STORE instruction in the memory-to-memory interaction
register-to-register a program's interaction. of a program.
RISC has more transistors on memory registers. CISC has transistors to store complex instructions.
The execution time of RISC is very short. The execution time of CISC is longer.
RISC architecture can be used with high-end applications like CISC architecture can be used with low-end applications like home
telecommunication, image processing, video processing, etc. automation, security system, etc.
It has fixed format instruction. It has variable format instruction.
The program written for RISC architecture needs to take more space in
Program written for CISC architecture tends to take less space in memory.
memory.
Example of RISC: ARM, PA-RISC, Power Architecture, Alpha, AVR, ARC Examples of CISC: VAX, Motorola 68000 family, System/360, AMD and the
and the SPARC. Intel x86 CPUs.
PIPELINING:
Pipelining is a computer architecture technique that allows multiple instructions to be
executed simultaneously, improving instruction throughput and overall performance.

Pipelining is an arrangement of the CPU’s hardware components to raise the CPU’s

general performance.
WORKING OF PIPELINE:

Break down instructions

The processor breaks down instructions into a series of sequential steps, or stages, that are
performed in parallel by different processor units.

Create a pipeline
The processor creates a pipeline, which is a logical structure of stages connected to each
other. Instructions enter the pipeline from one end and exit from the other.

Execute instructions
The processor executes instructions in an orderly, somewhat overlapped manner. Different
stages of instruction processing, such as fetching, decoding, executing, and writing back,
occur simultaneously across different instructions.

Add and remove instructions

New instructions are added to the pipeline, and completed instructions are removed after
processing.
Execution in a pipelined processor
In the pipeline, each segment consists of an input register that holds data and a
combinational circuit that performs operations. The output of the circuit is then
applied to the input register of the next segment of the pipeline. Here are the
steps in the process:
1. Instruction Fetch : Fetch instructions from memory.
2. Instruction Decode : Read the input register, and decode the instruction.
3. Instruction Execute : Execute the instruction.
4. Memory Access : Access an operand in data memory.
5. Write Back : Write the result of the operation into the input register of the next
segment.
Performance of a pipelined processor
Consider a ‘k’ segment pipeline with clock cycle time as ‘Tp’.
Let there be ‘n’ tasks to be completed in the pipelined processor. Now, the first instruction is going
to take ‘k’ cycles to come out of the pipeline but the other ‘n – 1’ instructions will take only ‘1’ cycle
each, i.e, a total of ‘n – 1’ cycles. So, time taken to execute ‘n’ instructions in a pipelined processor:

ETpipeline = k + n – 1 cycles
= (k + n – 1)Tp

In the same case, for a non-pipelined processor, the execution time of ‘n’ instructions will be:
ETnon-pipeline = n * k * Tp

Speedup (S) of the pipelined processor over the non-pipelined processor, when ‘n’ tasks are
executed on the same processor is:
S = Performance of non-pipelined processor /
Performance of pipelined processor

As the performance of a processor is inversely proportional to the execution time, we have,

S = ETnon-pipeline / ETpipeline
=> S = [n * k * Tp] / [(k + n – 1) * Tp]
S = [n * k] / [k + n – 1]
Advantages of Pipelining Disadvantages of Pipelining

1. Increased Throughput 1. Pipeline Hazards

2. Improved CPU Utilization 2. Increased Complexity
3. Better Performance for Repeated Tasks 3. Hardware Overhead
4. Scalability

Types of pipelines
There are two types of pipelines in computer processing.

Instruction pipeline
The instruction pipeline represents the stages in which an instruction is moved through the various segments of the
processor, starting from fetching and then buffering, decoding and executing. One segment reads instructions from the
memory, while, simultaneously, previous instructions are executed in other segments. Since these processes happen in an
overlapping manner, the throughput of the entire system increases. The pipeline's efficiency can be further increased by
dividing the instruction cycle into equal-duration segments.

Arithmetic pipeline
The arithmetic pipeline represents the parts of an arithmetic operation that can be broken down and overlapped as they are
performed. It can be used for arithmetic operations, such as floating-point operations, multiplication of fixed-point numbers,
etc. Registers are used to store any intermediate results that are then passed on to the next stage for further processing.