MC Interview Preparation

Protocols:

-> modes of comm ( simplex , half duplex, full duplex )

-> types of comm ( serial , parallel , synchornous and Asynchronous )

-> UART
-> SPI
-> I2C
-> CAN
d1 d2
UART
tx rx
->asynchronous
-> any duplex ( full duplex)
-> master - slave rx tx

frame format:

-> S - start why 2 ST ?

-> D0 - D7 - data bits - to avoid frame overrun
->P - parity
-> ST - stop bit ( 2 bits )

d1 d2 d3

tx rx rx MC -> laptop ( Mp)

rx tx tx
Mc -> Mc possible
18F -> 18F

D1 -> d2 -> d3

d1 d2
a
tx rx clcd

rx tx
SPI :

-> synchronous
-> full duplex
-> 1 master - multiple salve ( 1 M - 1S )

Interfacing lines SPI configuration

-> SCLK ->Normal method

->MISO -> Daisy chained method
->MOSI
-> nSS

I2C

-> snchrounous
-> half duplex
-> multiple master - multiple salve ( 1 M - 1 S )
update address bit ( 10 bits )

interfacing lines: salve ID (8 bit)

-> unique ID ( 7- bit ) unique ( 7 to 10 bits )
-> SCL -> R/W ( 1- bit )
-> SDA

M -> S
Master wait Ack ( 1 clock pulse )
1. M -> s ( unique ID & R/W )
2. M <- S (ack )

Data arbitration:
Mc 1 -> RTC ( 1111000) lowest unique ID
Mc 2 -> EEPROM(1010101)
overcome collision

lowest unique ID -> win the bus Mc 1 -> RTC ( 1111000) lowest data
Mc 2 -> RTC ( 1111000)

clock stretching:
int

MC1 -> MC2 ( S )

after ACK :
Slave - pull the data line to low ( hold the clock )

clock synchronization:

overcome collision:
waiting for long(high wait state)
same frequency different frequency

Mc1( faster) 1 0 1 0
wired AND 1 1

Mc2 ( slower) 0 0 1 1

0 0 1
CAN

-> asynchronous
-> half duplex
-> multiple master - multiple slave ( 1M - M S )

message based protocol -> Message ID -> lowest message ID high priority

frame format:
-> standard frame ( 11 - bit )
-> extended frame ( 29 - bit )

standard frame:

-> S - sart of frame(1 bit ) ( 0)

-> 11- bit ID
-> RTR - remote transmission reques( R/W ) ( read - 1 , write - 0 )
->IDE - identifier extension bit ( standard ( 0 )/ extended ( 1 ) )
-> r0 -reserved bit
-> DLC - data length count ( 4 - bit ) ( 0 - 8 bytes ) ( 0000 - 1000 )
-> data - ( 64 bit ) ( 0 - 8 bytes )
-> CRC - cyclic redundency check ( 16 bit ) ( CRC sequence ( 15 bit ) ,CRC delimiter ( 1 bit ) ( 1 ))
-> ACK - (2 bit ) (ack , ack delimiter ( 1 ))
-> EOf - end of frame ( 7 bit ) ( 1111111)

extended frame: ( 29 bit )

-> S - sart of frame(1 bit ) ( 0)

-> 11- bit ID
-> RTR - remote transmission reques( R/W ) ( read - 1 , write - 0 )
-> SRR - substitute remote request ( 1 )
->IDE - identifier extension bit ( standard ( 0 )/ extended ( 1 ) )
-> 18 - bit ID
-> RTR - remote transmission reques( R/W ) ( read - 1 , write - 0 )
-> r0 , r1 -reserved bit
-> DLC - data length count ( 4 - bit ) ( 0 - 8 bytes ) ( 0000 - 1000 )
-> data - ( 64 bit ) ( 0 - 8 bytes )
-> CRC - cyclic redundency check ( 16 bit ) ( CRC sequence ( 15 bit ) ,CRC delimiter ( 1 bit ) ( 1 ))
-> ACK - (2 bit ) (ack , ack delimiter ( 1 ))
-> EOf - end of frame ( 7 bit ) ( 1111111)

types of frame:

1. data frame Active state

2. remote frame passive state
3. overload frame bus off
4. error frame

error > 255 -> bus off

- reset
M( s) collision - lowest unique ID - 11 consecutive ( 128 )
M(E)
 In a 8-bit timer , tick inc for each 200 ns , How to calculate 1 sec delay?

count = T / (Q * R * P) time = 1 S
Q = 200 ns
count = 1 S / ( 200 ns * 256 * 1) R = 256 ticks
count = 1000000000 ns / ( 200 ns * 256 * 1) P=1
count = 19531.25
count => no.of overflow

count = 1000000000 ns / ( 200 ns * 250 * 1)

count = 20000

1sec => 20000 overflows

-> interface led to MC ( sourcing / sinking )

-> interface tactlie switches to MC ( pull -up / pull -down )
-> interface SSD to MC ( common cathode / common anode)
-> interface LCD to MC
- CLCD ( 16 pins ) -> 2 menthods to interface
->vss - 8-bit mode
-> vcc - 4 bit mode
-> vee (contrast ) ( pot )
-> RS ( register select bit ) ( data , instruction )
-> R/w ( read / write )
-> EN ( enable )
8 bit mode ( D0 - D 7 )
-> D0 - D 7 ( data bits )
-> led + clcd
-> led-

4 bit mode ( D4 - D 7 )
MC
clcd
16 pins

MC

12 pins

Busy flag -> CLCd execute ( data / instruction ) -> poll for D7
-> to check CLCD has completed the execution of data / instrcution
D7 == 0 // completed
PWM :

brightness of led :
period = ton + toff

led ( 5v )
1. 5V - glow (full ) => PWM
2. 2.5 V - glow ( half )
3. 0v - off

Methods to generate PWM :

-> bit banging ( high / low pulse , ton , toff )

-> timer ( , ton , toff ) ( isr - high / low pulse ) to avoid the delay (51.2 us )
-> bulit in block - ( period, duty cycle ) ( CCP1 ) 18F ( RC2)

Interrupt:

-> polling, disadvantage of polling. ( miss of event , bad responde time , bad power management )
->what is interrupt
-> types of interrupt
- hardware
- maskable
-external
-internal
- non maskable
-software
-> interrupt latency - delay
-> ways to handle the interrupt
- isr ( who will call isr ( MC ) , interrupt flag == 1 , who will set flag bit ( hardware))
- ivt
->what happens when an interrupt occurs
- pc ,satck

-> ADC , types , steps

-> Mc vs MP vs SOC
-> RISC vs CISC
-> architecture of MC ( ports , data bus , address bus , internal periphrals 18F ( page no 13 datasheet ))
-> general archituecture
->timer vs counter
->SPI vs I2C
-> programming timer ( 1sec, 1.5sec , 5 sec ) , led , switch , clcd
- how to refer the dasheet
- how to assign the bits