FACULTY OF ENGINEERING TECHNOLOGY DEPARTMENT OF

ELECTRICAL ENGINEERING TECHNOLOGY

PROJECT ASSIGNMENT
COURSE CODE BNF31802
COURSE COMPUTER ARCHITECTURE
GROUP 4
PROJECT TITLE IMPLEMENTING MIPS: THE
FETCH/EXECUTE CYCLE
GROUP MEMBERS 1. AHMAD SHAHEER KHUSAIRI
BIN MOHD AMBRIM
(CN230434)
2. ALYA KHAIRINA
NABIHAH BINTI AHMAD
JAWAHER
(CN230123)
3. AMEER HAKIM BIN MOHD
AZIZUL (CN230083)
4. MARSHEILLYN
NATASHA ANAK NAGA
(CN230318)
5. MUHAMMAD HAZIM BIN
SAMSUDIN (CN230384)
SECTION 1
SEMESTER/SESSION 1 SESI 2023/2024
LECTURE’S NAME ENCIK MOHD HAKIMI BIN ZOHARI

MARKS

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 GROUP MEMBERS
1. NAMA : AHMAD SHAHEER KHUSAIRI
BIN MOHD AMBRIM
NO. MATRIK : (CN230434)

2. NAMA : ALYA KHAIRINA NABIHAH BINTI

AHMAD JAWAHER
NO. MATRIK : (CN230123)

3. NAMA : AMEER HAKIM BIN MOHD

AZIZUL NO. MATRIK : (CN230083)

4. NAMA : MARSHEILLYN NATASHA ANAK NAGA

NO. MATRIK : (CN230318)

5. NAMA : MUHAMMAD HAZIM BIN SAMSUDIN

NO. MATRIK : (CN230384)

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 TABLE OF CONTENT
NO. CONTENTS PAGES
1. Group Members 2
2. 1.0 Introduction 4-5
3. 2.0 Create SR Latch 5-7
4. 3.0 Create Register 7-8
5. 4.0 Create ALU 9-10
6. 5.0 Create State Elements on The Datapath 11
7. 6.0 Create Data Memory Unit 12
8. 7.0 Create Sign Extension Unit 13-14
9. 8.0 Create Mux 14-15
10. 9.0 Execute the Complete MIPS Datapath 15-17
11. 10.0 Discussion 17-18
12. 11.0 Conclusion 18-20

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1.0 Introduction
The fetch/execute cycle, a key concept in computer architecture that dictates the sequence of
operations for instruction execution, is central to the MIPS (Microprocessor without
Interlocked Pipeline Stages) architecture's implementation. The cycle begins with the
Instruction Fetch (IF) step when the programme counter (PC) shows the memory address of
the next instruction. The instruction is retrieved from memory and stored in the instruction
register (IR) by the processor. The Instruction Decode (ID) step then decodes the instruction
to determine the operation and extracts pertinent information, creating control signals for the
following stages. The Execution (EX) step executes the instruction's actual execution,
executing arithmetic or logical operations on operands. Memory Access (MEM) is used when
instructions entail accessing memory and reading or writing data. The cycle is completed by
the Write Back (WB) stage, which writes the result back to the register file. Following that,
the programme counter is changed to refer to the next instruction, allowing the fetch/execute
cycle to continue. This repetitive process guarantees that programme instructions are
executed sequentially and serves as the foundation for effective MIPS-based processor
performance, emphasising the importance of understanding and optimising the fetch/execute
cycle in computer architecture and design.

The major goal of creating the MIPS (Microprocessor without Interlocked Pipeline Stages)
architecture and the related fetch/execute cycle is to execute programme instructions as
efficiently as possible. The fetch/execute cycle is a fundamental notion that describes the
processes taken by a processor to process instructions. The objective is to enable the
processor to effortlessly retrieve instructions from memory, decode them, execute the
prescribed operations, access memory if necessary, and write back the results by properly
implementing and optimising this cycle. The main goal is to guarantee that programme
instructions are executed smoothly and sequentially in order to maximise performance while
minimising processing time. The MIPS architecture strives to offer a dependable and high-
performance framework for processing instructions, catering to a wide range of computing
demands and applications, through the thorough design and execution of the fetch/execute
cycle. This goal emphasises the significance of understanding and developing the
fetch/execute cycle in the context of MIPS-based computer architecture and design.

Processor implementation includes a variety of approaches, each with its own set of features
that shape the trade-offs between simplicity, speed, and complexity. The single-cycle
technique conforms to the notion of executing each instruction within a single clock cycle.

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While this

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simplicity is desirable, it demands a longer clock cycle time to accommodate the slowest
instructions, potentially affecting overall performance. In contrast, the multicycle
implementation technique divides each instruction into several phases, each of which takes a
single clock cycle. This modular architecture allows for quicker clock cycles, but it
necessitates a more complex circuit design to control the sequencing of steps for various
instructions. The pipelined design, an extension of the multicycle notion, is a more advanced
approach. Pipelining divides the processor's execution pipeline into stages, each of which can
execute distinct instructions at the same time. This parallel processing capability considerably
improves performance by overlapping instruction execution. Pipelined processors can
achieve faster throughput and more effective resource utilisation despite the added
complexity in managing relationships between pipeline stages.

2.0 Create SR Latch

A Set-Reset (SR) latch is a basic digital electronic circuit that can store a single bit of
information. It has two inputs, S (Set) and R (Reset), and two outputs, Q and Q' (complement
of Q). The state of the latch is determined by the inputs and the previous state.

The SR Latch truth table is as below:

S R Q Q’
0 0 Q Q’
0 1 0 1
1 0 1 0
1 1 X X

The behavior of the SR latch can be described as follows:

 When S=0 and R=0, the latch maintains its previous state.
 When S=0 and R=1, the latch is reset, and Q becomes 0 while Q' becomes 1.
 When S=1 and R=0, the latch is set, and Q becomes 1 while Q' becomes 0.
 When S=1 and R=1, the behavior is undefined (X), and it should be avoided.
Example of an SR latch using NOR gates:

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the symbol 'SR' represents a NOR gate with inputs S and R. Connect the outputs of the NOR
gate to Q and Q'.

In this code, the always block is used with a ‘posedge clock’ (posedge clk) which means the
code inside the block will execute on the rising edge of the clock signal. The case statement is
used to select from a list of conditions. Each condition has a corresponding statement, and the
statement corresponding to the true condition is executed. In this code, the case statement is
used to determine the output of the ‘srff ’ module based on the value of the ‘sr’ input. Here,
2'b00, 2'b01, 2'b10, and 2'b11 are the different possible values of the ‘sr’ input. For each
value, a different statement is executed. For example, if ‘sr’ is 2'b00, then the q output is set
to the current value of q. If ‘sr’ is 2'b01, then the q output is set to 0, and then it is set to 1.
The reg type is used to declare a variable that can hold a value over multiple clock cycles. In
this code, the ‘srff ’ module has a reg type output named q. The value of q is determined by
the case statement inside the always block. The assign statement is used to assign a value to a
wire or reg type variable. In this code, the ‘qb’ output is assigned the value of q. This
Verilog code

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implements a sequential element (srff module) that can store the values 0, 1, or x (represented
by 1'bz) and provide those values on its output pins q and ‘qb’. The ‘sr’ input is used to
control which value is stored and output.

Below are the results for EPWave.

3.0 Create Register

Registers are essential to maintaining data and executing computations in the MIPS assembly
language. Now let's examine the main features of MIPS registers:

1. Standard-Use Registers:

 32 general-purpose registers make up MIPS, and each one is distinguished by a

number and a symbolic designation.
 These registers can be used for providing function parameters, storing data, and
carrying out arithmetic calculations.
 Zero is always present in the final register, known as register zero ($zero or $0).

2. Floating-Point Registers:

 32 floating-point registers, denoted as $f0 to $f31, are also provided by MIPS.

 Arithmetic operations using floating points are performed on these registers.

3. Rules for Using the Register:

 Although there is a theoretical limit to what can be done with any register, MIPS
programmers adhere to predetermined guidelines.
 Code that follows these recommendations interacts with other MIPS applications
consistently.

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  Compatibility is ensured, for instance, by using the proper registers for function
parameters, temporary values, and saved values.

The code demonstrates the basic concept of a MIPS processor register in Verilog. The
testbench drives the register with some test data and clock, and the register file updates its
memory based on the inputs.

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4.0 Create ALU

The ALU, or arithmetic logic unit, is a key part of the MIPS (microprocessor without
interlocked pipeline stages) and oversees carrying out arithmetic and logic operations. The
ALU of MIPS, a RISC (Reduced Instruction Set Computing) architecture, is made to carry
out a short, effective set of instructions.

Here are key features and aspects of the ALU in MIPS:

1. Operations:
 Basic arithmetic operations including addition, subtraction, multiplication, and
division are carried out by the ALU in MIPS.
 Logical operations such as AND, OR, XOR, and NOT are also handled by it.
2. Data Types:
 ALUs work with fixed-size data types; depending on the MIPS architecture, these are
usually 32- or 64-bit integers.
3. Registers:
 Typically, registers provide the operands for ALU operations. ALU operations are
performed on data stored in MIPS's general-purpose registers, which are a collection
of registers.
4. Instructions:
 The instruction set contains the encoded MIPS instructions that use the ALU. Certain
ALU operations, for instance, are mapped to the instructions add, sub, and, or, xor,
and nor.
5. Conditional Branching:
 Instructions for conditional branching frequently use the ALU. Branch instructions
use the outcome of an ALU comparison to decide whether to jump to a new section of
the program.

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5.0 Create State Elements on The Datapath

Two modules make up the Verilog program: Datapath in the testbench.sv file and
Datapath_tb in the design.sv file. A simple digital datapath with registers, an ALU, and
control logic is represented by the Datapath module. In addition to creating clock and reset
signals, the Datapath_tb module instantiates the Datapath module and functions as a
testbench. Data values and opcodes are set in the testbench's first block of code to simulate
the datapath's behavior for a particular scenario. The simulation is set up to use EPWave
commands to create a VCD file (dump.vcd), which makes waveform visualization easier for
analysis and debugging. The main goal is to use a modular and well-organized Verilog design
to model and test the functionality of a digital datapath.

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6.0 Create Data Memory Unit

A Data Memory Unit (DMU) design (design.sv) and corresponding testbench (testbench.sv)
make up the Verilog program. The DMU module has a 256-location, 8-bit memory array that
can be used for both read and write operations. The DMU is instantiated in the testbench,
clock and reset signals are generated, and a test scenario involving a write operation to a
given memory address and a read operation from the same address is carried out. In order to
guarantee a clean start during the reset condition, the design initializes the memory array.
Because of the program's simulation-oriented design, waveform visualization with EPWave
enables the observation of the DMU's behavior, including memory updates and retrievals.
The DMU functionality can be tested and verified in a controlled simulation environment
with the help of this modular approach.

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7.0 Create Sign Extension Unit

A Sign Extension Unit (SEU) is a component in computer architecture that is responsible for
extending the sign bit of a binary number when it undergoes a sign extension operation. Sign
extension is a process that occurs when a binary number representing a signed integer is
widened or extended to a larger number of bits.
In signed integer representation, the most significant bit (MSB) is often used as the sign bit,
where 0 represents a positive number and 1 represents a negative number. When you extend
the size of a signed integer, you need to preserve the sign of the original number by
replicating the sign bit into the additional bits.
The Sign Extension Unit takes care of this process by copying the sign bit (MSB) into the
additional bits of the extended number. This ensures that the signed integer retains its correct
value after the extension. The extension can be necessary, for example, when performing
arithmetic operations or data manipulation that requires a larger bit-width representation.
Coding for Sign Extension Unit:

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Result EPWave:

8.0 Create Mux

A multiplexer, often abbreviated as “Mux” is a digital electronic device that selects one of
several input signals and directs it to a single output. The selection of a particular input signal
is controlled by a set of binary inputs to the multiplexer, known as the select lines or control
lines.
Coding MUX (Verilog):

Result(EPWave):

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In Verilog, a 4:1 multiplexer (mux) is a digital circuit that selects one of four input
signals and directs it to the output based on a select signal. The notation "4:1" indicates
the number of data inputs to the multiplexer and the number of select inputs.

9.0 Execute the Complete MIPS Datapath

Coding (Verilog) And Result (EPwave) :

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Based on the graph, an EP waveform for the MIPS Verilog program is shown. There are few
procedures to execute the complete MIPS data path. A set of testbench Verilog coding is
produced which acts as the highest-level code, to fill in the inputs to our design code. Input in
SR Latch, Register, ALU, State Elements on the Datapath, Data Memory Unit,SignExtension
Unit and Mux are inserted to combine and run the program. In the beginning,code of
testbench is implemented. A Single-cycle is used for every instruction in the first
implementation. Every instruction begins on one up (or, down) clock edge and ends on the
next up (or, down) clock edge.

The process of adding two numbers can be represented using a timing diagram or waveform.
A waveform represents the changes in signal values over time and can be used to visualise
the operation of the Arithmetic Logic Unit (ALU) during an addition. Fetch phase: In this
phase, the CPU retrieves the instruction from memory and loads it into the instruction register
(IR).

Execute phase: In this phase, the CPU decodes the instruction, performs any necessary
operations, and writes the result back to memory or the register file. Single-cycle
implementation executes each instruction in a single clock cycle, making it simple to
implement but slower compared to pipelined implementation. Pipelined implementation
divides the instruction execution into multiple stages, executed in parallel, allowing multiple
instructions to be executed in a single clock cycle. This makes the pipelined implementation
faster than the single-cycle implementation but more complex to implement, as each stage
must be properly synchronised and managed. In summary, the single-cycle implementation is
slower but easier to implement, while the pipeline implementation is faster but more complex
to implement.

To create a datapath with a common register file and ALU, we must support two different
sources for the second ALU input, as well as two different sources for the data stored into the
register file. Thus, one multiplexor needs to be placed at the ALU input and another at the
data input to the register file, as shown in Figure 8.10.

We have discussed the individual instructions – arithmetic/logical, memory related and

branch. Now we can combine all the pieces to make a simple datapath for the MIPS
architecture by adding the datapath for instruction fetch, the datapath from R-type and
memory instructions and the datapath for branches. Figure below shows the datapath we
obtain by combining the separate pieces. The branch instruction uses the main ALU for
comparison of the register operands, so we must keep the adder shown earlier for computing
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the branch target address.

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An additional multiplexor is required to select either the sequentially following instruction
address, PC + 4, or the branch target address to be written into the PC.

10.0 Discussion

The execution of instructions in a computer follows a systematic process known as the

Fetch/Execute Cycle, a fundamental concept in computer architecture. In this essay, we will
delve into the implementation of the Fetch/Execute Cycle within the context of the MIPS
(Microprocessor without Interlocked Pipeline Stages) architectureThe Fetch/Execute Cycle
comprises several key stages, each crucial in the seamless execution of instructions. The
cycle begins with the Instruction Fetch (IF) stage. At this point, the program counter (PC)
holds the address of the next instruction to be executed. The content at this address is fetched
from memory, initiating the cycle.

Following the IF stage is the Instruction Decode (ID) phase. During this stage, the fetched
instruction is decoded to ascertain the operation it entails and identify the associated
operands. Additionally, if the instruction involves register operations, the necessary register
values are retrieved. This phase essentially sets the stage for the subsequent execution
steps.The heart of the cycle lies in the Execution (EX) phase. Here, the Arithmetic Logic Unit
(ALU) performs the operation specified by the instruction. Whether it involves arithmetic
calculations, logical operations, or data movement, the EX stage is where the actual
computation takes place. The ALU plays a central role in determining the outcome of the
instruction.

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Post-ALU operation, the cycle proceeds to the Memory Access (MEM) stage. This phase is
pertinent when instructions involve memory operations, such as loading or storing data.
Depending on the instruction, data is either read from or written to memory. This interaction
with memory is crucial for programs that require dynamic data manipulation. Subsequently,
the Write Back (WB) stage completes the cycle. The results obtained from the execution
phase are written back to the register file. This ensures that any changes to register values are
stored, maintaining the state of the processor. Moreover, the program counter is updated to
point to the address of the next instruction. This Update PC stage is influenced by the type of
instruction executed. For sequential instructions, the program counter is incremented.
However, for branch or jump instructions, the PC is set to the target address, redirecting the
program flow.

In conclusion, the implementation of the Fetch/Execute Cycle in the MIPS architecture

showcases the intricate coordination of hardware components. From fetching instructions to
executing them and updating the program counter, each stage plays a crucial role in the
smooth operation of a MIPS-based processor. This cycle serves as a foundational concept in
understanding how instructions are processed at the heart of computer systems, bridging the
gap between high-level programming and low-level hardware execution. To orchestrate these
stages effectively, a robust control unit is essential. The control unit generates signals that
coordinate the actions of various components in the datapath, ensuring a synchronized and
sequential execution of instructions.

11.0 Conclusion

In conclusion, the implementation of the Fetch/Execute Cycle within the MIPS architecture
represents a cornerstone in the realm of computer architecture, embodying the meticulous
dance between hardware components that gives life to the execution of instructions. This
fundamental process delineates the journey an instruction takes from its residence in memory
to its transformation into tangible outcomes. The orchestration begins with the Instruction
Fetch (IF) stage, where the program counter beckons the next instruction from memory. The
subsequent Instruction Decode (ID) phase unravels the instruction's intent and prepares the
groundwork for the ensuing stages. The crux of the matter unfolds during the Execution (EX)
phase, where the Arithmetic Logic Unit (ALU) takes center stage, performing the actual

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computational heavy lifting.

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The symbiotic relationship continues with the Memory Access (MEM) stage, where
instructions interacting with memory read or write data. This interaction is vital for
applications requiring dynamic data manipulation. The cycle then culminates in the Write
Back (WB) stage, where the fruits of computation are inscribed back into the register file,
maintaining the processor's state. The elegance of the Fetch/Execute Cycle lies in its cyclic
nature, perpetually looping through these stages. The Update PC stage ensures the program
counter is judiciously adjusted, facilitating the sequential flow of instructions or redirecting
program execution based on conditional branches and jumps. Integral to this process is the
role of the Control Unit, acting as the maestro orchestrating the symphony of hardware
components. Its ability to generate precise control signals based on the instruction's opcode
ensures that each stage plays its part in harmonious unison.

The MIPS Fetch/Execute Cycle not only demystifies the inner workings of a processor but
also embodies the symbiosis between high-level programming and low-level hardware
execution. It serves as a nexus where abstract algorithms find expression in the intricate dance
of transistors and datapaths. This marriage of abstraction layers is timeless, with the
Fetch/Execute Cycle standing as a testament to the enduring principles of computer
architecture. As technology evolves, this cycle remains a linchpin, influencing the design and
optimization of processors. Understanding its nuances not only unravels the intricacies of the
MIPS architecture but also provides a gateway to comprehending the broader panorama of
modern computing systems. In essence, the MIPS Fetch/Execute Cycle encapsulates the
essence of computational elegance, where every pulse of the cycle propels the relentless
march of instruction execution, defining the heartbeat of computing itself.

Making a single cycle or pipelined CPU depends on the design goals and trade-offs. Single
cycle CPUs are simple to design and understand, but they have low performance because they
can only execute one instruction at a time. On the other hand, pipelined CPUs can execute
multiple instructions in parallel, which increases performance. However, they are more
complex to design and require additional hardware to handle pipeline hazards. The choice
between a single cycle and pipelined CPU largely depends on the target application and the
desired performance. Hence, we had discovered some advantages of implementing a MIPS
processor.

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First , is education, it can be an excellent educational tool for students and researchers who
are interested in computer architecture. It provides a hands-on experience that helps to deepen
understanding of these subjects. Besides that, in the field of research, it allows them to test
their theories and evaluate the performance of their designs. Furthermore, MIPS is a Reduced
Instruction Set Computing (RISC) architecture, which is known for its simplicity, elegance,
and efficiency. Implementing a MIPS processor can result in a fast, low-power, and low-cost
system.