Computer Organization and Architecture

Code: SEng3022
Set by :
Molla K.
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 Chapter 6
Central Processing Unit

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 Central Processing Unit [CPU]
 The part of the computer that performs the bulk of data processing operations is called the Central processing unit.

 The CPU is made up of three major parts:

1. The register set stores intermediate data used during the execution of the instructions.

2. The Arithmetic and Logic unit (ALU) performs the required micro-operations for executing the instructions.

3. The control unit supervises the transfer of information among the registers and instructs the arithmetic and logic units

as to which operation to perform.

 The CPU performs a variety of functions dictated by the type of instructions that are incorporated in the computer.

 Computer architecture is sometimes defined as the computer structure and behavior as seen by the programmer that uses machine

language instructions.

 This includes the instruction formats, addressing modes, the instruction sets and the general organizations of the CPU registers.

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 General Register Organizations
 Memory locations are needed for storing pointers, counters, return addresses, temporary results and
partial product during multiplication.
 Memory locations for such applications is time consuming because memory access is the most time consuming
operation in a computer.
 It is more convenient and more efficient to store these intermediate values in processor register.
 A bus organization for 7-CPU registers.
 The output of each register is connected to multiplexers (MUX) to form the two buses A and B.
 The selection lines in each multiplexer select one register or the input data for the particular bus.
 The A and B busses form the inputs to ca common arithmetic logic unit.
 The operation selected in the ALU determines the arithmetic or Logic micro-operation that is to be
performed.
 The result of micro-operation is available for out put data and also goes in to the inputs of all the registers.

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 The register that receives the information from the output bus is selected by a decoder. Cont’d
 The decoder activates one of the register load inputs, thus providing a transfer path between the data in the output bus
and the inputs of the selected destination register.
 The control unit that operates the CPU bus system directs the information flow through the register and ALU by
selecting the various components in the system.
 E.g. to perform the operation R1  R2 + R3, the control must provide binary selection variables to the following
selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic addition A +B.
4. Decoder destination selector (SELD): to transfer the content of output bus in to R1.
 The four control selection variables are generated in the control unit and must be available at the beginning of a clock cycle.
 The data from the two source registers spreads through the gates in the multiplexers and the ALU, to the output
bus, and into the inputs of the destination register, all during the clock cycle interval.
 To achieve a fast response time, the ALU is constructed with high speed circuits.
 The busses are implemented with multiplexers or three state gates. 5
Cont’d

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 Stack Organization
 A useful feature that is included in the CPU of most computers is a stack or Last- In, First-out (LIFO) list.

o A stack is a storage device that stores information in such a manner that the item stored last is the first item retrieved.

o The stack in digital computers is essentially a memory unit with an address register that can count only (after an initial

value is loaded into it).

 The register that holds the address for the stack is called a Stack Pointer (SP) because its value always points at the top in

the stack.

 The two operations of a stack are the insertion and deletion of items.

o The operation of the insertion is called PUSH (or push-down) because it can be thought of as the result of pushing a

new item on top.

o The operation of deletion is called POP (or pop-up) because it can be thought as the result of removing one item so

that the stack pops up.

 Nothing is pushed or popped in a computer stack. In computers, these operations are simulated by

incrementing or decrementing the stack pointer register.

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 Memory Stack
 A stack can exist as separate unit can be implemented in RAM attached to a CPU.
 The implementation of a stack in the CPU is done by assigning a portion of memory to
stack operation and using a processor register as a stack pointer.
 Computer memory partitioned into three segments: Program, Data, and Stack.
 The PC points at the address of the next instruction in the program.
 The three registers are connected to a common address bus, and either one can
provide an address for memory.
 PC is used during the fetch phase to read an instruction.
 AR is used during the execute phase to read an operand.
 SP is used to push or POP items into or from the stack.
 Most computers do not provide hardware to check for stack overflow (full stack) or
underflow (empty stack).
 After a push operation, SP is compared with the upper limit register and after a pop
operation SP is compared with the lower limit register.
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 Instruction Formats
 An instruction format defines the layout of the bits of an instruction, in terms of its constituent fields.

 Instruction includes a set of operation codes and operands that manage with the operation codes.

 Instruction format supports the design of bits in an instruction.

 It contains fields including opcode, operands, and addressing mode.

 The instruction length is generally preserved in multiples of the character length, which is 8 bits.
 The function of allocating bits in the instruction can be interpreted by considering the following elements :

 Number of addressing modes

 Number of operands

 Number of CPU registers

 Number of register sets and Number of address lines

 Computers may have instruction of several lengths containing varying number of addresses.

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Instruction Formats

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 Cont’d
 The number of address field in the instruction format of a computer depends on the internal organization of its registers.
 Most computers fall into one of three types CPU organizations.
1. Single accumulator organization
2. General register organization
3. Stack organization
 In an accumulator-type organization, all operations are performed with an implied accumulator register. The
instruction format in this type of computer uses one address field.
 For example: the instruction that specifies an arithmetic addition is defined by an assembly language instruction as ADD
X, where X is the address of the operand.
 The ADD instruction in this case results in the operation AC  AC + M[X].
 AC is the accumulator register and M[X] symbolizes the memory word located at address X.
 The instruction format in a computer with a General Register Organization type needs three register address
fields.
 The instruction for an arithmetic addition may be written in an assembly language as ADD R1, R2, R3 to denote the
operation R1  R2 + R3. 11
 Cont’d
• The number of address field in the instruction can be reduced from three to two if the
destination register is the same as one of the source register.
• Thus the instruction ADD R1, R2 would denote the operation R1  R1 + R2.
• Only register addresses for R1 and R2 need be specified in this instruction.
 To illustrate the influence of the number of addresses on computer programs, we will evaluate
the arithmetic statement X = (A+B)  (C+D) using zero, one, two, or three address instructions.
• We will use symbols ADD, SUB, MUL and DIV for four arithmetic operations; and LOAD and
STORE for transfers to and from memory and AC register.

• We will the operand assume that the operands are in memory addresses A, B, C, and D, and the
result must be stored in memory at address X.
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 Three-address Instruction
 Computers with three-address instruction formats can use each address field to specify either a processor register
or a memory operand.

 The program in assembly language that evaluates X = (A+B)  (C+D) is shown below, together with comments that
explain the register transfer operation of each instruction.

o ADD R1, A, B R1  M[A] + M[B]

o ADD R2, C, D R2  M[C] + M[D]

o MUL X, R1, R2 M[X]  R1  R2

 It is assumed that the computer has two processor registers, R1 and R2.

 The symbol M[A] denotes the operand at memory address symbolized by A.

 The advantage of three-address format is that it results in short programs when evaluating arithmetic expressions.

 The disadvantage is that the binary-coded instructions require too many bits to specify three addresses.
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 Two- Address Register
 Two-address instructions are the most common in commercial computers.

 Here again each address field can specify either a processor register or a memory word.

 The program to evaluate X = (A+B)  (C+D) is shown as follows:

 MOV R1, A R1  M[A]

 ADD R1, B R1  R1 + R2
 MOV R2, C R2  M[C]
 ADD R2, D R2  R2 + M[D]
 MUL R1, R2 R1  R1  R2
 MOV X, R1 M[X]  R1
 The MOV instruction moves or transfers the operands to and from memory and processor registers.

 The first symbol listed in an instruction is assumed to be both a source and destination where the result of the
operation is transferred.
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 One-Address Instruction
 One-address instructions use an implied Accumulator (AC) Register for all data manipulations.

 For multiplication and division there is a need for a second register.

 However, here we will neglect the second register and assume that the AC contains the result of all operations. The
program to evaluate X = (A+B)  (C+D) is:
 LOAD A AC  M[A]
 ADD B AC  AC + M[B]
 STORE T M[T]  AC
 LOAD C AC  M[C]
 ADD D AC  AC + M[D]
 MUL T AC  AC  M[T]
 STORE X M[X]  AC
• All operations are done between the AC register and a memory operand.
• T is the address of a temporary memory location required for storing the intermediate result.
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 Zero-Address Instruction
 A stack-organized computer does not use an address field for instructions ADD and MUL.

 The PUSH and POP instructions, however, need an address field to specify the operand that communicates
with the stack.

 The following program shows how X = (A+B)  (C+D) will be written for a stack-organized computer (TOS
stands for top-of-stack)

 PUSH A TOS  A
 PUSH B TOS  B
 ADD TOS  (A + B)
 PUSH C TOS  C
 PUSH D TOS  D
 ADD TOS  (C + D)
 MUL TOS  (C + D)  (A + B)
 POP X M[X]  TOS 16
 Addressing Modes
 An addressing mode refers to how you are addressing a given memory location.

 There are five different ways or five addressing modes to execute this instruction which are as
follows:

 Immediate addressing mode

 Direct addressing mode

 Register direct addressing mode

 Register indirect addressing mode

 Indexed addressing mode

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 Addressing Modes
 Immediate Addressing Mode

 In this mode, the operand is specified in the instruction itself.

 In other words, an immediate-mode instruction has an operand field instead of an address

field.

 The operand field includes the actual operand to be used in combination with the
operation determined in the instruction.

 Immediate-mode instructions are beneficial for initializing registers to a constant value.

Algorithm: operand = A E.g. Mov ax, 1231h

MOV DL, 08H
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 Addressing Modes
 Register Direct Mode − In this mode, the operands are in registers that reside within the CPU.
•The specific register is selected from a register field in the instruction.

Algorithm: EA = R
Example: MOV AX, BX , MOV BL, AL

 Register Indirect Mode − In this mode, the instruction defines a register in the CPU whose contents provide the
address of the operand in memory.
 A reference to the register is then equivalent to specifying a memory address.
 The advantage of a register indirect mode instruction is that the address field of the instruction uses fewer bits to
select a register than would have been required to specify a memory address directly.
Algorithm: EA = [R ] e.g MOV CX, [BX]

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 Addressing Modes
 Direct Memory Address Mode: In this mode, the effective address is equal to the address part of the instruction.

 The operand resides in memory and its address is given directly by the address field of the instruction.

Algorithm: EA =A E.g. MOV BX, [1354H] . MOV BL, [04H]

 Indirect Address Mode: In this mode, the address field of the instruction gives the address where the
effective address is stored in memory.

 Control fetches the instruction from memory and uses its address part to access memory again to read the
effective address. Algorithm: EA =(A) E.G. MOV AX, [BX + 08H]

 Indexed Addressing Mode: In this mode, the content of an index register is added to the address part of the
instruction to obtain the effective address.

 The index register is a special CPU register that contains an index value. The address field of the instruction
defines the beginning address of a data array in memory. E.G MOV CX, [SI + 0A2H], MOV DX, [BX + SI + 0AH]
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 Data Transfer and Manipulation
 Computers provide an extensive set of instruction to give the user the flexibility to carry out various
computational tasks.
 The instruction set of different computers differ from each other mostly in the way the operands are
determined from the address and mode fields.
 The actual operations available in the instruction set are not very different from one computer to another.
 It so happens that the binary code assignments in the operation code field is different in different
computers, even for the same operation.
 It may also happen that the symbolic name given to instructions in the assembly language notation is
different in different computers, even for the same instruction.
 Most computer instructions can be classified in to three categories.
1. Data transfer instruction
2. Data manipulation instruction
3. Program control instruction 21
 1. Data Transfer Instructions
 It moves data from one place in the computer to another without changing the data content.

 The most common transfers are between memory and processor registers, between processor registers and
input or output, and between the processor registers themselves.

 Typical Instructions are,

 Load (LD) - Transfer from memory to a processor register, usually an accumulator.

 Store (ST) - Transfer from a processor register into memory.

 Move (MOV) - Transfer from one register to another.

 Exchange (XCH) - Swaps information between two registers or a register and a memory word.

 Input (IN), Output (OUT) - Transfer data among processor registers and input or output terminals.

 Push (PUSH), Pop(POP) - Transfer data between processor registers and a memory stack.
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 2. Data Manipulation Instructions
 Data manipulation instructions perform operations on data and provide the computational capabilities for the computer.
Divided into three basic types:
A. Arithmetic instructions.
B. Logical and bit manipulation instructions.
C. Shift instructions.
1. Arithmetic Instructions
 Increment (INC) : adds 1 to the value stored in a register or memory word.
Decrement (DEC) : subtracts 1 from a value stored in a register or memory word.
Add (ADD) : Addition.
 Subtract (SUB) : Subtraction.
Multiply (MUL) : Multiplication
Add with carry (ADDC) : Performs the addition on two operands plus the value of the carry from the previous computation.
Subtract with borrow (SUBB) : Subtracts two words and a borrow which may have resulted from a previous subtract
operation.
Negate (NEG) : Forms the 2’s complement of a number.
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 2. Logical and Bit Manipulation Instructions

 Clear (CLR)
 Logical instructions perform binary operations
 Complement (COM)
on strings of bits stored in registers.
 AND (AND)
 They are useful for manipulating individual bits  OR (OR)
or a group of bits that represent binary coded  Exclusive-OR (XOR)

information.  Clear carry (CLRC)

 Set carry (SETC)
 The logical instructions consider each bit of the
 Complement carry (COMC)
operands separately and treat it as a Boolean
 Enable interrupt (EI)
variable.
 Disable interrupt (DI)

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 Program Control Instructions
 Program control instructions specify conditions for altering the content of the program
counter.

 Provides decision making capabilities.

 Branch (BR) : BR ADR, branch the program to Address ADR. (PC←ADR)

 Jump (JMP)

 Skip (SKP) : Skip instruction(PC←PC + 1) if some condition is met.

 Call (CALL) : Used with subroutines

 Compare (CMP) : Compare by subtraction.

 Test (by ANDing) TST : AND instruction without storing result.

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 Instruction Sets
• Generally, there are two types of instruction set used in computers:
1. Reduced Instruction set Computer (RISC):
 A number of computer designers recommended that computers use fewer instructions with simple constructs so that
they can be executed much faster within the CPU without having to use memory as often called a Reduced Instruction
Set Computer.
 The concept of RISC involves an attempt to reduce execution time by simplifying the instruction set of computers.
2. Complex Instruction Set Computer(CISC):
 CISC is a computer where a single instruction can perform numerous low-level operations like a load from memory
and a store from memory, etc.
 The CISC attempts to minimize the number of instructions per program but at the cost of an increase in the number of
cycles per instruction.
 The design of an instruction set for a computer must take into consideration not only machine language constructs but
also the requirements imposed on the use of high level programming languages.
 The goal of CISC is to attempt to provide a single machine instruction for each statement that is written in a high level
language.
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 Characteristics of RISC
• The characteristics of RISC are as follows:
 Relatively few instructions.

 Relatively few addressing modes.

 Memory access limited to load and store instructions.

 All operations done within the register of the CPU.

 Single-cycle instruction execution.

 Fixed length, easily decoded instruction format.

 Hardwired rather than micro programmed control.

 A relatively large number of registers in the processor

 Use overlapped register windows to speed up procedure call and return

 Efficient instruction pipeline

 Compiler support for efficient transmission high-level language programs into machine language programs
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 Characteristics of CISC
• The characteristics of CISC are as follows:
 A large number of instructions typically from 100 to 250 instructions.
 Some instructions that perform specialized tasks and are used infrequently.
 A large variety of addressing modes- typically from 5 to 20 different modes.
 Variable length instruction formats.
 Instructions that manipulate operands in memory.
• Example: For performing an ADD operation, CISC will execute a single ADD command which will
execute all the required load and store operations.
 RISC will execute each operation for loading data from memory, adding values and storing data back to
memory using different low-level instructions.

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