Ch8a Myppt
Ch8a Myppt
Code Generation
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Flow Graphs
• A flow graph is a graphical depiction of a
sequence of instructions with control flow
edges
• A flow graph can be defined at the
intermediate code level or target code level
MOV 1,R0 MOV 0,R0
MOV n,R1 MOV n,R1
JMP L2 JMP L2
L1: MUL 2,R0 L1: MUL 2,R0
SUB 1,R1 SUB 1,R1
L2: JMPNZ R1,L1 L2: JMPNZ R1,L1
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Basic Blocks
• A basic block is a sequence of instructions
– Control enters through the first instruction
– Control leaves the block without branching,
except possibly at the last instruction
MOV 1,R0
MOV 1,R0 MOV n,R1
MOV n,R1 JMP L2
JMP L2
L1: MUL 2,R0 L1: MUL 2,R0
SUB 1,R1 SUB 1,R1
L2: JMPNZ R1,L1
L2: JMPNZ R1,L1
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MOV 1,R0
MOV n,R1
JMP L2
Loops
• A loop is a collection of basic blocks, such
that
– All blocks in the collection are strongly
connected
– The collection has a unique entry, and the only
way to reach a block in the loop is through the
entry
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Loops (Example)
B1: MOV 1,R0 Strongly connected
MOV n,R1
JMP L2
components:
a := c*a a := c*a
b := 0 b := 0
Blocks are equivalent, assuming t1 and t2 are dead: no longer used (no longer live)
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Common-Subexpression
Elimination
• Remove redundant computations
a := b + c a := b + c
b := a - d b := a - d
c := b + c c := b + c
d := a - d d := b
t1 := b * c
t1 := b * c
t2 := a - t1
t2 := a - t1
t3 := b * c
t4 := t2 + t1
t4 := t2 + t3
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b := a + 1 b := a + 1
a := b + c …
…
Assuming a is dead (not used)
if true goto L2
b := x + y
Remove unreachable code
…
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t1 := b + c t1 := b + c
t2 := a - t1 t2 := a - t1
t1 := t1 * d t3 := t1 * d
d := t2 + t1 d := t2 + t3
Normal-form block
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Interchange of Statements
• Independent statements can be reordered
t1 := b + c t1 := b + c
t2 := a - t1 t3 := t1 * d
t3 := t1 * d t2 := a - t1
d := t2 + t3 d := t2 + t3
Algebraic Transformations
• Change arithmetic operations to transform
blocks to algebraic equivalent forms
t1 := a - a t1 := 0
t2 := b + t1 t2 := b
t3 := 2 * t2 t3 := t2 << 1
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A Code Generator
• Generates target code for a sequence of
three-address statements using next-use
information
• Uses getreg to assign registers to variables
• For instruction x := y op z
getreg(y, z) returns a location (register) for x
• Results are kept in registers as long as possible:
– Result is needed in another computation
– Register is kept up to a procedure call or end of block
• Check if operands of three-address code are
available in registers
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Peephole Optimization
• Examines a short sequence of target instructions in
a window (peephole) and replaces the instructions
by a faster and/or shorter sequence when possible
• Applied to intermediate code or target code
• Typical optimizations:
– Redundant instruction elimination
– Flow-of-control optimizations
– Algebraic simplifications
– Use of machine idioms
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b := x + y b := x + y
… …
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b := x + y b := x + y
… …
…
goto L1
L1:
… …
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