Unit 1

MPU(Micro Processor Unit) Organization

Reference Books
1.Douglas Hall, “Micro-Processors and Interfacing-Programming &
Hardware”, TMH, 2nd Edition, 2002.

2. Barry B. Brey, “The Intel Micro-processors, Architecture, Programming and Interfacing”,

Pearson Education, 6th Edition, 2008.

3. Kenneth J. Ayala; “The 8051 Microcontroller Architecture, Programming &

Applications”; Thomson Learning; 2nd Edition, 2004.

4. Muhammad A Mazidi;”The 8051 Microcontroller and Embedded Systems”;

Pearson Education; 2nd Edition, 2009.

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 Unit 1: Syllabus
CISC & RISC Design Philosophy, Harvard & Von-Neuman
Architectures, Microprocessor & Microcontroller, Intel’s 8086
architecture, Pin groups, Functioning, Segmentation,
Maximum Mode, Minimum Mode, Address generation, Stack,
Interrupts.

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 Instruction Set Architectures(ISA)
 An instruction set, or instruction set architecture
(ISA), is the part of the processor architecture related to
programming.
 All processors are supported by instruction set /instructions
(Assembly instructions) which are dependent on organization
of different components in PLU.
 Depending upon the way of supporting different
instructions, the ISA is divided into
-Reduced Instruction Set Computer(RISC)
-Complex Instruction Set Computer(CISC)
 Other types of ISA
- Very Long Instruction Word(VLIW), MIPS, etc….
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 CISC & RISC Design Philosophy: CISC Vs RISC
CISC RISC
 More number of  Lesser no. of instructions.
instructions
 Instructions are Easier to
 Instructions are complex to
understand.
understand.
• Hardware support for many • Software support for many
instructions (More silicon instructions/operations.
Usage) (Less silicon usage)
A programmer can achieve the Programmer needs to write more
desired functionality with a single code to execute a task since the
instruction which in turn provides instructions are simpler ones
the effect of using more simpler
single instructions in RISC
• Clock cycles per  Clock cycles per
instruction(CPI)
MGR,ECE,RVCE is more. instruction(CPI) is less.
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 CISC & RISC Design Philosophy: CISC Vs RISC
CISC RISC
 Code density is more.  Code density is less.
 Less number of registers.  More number of registers.
 Memory to memory  No memory to memory
operations are supported. operations are supported.
Load & store operations in a Load & store operations not in
instruction a instruction ( So called as
load-store architecture)

• More number of addressing • Less number of addressing

modes. modes.
• Variable length instructions. • Fixed length instructions.
• Design of Pipelining is • Design of Pipelining is
Complex. easier.
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 CISC & RISC Design Philosophy: CISC Vs RISC
CISC RISC
 Non Orthogonal Instruction  Orthogonal Instruction
Set Set
All instructions are not allowed Allows each instruction to
to operate on any register and operate on any register and use
use any addressing mode. It is any addressing mode.
instruction specific. • Examples: ARM, MSP 430, PIC
• Examples: 8086 POWERPC

NOTE: The fact is, the designers are not worried about the
architecture(CISC/RISC). So, the features from both the architectures are
mixed up to increase the performance(Increase speed & reduce memory
consumption).
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 Questions
 What is code density?
 What is orthogonal instruction set?
 Why CPI is less in RISC architecture?
 Which is the preferable control unit to support complex
operations ?
 What is the advantage/disadvantage of fixed length
instructions?
 What is hardware support for an instructions?

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Microprocessor (MP) & Microcontroller (MC)
MP MC
 A silicon chip representing a • A microcontroller is a highly
Central Processing Unit (CPU), integrated chip that contains a
which is capable of performing CPU, RAM, On Chip
arithmetic as well as logical ROM/FLASH memory for
operations according to a pre- program storage, Timer and
defined set of Instructions Interrupt control units and
dedicated I/O ports.
 It is a dependent unit. It  It is a self contained unit and
requires the combination of it doesn’t require external
other chips like Timers, Interrupt Controller, Timer,
Program and data memory UART etc. for its functioning
chips, Interrupt controllers
etc. for functioning
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Microprocessor (MP) & Microcontroller (MC)
MP MC
 Doesn’t contain a built in I/O  Most of the controllers contain
port. The I/O Port functionality multiple built-in I/O ports
needs to be implemented with which can be operated as a
the help of external single 8 or 16 or 32 bit Port or
Programmable Peripheral as individual port pins
Interface Chips like 8255.
 Targeted for embedded
 Targeted for high end market
where performance is market where performance is
important not so critical (At present
 Most of the time general this demarcation is invalid)
purpose in design and  Mostly application oriented
operation or domain specific
 Limited power saving options  Includes lot of power saving
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compared to
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microcontrollers features
 Microprocessor (MP) & Microcontroller (MC)

Data Pgm Data Pgm

Memory Memory Memory Memory

 E.g:8086  E.g:8051
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Von Neumann & Harvard Architecture
 This classification is based on processor architecture design to
support memory.
 Address Space:
- No. of locations a processor/controller can address.
E.g: 8086: Address bus=20 bits, so address space is 1 Mb
(00000H-FFFFFH)
8051: Address bus=16 bits, so address space is 64 Kb
(0000h-FFFFh)

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 Von Neumann/Princeton Architecture
 In this architecture, address space is shared between program
memory & data memory.
 Common memory for program & data.
 E.g: 8086
-Total Address space is 1Mb
- The address space is segmented(shared) in to code
segment(Program memory) and data segment (data memory).
 Single shared bus(Address, data & control: System bus) for Instruction
and Data fetching. Pgm /data
memory

 The speed of execution is less because sharing of bus.

 TheMGR,ECE,RVCE
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complexity of design of processor is less because single bus.
 Harvard Architecture
 In this architecture, address space is not shared between program
memory & data memory.
 Separate memory for program & data.
 E.g:8051
- Total address space for program memory is 64Kb & for
data memory is 64Kb.
- Program memory & data memory locations are separate.
 Separate buses for Instruction and Data fetching.

 The speed of execution is more because separate buses.

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 The processor design is complex.
 Von Neumann & Harvard Architecture
 What is the meaning of common memory for program & data?
- Is it possible to use RAM as program memory(Basic need:
Permanent storage)?
- Is it possible to use ROM as data memory?(Basic need:
Read/write during program execution)

Case 1: Microcontrollers
-The flash (EEPROM) is used as program memory &
RAM(SRAM) is used as data memory.(Integrated into chip)
- Usually based on Harvard architecture.

So, the question is invalid!

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 Von Neumann & Harvard Architecture
Case 2: Microprocessor
-The block diagram shows 8086 MPU connected to memory.

 Separate memory! Why it is called as Von Neumann?

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 Von Neumann & Harvard Architecture
Case 3: Modern Microprocessors/ Computers
- The block diagram shows MPU connected to memory

 Common memory! Architecture is Von Neumann

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 Von Neumann & Harvard Architecture
Case 4: Modern Microprocessors/ Computers

 Architecture is Von Neumann.

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 Von Neumann & Harvard Architecture
Case 5: Modern Microprocessors/ Computers
- The block diagram shows MPU connected to memory

 What is this architecture called?

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 Von Neumann/Princeton Architecture

Note: The separate bus for program memory & data memory is
applicable only to on chip memory.

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 Questions
 What is address space?
 Why execution is faster in a processor based on Harvard
architecture?
 Differentiate between general computer system & an
embedded system.
 Why address bus is unidirectional?
 What is cache?

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8086 Features
 16 bit micro processor (ALU is designed to work
with 16 bit data).
 16 bit data bus.
 20 bit address bus, so it can access 220 or
1048576(1 Mb) memory locations of byte wide
each. Therefore, a sixteen bit words are stored in
two consecutive memory locations (Von
Neumann).
 Support memory segmentation

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  The 8086 has multiplexed address and data bus
which reduces number of pins required.
 The 8086 requires clock with a 33% duty
cycle.(no on chip oscillator, requires clock
generator 8284)
 clock speed: 5 MHz- 8086
8 MHz - 8086-2
10 MHz – 8086-1

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  The 8086 can generate 16 bit I/O addresses.
 The 8086 provides fourteen 16 bit registers (SFR+
GPR)
 Micro-programmed control unit
 16-Bit flag register (Control + Status)
 6 bytes instruction queue(Pipelining)
 Interrupts
- NMI & INTR (Hardware)
- INT instruction(Software)

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 Two modes of operation:
Minimum Mode: CPU is connected to memory and I/O
devices.
Maximum Mode: CPU is connected to another processor
(Multiprocessor Mode) in addition to
memory and I/O devices.

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 8086 Internal Configuration

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Architecture of 8086
 The 8086 CPU is divided into independent functional
parts:
-Bus Interface Unit(BIU)
- Execution Unit(EU)
 BIU sends out addresses, fetches instructions from
memory, reads data from ports and memory and writes
data to ports and memory

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 Architecture of 8086….

 The EU tells the BIU where to fetch instructions and

data from, decodes instructions and executes
instructions.
 Dividing work between these two units, speeds up the
execution.

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 8086 Internal Diagram

Bus Interface Unit

(B I U)

Execution Unit (EU)

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 BUS INTERFACE UNIT(BIU)
Instruction Queue
 While the EU decoding an instruction or executing an instruction
which does not require use of the system buses, the BIU fetches up to
six bytes for the following instructions and stores in FIFO queue.
 The size of queue is 6 bytes.
 When EU is ready for next instruction execution, it simply reads
instruction byte(s) from the queue.
 Fetching next instruction while the current instruction executes is
called pipelining.

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 BIU-Instruction Queue
 This speeds up program execution(Except for JMP and CALL
instruction).

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Segment Registers
BIU
 The BIU sends out the 20-bit address, so it can address any location of
1048576 bytes(1 Mb).
 Memory Segmentation
-At any time 8086 works with only four segments of 64Kb
with in 1 Mb.
- The 4 segment registers of 16 bits wide in the BIU are used to
hold upper 16 bits of the starting address of 4 segments.

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 BIU
 Four segment registers:
-Code segment (CS) register for code segment:
Used for program storage(Instruction codes)
- Data Segment (DS) register for data segment:
Used for data storage
- Extra Segment (ES)register for extra segment:
Used for data storage
- Stack Segment (SS) register for stack segment:
Used to store address & data while subprogram executes

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Memory Segmentation

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Generation of 20 bit address
 The index registers or pointer registers contain displacement
or offset, used to point to a particular location is called offset or
effective address.
 Index registers/ Pointer registers
IP (Instruction Pointer) for CS
SI(source Index) for DS(default)
16
DI(Destination Index) for ES (with string instruction)
bit
SP(Stack Pointer) for SS
BX register for DS(default), CS,ES,SS(Alternate)
BP(Base Pointer) for SS(default), CS,ES,DS(Alternate)
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 20 bit address….
 The address put on address bus called as physical address must contain
20 bits.
 The physical address is calculated as follows.

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Questions
1. If CS=1000H, IP= 1234H what is effective address & physical
address?
2. What is the operation of following instruction? MOV AL,[BP]
3. What is the operation of following instruction? MOV CX, [BX]
4. What is the operation of following instruction? MOV
DS:[BP],AL
5. What is synchronous & Asynchronous interrupt?
6. If BX=0adech ,DS= 2000h and SI= 55h, find the effective
address and physical address of the instruction MOV
AL,[BX][SI].
7. What is the IO capability of 8086 in IO mapped IO method?

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 Advantages of memory segmentation
1. Allow the memory capacity of 1 Mb even though
index registers & pointer registers used to access
memory are 16 bits wide.
2. Allow the instruction, data or stack portion of a
program to be more than 64K bytes long using
more than one code, data and stack segment.
2. Facilitate the use of separate memory areas for a
program, its data and the stack.

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 Execution Unit(EU)
 The EU tells the BIU where to fetch instructions and data from,
decodes instructions & executes instructions.
 It contains,
- Control Circuitry
- Instruction decoder
- ALU
-Flags
- General Purpose registers
-Pointers & index registers

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 The STATUS register(Flag register)
 Indication/Status Bits
 only for status: Bits are set or cleared based on the result
of any Arithmetic or Logic operation.

 Control Bits
 Used for control: Bits may be affected indirectly (by the execution o
an instruction) or directly by an instruction designed to access the statu
word

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

x x x x OF DF IF TF SF ZF x AF x PF x CF

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 The STATUS register(Flag register)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

x x x x OF DF IF TF SF ZF x AF x PF x CF

 Carry flag(CF): This flag is set if there is carry out of MSB in

addition. It is set when borrow is needed in
Subtraction.
 Parity flag(PF): It is set to 1 when result of byte operation or
lower byte of the word operation contain
even number of ones.

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  Auxiliary Carry Flag(AF): This is set when there is an
carry out from lower nibble to higher nibble (D3 to
D4).(used in BCD operations)
 Zero Flag(ZF): This flag is set if the result of ALU
operation is zero.
 Sign Flag(SF): After ALU operation, if the MSB of the
result is 1, sign bit is set.
 Overflow Flag(OF): If result is out of range.
This bit is set if there is carry into MSB and no carry out of
it or vice versa for addition.
Subtraction: set to 1 when MSB needs borrow & no borrow
from the MSB.
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 Question
 Give the contents of flag register after execution of following
addition.
65D1H+2359H = 892A H
0110 0101 1101 0001

0010 0011 0101 1001

1000 1001 0010 1010

SF=1,ZF=0,PF=0, CF=0,AF=0,OF=0

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 Control Bits
 Trap Flag (TF): Trap flag is used for single stepping.
A system will stop after it executes each instruction
and wait for further direction from programmer.
 Interrupt Flag(IF): If set, maskable interrupts are enabled.
 Direction flag(DF): It used to auto increment/decrement
pointers (DI & SI) made to point to string.
DF=0 =>Increment
DF=1=>Decrement

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 8086 Pin diagram

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 8086 Pin Description
 The 8086 pins can be categorized into 3 groups
 Pins having common functions in minimum and maximum
modes.
 Pins having special functions in minimum mode.
 Pins having special functions in maximum mode.

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 Common Pins
 GND: Ground(2 pins)
 Vcc : Supply voltage of 5 V with ± 10%
 AD15-AD0 : Bidirectional in nature, during first part of
the bus cycle, processor outputs address and during later
part of the bus cycle, processor reads (input) or write
(output) data.
 NMI: Non Maskable Interrupt request pin. It is positive
edge triggered.
 INTR : Maskable interrupt request. If INTR is held active
high when IF=1, 8086 enters into interrupt acknowledge
cycle(INTA becomes active) after the current instruction
execution completion.
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  CLK : Input Clock frequency
The 8284 clock generator is used to obtain the clock.
- The crystal is connected to 8284 chip, which divides
crystal frequency by three internally.
- Maximum CPU operation
8086 :5 MHz( Crystal frequency:15 MHz)
8086-2 :8 MHz(Crystal Frequency:24 MHz)
8086-1 : 10 MHz (Crystal Frequency: 30 MHz)
 RESET: Active high signal, when maintained for atleast 4 clock
cycle , reset is initiated.
- Reset clears PSW, IP,DS, SS,ES and instruction
queue
- The CS register set to FFFFh
- Processing begins at FFFF0H
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 Ready : The 8086 bus cycle consists of 4 clock cycles (T states).

- The ready pin is checked at the end of T2 of every bus cycle.

- If ready pin is low, it inserts wait state between T2 and T3.
- If the READY pin is still low after wait state, one more wait state
is inserted.
- The 8086 enters to T3 state only when READY pin high at the end of wait
state.
- Used to match the speed of slower peripherals.
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 Tw T3
 One wait state

 2 wait states Tw T3

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  Test: A wait instruction causes CPU to idle (except for
interrupt processing) until low signal applied to this pin.
 RD : whenever this signal is low it indicates memory or I/O
read operation is to be performed.
 MN/MX : When tied to Vcc, 8086 is in minimum mode, when
grounded 8086 will be in maximum mode.

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  BHE /S7: Byte High Enable, Active low signal
- Used to enable most significant data bus bits (D15-
D8) during read or write operation.
- Generated during first part of machine cycle.

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  BHE & A0 pin together indicate various data transfer as
indicated below.
Operation A0 Data Pins used
BHE
Write/Read a word 0 0 AD15-AD0
at Even Address
Write/Read a byte 1 0 AD7-AD0
at even address
Write/ Read a byte 0 1 AD15-AD0
at an odd address
Write/Read a word 0 1 AD15-AD0
at odd Address Read least
significant byte
1 0 AD7-AD0
Read Most
significant byte

55  S7MGRCarries no meaning, always high.

  A19/S6-A16/S3 : During First part of the bus cycle(T1) the
most significant 4 bits of the address.
- Later part of the bus cycle status is output.
-S6 always zero, carries no meaning
- S5 gives the current setting of IF (interrupt Flag)
- S4 & S3 show which segment is accessed during the
current bus cycle.

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 Minimum Mode pins
 INTA: Acknowledgement given by CPU to interrupt
request.
 ALE(Address Latch Enable):This shows that the 8086
address/data bus contain address information.
- The address can be memory address or I/O port
address.
 DT/R: Data Transmit/Receive signal shows that
microprocessor data bus is transmitting(DT/R=1) or
receiving(DT/R=0).
- This signal is used to control direction of data bus
buffers.
- This is output signal issued by microprocessor.
 WR: whenever this signal is low it indicates memory or
I/O write operation is to be performed.
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  DEN: The data bus enable is an output signal given by µP,
during later part of the cycle to inform the transceivers that
CPU is ready to send or receive data.
 M/IO : This pin selects memory or I/O
 HOLD, HLDA
when HOLD line goes High – it indicates the processor that
another master(DMA: Direct Memory access) is requesting
the bus access.
In-turn the processor
 issues acknowledge on HLDA pin, in the middle of the next
clock cycle after completing the current bus cycle.
 Processor enters into hold state until hold release signal.
58  Asynchronous input
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 Maximum mode pins
 S2, S1, S0
 Indicates the type of operation carried out by the processor.
 Becomes active in the previous T4 and remains till T1,T2 of current cycle.
 Return to 'Passive State' during T3 – so that they may again become active for
the next cycle during T4.
 These output signals are used by 8288 bus controller to generate all memory
& IO access control signals
S2’ S1’ S0’ Indication
0 0 0 Interrupt Acknowledgement
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive (Inactive)
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  LOCK
 Prevents the other system bus master from gaining the
system bus.
 Activated by the 'LOCK' prefix instruction and remains
active until the completion of the next instruction.
 QS1, QS0
 Queue status – informs the status of the code-pre fetch queue
QS1 QS0 Indication
0 0 No operation
0 1 1st byte of opcode from the queue
1 0 Empty queue
1 1 Subsequent byte of the opcode

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  RQ/GT0, RQ/GT1 (Request/grant)
used by other local bus masters – to force the processor
to release the local bus at the end of the processor's
current bus cycle.
RQ/GT0 has the highest priority than RQ/GT1
These lines are bidirectional and are used to both request
and grant a DMA operation.

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