NTHUEE 113 Fall Electronic II

EE226001 Electronics2
Homework 4
two-Stage Opamp with local CMFB and miller compensation

Due date: 2024.12.24 (Thu.) 10:10 (upload to eeclass system)

Suppose 𝑉𝐷𝐷 =1.8𝑉, temperature=27°C in this homework.

Please note that:

1. No delay allowed.
2. Please hand in your report using eeclass system.
3. Please generate your report with pdf format, naming rule follow the rule in the
last page.
4. Please hand in the spice code file (.sp) for each work. Do not include output file.
5. Please print waveform with white background, and make sure the X, and Y
labels are clear.
6. Please do not zip your report.

Remind that
⚫ Sweeping size or voltage without no design consideration will get no credits. You
should know what direction you want and sweep it to find the optimal point.
⚫ The minimum tuning step for W is 0.1um, L is 0.01um, voltage is 0.1V, current
is 0.1𝜇𝐴.
⚫ All body of MOS, please connect to VDD(if PMOS) or VSS(if NMOS)
⚫ No Negative voltage is allowed in the homework.
In this homework, you are asked to build the circuit shown in Fig. 1, and the
specifications you need to meet are listed in Table. 3. Please make sure your circuit
meets all specs in TT corner. Don’t be afraid. Please follow the guide line step by step.
You will make it.

Fig. 1. two Stage Opamp with Local Common Mode Feedback and miller compensation

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NTHUEE 113 Fall Electronic II

➢ Part I： 1st stage design and simulation

In this part, please follow the following step to design the 1st stage in Fig.1.
Moreover, the final simulation(including CMFB) should achieve the specification
shown in Table.1
✓ STEP1：Design the 1st stage with ideal voltage source as shown in Fig.2
(1) Write down your design for achieving the specification shown in Table.1
(must include the differential mode gain equation of the differential pair)
(2) Plug the designed sizing and biasing into hspice. Adjust the sizing and biasing
according to your observation and simulation to meet the specification. You
are required to describe in detail what the adjustments you do as well.
(3) Please print(Screenshot from .lis file) the small signal parameter of all MOS
and make sure all of them are in Saturation.
(4) Please print(Screenshot from .lis file) the gain and impedance from .tf
command. Then compare the gain with hand calculation and simulation.
Calculating the error between them.

✓ STEP2：adding CMFB to Fig.2 as shown in Fig.3

(1) Please describe how you choose Rsenp and Rsenn to make the gain attenuation
no larger than 1(V/V).
(Hint: How Rsenp and Rsenn change the equation for differential mode gain?)
(2) After adding Rsenp and Rsenn, if the performance of your circuit doesn’t meet
the specification, Please do some adjustments to sizing/biasing. You are
required to describe in detail what the adjustments you do as well.
(3) Fill the size table Part I

Fig. 2. 1st stage with ideal biasing Fig. 3. 1st stage with CMFB
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Step1 Simulation Step2 Simulation

Parameters Specification
(w/o CMFB) (w/ CMFB)
Supply Voltage (V) 1.8
Corner TT
Temp. (°C) 27
Rsenp, Rsenn(Ω) ------ ------
Vx(V) *note
Vbias(V) ------
Differential gain
𝑉𝑜𝑝 −𝑉𝑜𝑛 > 40
(| 𝑉 |)(V/V)
𝑖𝑝 −𝑉𝑖𝑛
Power(𝜇𝑊) < 20
Table. 1. Specification and Performance of PartI
1st stage amplifier
M0(W/L, m) ----------------
M1(W/L, m) M2(W/L, m)
M3(W/L, m) M4(W/L, m)
Size table Part I
Note：The biasing voltage for Vx is recommend to be 1.1V or 1.2V
(or you could design your own biasing)
(The accuracy of Vx voltage step is NOT limited. Using Vx=1.12345V is OK)
The 2nd stage is PMOS common source. After adding common mode feedback, if the
biasing is too low, M6 may be easily enter triode region. oppositely, if the biasing is
too high, M6 may be easily cut off.

Note：definition of power in all Table ─ please use .op command to print out the
parameter. You will find this line. Please fill the Table with the value you find.

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➢ Part II： adding the 2nd stage

1. Please describe the design consideration for 2nd stage(M5, M6) to meet the
specification shown in Table.2. (use the Vbias designed in the Part I for M5 biasing)
2. Plug the designed sizing and biasing into hspice. Adjust the sizing and biasing
according to your observation and simulation to meet the specification. You are
required to describe in detail what the adjustments you do as well.
3. Please print(Screenshot from .lis file) the small signal parameters of all MOS and
make sure all of them are in saturation.
4. Please print(Screenshot from .lis file) the gain and impedance from .tf command.
5. Fill up the size table Part II

Fig. 4. Adding 2nd stage to Fig.3

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Parameters Specification Part II simulation

Supply Voltage (V) 1.8

Corner TT
Temp. (°C) 27
Rsenp, Rsenn(Ω) ------ (write down 𝑅𝑠𝑒𝑛 from Table.1)
Vx(V) ------ (write down the final biasing from Table.1)
Vbias(V) ------ (write down the final biasing from Table.1)
𝑉𝑜𝑢𝑡
Gain= |𝑉 | (dB) > 60
𝑖𝑝 −𝑉𝑖𝑛
Power(𝜇𝑊) < 60
Table. 2. Specification and Performance of PartII
1st stage amplifier
M0(W/L, m) ----------------
M1(W/L, m) M2(W/L, m)
M3(W/L, m) M4(W/L, m)
2nd stage amplifier
M5(W/L, m) M6(W/L, m)
Size Table Part II

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➢ Part III： Adding miller compensation

1. Overall circuit analysis
In the following simulation, it would be a little bit complicated. We need some
direction for adjusting these parameters. Hence, we must first simplify the circuit and
analyze it. Due to the miller compensation, there will be pole splitting on the frequency
response, i.e, the miller effect decreases the -3dB bandwidth and moves the non-
dominant pole away. However, the miller compensation technique introduce a right-
half-plane(RHP) zero, which will degrade the phase margin. The simplified model is
shown in Fig. 5. Please apply KCL and KVL to find the
(a) DC gain
(b) pole1(𝜔𝑝1)
(c) pole2(𝜔𝑝2)
(d) unity gain bandwidth 𝜔𝑢
(e) zero1(𝜔𝑧1)
with the symbol shown in Fig.5.
(Hint: For simplified answer, you could refer to textbook.)

Fig. 5. Simplified model for the circuit in Fig.2

Note：Why the right-half-plane(RHP) zero degrade phase margin?

𝑠 𝜔
𝐻(𝑠) = 1 − => 𝐻(𝑗𝜔) = 1 − 𝑗
𝜔𝑟ℎ𝑝𝑧 𝜔𝑟ℎ𝑝𝑧
𝜔 𝜔
=> ∠𝐻(𝑗𝜔) = tan−1 (− ) = −tan−1 ( )
𝜔𝑟ℎ𝑝𝑧 𝜔𝑟ℎ𝑝𝑧
Hence, the phase margin will be degraded.

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2. Design of the circuit shown in Fig. 1

So far, we have the circuit shown in Fig. 4. For completing the circuit in Fig.1, we
need to further design the miller compensation capacitor and current mirror. And
in this part, you are required to meet the specification in Table.3
(1) Please describe the design of your current mirror (𝐼𝑟𝑒𝑓 , 𝑀𝑚𝑖𝑟 ).
(2) Please follow the hints to describe the design of the value of miller
compensation capacitor 𝐶𝑐 based on the parameters in Part II and the equation
in Part III.1 to meet the specification in Table.3
(Hint: For bandwidth specification, please use the derived equation in Part III.1)
(Hint: For phase margin specification, please follow the rule of thumb, i.e,
2nd pole frequency > 3 * unity gain frequency)
(3) Adjust the sizing if needed. You are required to describe in detail what the
adjustments you do.
Note： when you test the circuit in this part, please add a replica of 2nd stage amplifier,
miller capacitor and loading as the following circuit.

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3. Operating point Checking

(1) Please print out small signal parameters(include operation region)of all MOS
from .lis file.
(2) Please fill following table shown in below with the MOS size you designed
Current mirror & passive component & miller compensation
Mmir(W/L, m) Iref(A)
Rsenp, Rsenn(Ω) Cc(F)
1st stage amplifier
M0(W/L, m) ----------------
M1(W/L, m) M2(W/L, m)
M3(W/L, m) M4(W/L, m)
2nd stage amplifier
M5(W/L, m) M6(W/L, m)
Size Table Part III
(3) Why do we need current mirror? (Hint: Please replace the current mirror with
ideal biasing voltage source and run TT/FF/SS corner. Then, you could observe
the circuit operating point with and without current mirror under different
corners.)
4. Open-loop differential mode AC response
(1) Please plot the AC magnitude and phase response of differential-mode gain
and mark the pole1, pole2, zero1, unity gain frequency, dc gain, phase margin.
(2) Please print the gain and impedance from .tf command
(3) Please print the poles and zeros from .pz command
(4) Please check the results with your hand calculations(dc gain, pole1, zero1).
Discussion of the movement of poles after compensation(𝜔𝑝1 , 𝜔𝑝2 )

Parameters Specification Part III simulation

Supply Voltage (V) 1.8

Corner TT
Temp. (°C) 27
𝑉𝑜𝑢𝑡
Gain= |𝑉 | (dB) > 60
𝑖𝑝 −𝑉𝑖𝑛
-3dB Bandwidth(Hz) > 6k
Phase Margin(°) > 45
Power(𝜇𝑊) < 60
Table. 3. Specification and Performance of Part III
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NTHUEE 113 Fall Electronic II

➢ Bonus Part (optional)：Common mode feedback loop

This part involves advanced analysis. After finishing all the parts in the above, if
you have sparse time or you want to learn more than course, you could further answer
the question in this part.
In this part, the signal become common mode signal, different from the previous
differential signal. The input is in the same direction.
Note：If the opamp is in fully differential form, then
(Differential mode gain testing) As shown in the following figure, apply a differential
signal to the opamp, and then probe the differential output, Voutp and Voutn,
𝑉𝑜𝑢𝑡𝑝 − 𝑉𝑜𝑢𝑡𝑛
|𝐷𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑡𝑖𝑎𝑙 𝑀𝑜𝑑𝑒 𝐺𝑎𝑖𝑛| =
𝑉𝑖𝑛𝑝 − 𝑉𝑖𝑛𝑛

(Common mode gain testing) As shown in the following figure, apply a common
mode signal to the opamp, and then probe the single end output, Voutp or Voutn,
𝑉𝑜𝑢𝑡𝑝 𝑉𝑜𝑢𝑡𝑛
|𝐶𝑜𝑚𝑚𝑜𝑛 𝑀𝑜𝑑𝑒 𝐺𝑎𝑖𝑛| = 𝑜𝑟
𝑉𝑖𝑛 𝑉𝑖𝑛

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NTHUEE 113 Fall Electronic II

1. Common mode AC response(Overall)

(1) Please plot the AC magnitude of common mode gain.
(The gain at dc is called CMR(dB), i.e, common mode rejection)
(2) The simplified common mode model for Fig. 1 is shown in Fig. 6. Here is some
explanations for the notation in Fig. 6.
‧𝐴𝑣1.𝑐𝑚 is the common mode gain from Vin to Vop1.
‧𝐴𝑣2.𝑐𝑚 is the common mode gain from Vop1 to Vout.
‧𝐴𝑐𝑚𝑐 is the common mode gain from Vx to Vop1
Please find the equation of for the gain mentioned above, hand calculate it
with the parameters got from .lis.
(3) Based on the diagram shown in Fig. 6, please write down the common mode
𝑉𝑜𝑢𝑡
gain of whole circuit with common mode feedback, i.e, and also
𝑉𝑖𝑛 (𝑉𝑖𝑝 )

compare the calculated result with simulated result got from Bonus
Part.1.(1).

Fig. 6. Simplified common mode model for the circuit in Fig. 1

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NTHUEE 113 Fall Electronic II

2. Common mode AC response(break the common mode feedback loop)

The common mode feedback will also form a loop. When it comes to a feedback
loop, there must be the concern for loop stability, which will manifest on the phase
margin. Hence, in this question, we are going to inspect the phase margin of common
mode loop. The phase margin here is different from the one you get in
Part III.4.
(1) Recall what you learned in the lecture. When you want to see a phase margin of
a loop, you will probe the AC response of “Loop Gain”. Please write down the
equation of loop gain for common mode feedback loop with the notation in
Fig. 6 as well as calculating the real value of it.
(2) Break the loop as shown in Fig. 7. Please plot the AC magnitude and phase
response from Vin to Vout. Mark the DC gain and phase margin on the plot.
Compare the simulated result(DC gain) with hand calculated result from last
question. (Make sure the common mode loop phase margin large than 0°)(If
your common mode phase margin < 0°, you could adjust pole and zero along
the common mode loop to get a stable loop.)

Fig. 7. How to break the loop

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NTHUEE 113 Fall Electronic II

Homework Submission
Please upload the following document to the eeclass
1. Your report, named as “Electronics2_HW4_studentID_name.pdf”. E.x.,
Electronics2_HW4_123456789_廖帥哥.pdf.
If you have done the BonusPart1., please name as
“Electronics2_HW4_studentID_name_Bonus1.pdf”
If you have done the BonusPart1. & BonusPart2, please name as
“Electronics2_HW4_studentID_name_Bonus1_2.pdf”
2. Your circuit file
➢ HW4_diff_AC_tb.sp : differential mode testbench
(circuit file in Part III)
➢ HW4_cm_AC_w_cmfb_tb.sp : with CMFB loop common mode testbench
(circuit file in Bonus Part 1.)
HW4_cm_AC_break_cmfb_tb.sp : break CMFB loop common mode
testbench
(circuit file in Bonus Part 2.)
➢ Other .spi file(if you have)
Grading Policy
➢ Part I(30%)
1. Step1(20%)
2. Step2(10%)
➢ Part II.(30%)
➢ Part III (40%)
1. Overall circuit analysis(10%)
2. Design of the circuit shown in Fig. 1(10%)
3. Operating point Checking(5%)
4. Open-loop differential mode AC response(15%)
➢ Bonus Part(20%)
1. Common mode AC response(Overall)(10%)
2. Common mode AC response(break the common mode feedback loop)(10%)

Total point:120%

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Reference Hspice code

1. Differential mode gain testing (fully differential opamp)
.param VDD = 1.8
.param VCM = 0.9
* voltage source
Vdd vdd 0 dc=VDD
Vss vss 0 dc=0
VCM VCM 0 dc=VCM
Vdiff Vdiff 0 dc=0 ac=1

*Differential input
Ep Vip VCM VCVS Vdiff Vss 0.5
En Vin VCM VCVS Vdiff Vss -0.5

* fully differential opamp

X_opamp Vdd Vss VCM Vip Vin Voutp Voutn opamp

*The following is probing

*Operating point
.op

* differential gain
.tf V(Voutp, Voutn) Vdiff

* Frequency response
.AC DEC 10 1 10G
.probe AC vdb(Voutp, Voutn) vp(Voutp, Voutn)
.measure AC dc_gain find Vdb(Voutp, Voutn) at=1Hz
.measure AC bw when Vdb(Voutp, Voutn)='dc_gain-3'

* pole/zero
.pz V(Voutp, Voutn) Vdiff

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2. Common mode gain testing (single out differential input opamp)

.param VDD = 1.8
.param VCM = 0.9
* voltage source
Vdd vdd 0 dc=VDD
Vss vss 0 dc=0
VCM VCM 0 dc=VCM ac=1

* single out differential input opamp

X_opamp Vdd Vss VCM Vip Vin Vout opamp

*The following is probing

*Operating point
.op

* common mode gain

.tf V(Vout) VCM

* Frequency response
.AC DEC 10 1 10G
.probe AC vdb(Vout) vp(Vout)
.measure AC dc_gain find Vdb(Vout) at=1Hz
.measure AC bw when Vdb(Vout)='dc_gain-3'

* pole/zero
.pz V(Vout) VCM

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