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Chapter 4

INPUT/OUTPUT ORGANIZATION

4.1 ACCESSING I/O DEVICES

• The single bus arrangement is shown in the fig. 4.1.

• It consists of three sets of lines used to carry address, data and control signals.
• When the processor places the address of I/O device on the address line, the device that
recognizes this address responds to the commands issued on the control lines.
• The requested data are transferred over the data lines.

Memory Mapped I/O

• When I/O devices and memory share the same address space, the arrangement is called
memory-mapped I/O.
• With memory mapped I/O, any machine instruction that can access memory can be used
to transfer data to or from an I/O device. For example if DATAIN is the address of the
input buffer associated with the keyboard, the instruction
Move DATAIN,R0
reads the data from DATAIN and stores them into the register R0. Similarly theinstruction
Move R0,DATAOUT
sends the contents of register R0 to location DATAOUT which is the output databuffer of
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display unit.

Program Controlled I/O

• Some processor (Intel family), have special I/O instructions and separate 16 bit address
space for I/O devices. One advantage of this is that I/O devices deal with fewer
address lines
• Separate I/O address space does not mean that I/O address lines are separate from
memory address lines. A special signal on the bus indicates that the requested read or
write transfer is an I/O operation. When this signal is asserted, the memory unit ignores
the requested transfer.
• Figure 4.2 illustrates the hardware required to connect an I/O device to the bus.
• The device recognizes its address by using address decoder. The data register holds the
data being transferred to or from the processor. The status register contains information
relevant to the operation of the I/O device. Both data and status registers are connected to
the data bus and are assigned unique addresses. The control circuit coordinates I/O
transfer. The address decoder, data and status registers and the control circuitry required
to co-ordinate I/O transfers constitute the device's interface circuit.
• I/O device operates at speed lesser than that of the processor. By the time a
human enters one character, the processor can execute millions of instructions. Hence the
instruction to read a character from keyboard is executed only when a character is
available in the input buffer of the keyboard interface.
• For an input device such as keyboard, a status flag SIN is included in the
interface circuit as part of the status register. This flag is set to 1 when a
character is entered at the keyboard and cleared to 0 when this character is read by the
processor.
• Similarly output operations can be controlled by output status flag SOUT.

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Example:
✓ Let us consider an example of I/O operations involving a keyboard and adisplay
device in a computer system.
✓ The four registers shown below are used for data transfer operations.
✓ STATUS register contains two control flags, SIN and SOUT which providestatus
information for the keyboard and display unit respectively.
✓ Two flags KIRQ and DIRQ in STATUS register and KEN and DEN in
CONTROL register are used for interrupts.
✓ Data from keyboard are made available in the DATAIN register, and thedata
sent to the display are stored in DATAOUT register.

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✓ The program below reads a line of characters from keyboard and stores it ina
memory buffer starting a location LINE.
✓ Subroutine PROCESS is used to process the input line.
✓ As each character is read, it is echoed back to the display.
✓ Register R0 is used as a pointer to the memory buffer area.
✓ R0 is updated using Autoincrement addressing mode so that successive
characters are stored in successive memory locations.
✓ Each character is checked whether it is the Carriage Return (CR) characterwhich
has the ASCII code 0D (hex).
✓ If it is, a Line Feed character (ASCII code 0A) is sent to move the cursorone
line down on the display and subroutine PROCESS is called.
✓ Otherwise, the program waits for another character from the keyboard.
✓ This example illustrates program controlled I/O, in which processor repeatedly
checks status flag to achieve synchronization between processor and I/O device.

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4.2 INTERRUPTS

• Sometimes the processor time will be wasted while waiting for an I/O device to become
ready.
• This time can be eliminated by I/O device by sending a hardware signal called an
interrupt to the processor. A bus control line called interrupt signal line is dedicated for
this purpose.

Example:
Consider a task that requires some computations to be performed and the results to be
printed on a line printer. Let the program contain two routines COMPUTE( to produce a set of n
lines of output) and PRINT( to print the output).
The required task may be performed by repeatedly executing first the COMPUTE routine
and then the PRINT routine. The printer accepts only one line of text at a time. The disadvantage
of this process is that the processor spends considerable amount of time waiting for the printer to
get ready. So COMPUTE and PRINT routines must be overlapped.
1. COMPUTE routine is executed to produce the first n lines of output. Then
PRINT routine is executed to send the first line of text to the printer.
2. Instead of waiting for the line to be printed, the PRINT routine may be
temporarily suspended and execution of COMPUTE routine continued.
3. Whenever the printer becomes ready, it alerts the processor by sending an
interrupt request signal.
4. The processor interrupts the execution of the COMPUTE routine and transfers
control to the PRINT routine.
5. The PRINT routine sends the second line to the printer and is again
suspended.
6. The interrupted COMPUTE routine resumes execution at the point of interruption.
7. This process continues until all n lines are printed and the PRINT routine ends.
• In the above example PRINT routine is the interrupt service routine
• Assume that an interrupt request arrives during execution of instruction i in the
figurebelow.
• The processor first completes execution of instruction i, then it loads the PC with
theaddress of the first instruction of interrupt service routine.
• To return back to the instruction i+1, the contents of PC are saved in processor stack.
• After the completion of interrupt service routine, the contents of processor stack
arereloaded back into PC.

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• However, the processor must inform the device that its request has been recognized so
that it may remove its interrupt request signal.
• This can be accomplished by using an interrupt acknowledge signal.
• The status or data register in the device interface may also inform that its interrupt
request has been recognized.
• Before starting the execution of ISR, any information that may be altered during the
execution of that routine must be saved.
• The information that needs to be saved include condition code flags and the contents of
any registers used by both the interrupted program and interrupt service routine.

Difference between Subroutine and Interrupt Service Routine

Subroutine Interrupt Service Routine

It is a portion of the code within a large
program which performs a specific task. ISR are to handle hardware interrupts.

It runs whenever a certain signal

It runs when we call it.
occurs.
We know where the subroutine runs We don't know when ISR will be
because we call it. executed.

• The task of storing and restoring information can be done automatically by the processor.
But this increases the total execution time. Saving registers also increases the delay
between the time an interrupt request is received and the start of execution of the
interrupt service routine. This delay is called interrupt latency. This latency should be
kept minimum. So the processor saves only the contents of program counter and
processor status register.
• Duplicate sets of processor registers can be used by ISR. This eliminates the
need to save and restore registers.
• Real Time Processing is processing of certain routines which are accurately timed
relative to external events.

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4.2.1 Interrupt Hardware:

• The figure below shows that a single interrupt line can serve n devices.
• To request an interrupt, the device closes its associated switch.
• If all interrupt request signals are inactive (all switches are open), the voltage on the
interrupt request line will be equal to Vdd. This is inactive state of the line.
• When a device requests an interrupt (switch is closed), the voltage on the line drops to 0
causing the interrupt request signal INTR received by the processor togo to 1.
• The value of INTR is the logical OR of the requests from individual devices. INTR
= INTR1 + ........................... + INTRn
• In the electronic implementation of the circuit in fig. 4.6, special gates known as open
collector (for bipolar circuits) or open drain (for MOS circuits) are used to drive the
INTR line.
• The resistor R is called a pull up resistor because it pulls the line voltage up to the
high voltage state when the switches are open.

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4.2.2 Enabling and Disabling Interrupts

• Sometimes the interrupts may alter the sequence of events envisaged by the programmer.
In some cases, the ISR may change some of the data used by the instruction in question.
So enabling and disabling of interrupts must be available.
• A simplest way is to provide machine instructions such as Interrupt-enable and Interrupt-
disable.
• When a device activates the interrupt request signal, it will be active during the execution
of ISR. This active request should not lead to successive interruptions causing the system
to enter an infinite loop from which it cannot recover. There are three mechanisms to
solve this problem.
• The first possibility is to have the processor hardware ignore the interrupt request
line until the execution of the first instruction of the ISR has been completed. The
programmer can ensure that no further interruptions will occur by using Interrupt- disable
instruction as the first instruction of the ISR. The Interrupt-enable instruction is the last
instruction of the ISR before the Return from interrupt instruction.
• In second option (for processor with only one interrupt request line), the
processor can automatically disable interrupts before starting the execution of the ISR.
One bit of program status register (PS), called interrupt enable indicates whether
interrupts are enabled. After saving the contents of PS on stack, the processor clears the
interrupt enable bit in its PS register thus disabling further interrupts. When the Return-
from-interrupts instruction is executed, the contents of PS are restored from the stack
setting the Interrupt-enable bit back to 1.
• In the third option, the processor has a special interrupt request line for which the
interrupt handling circuit responds only to the leading edge of the signal. Such a

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line is said to be edge triggered. In this case, the processor will receive only onerequest.
Hence no danger of multiple interruptions.
• Following are the sequence of events involved in handling an interrupt request
from a single device.
➢ The device raises an interrupt request.
➢ The processor interrupts the program currently being executed.
➢ Interrupts are disabled by changing the control bits in the PS
➢ The device is informed that its request has been recognized, and inresponse, it
deactivates the interrupt request signal.
➢ The action requested by the interrupt is performed by the ISR.
➢ Interrupts are enabled and execution of the interrupted program isresumed.

4.2.3 Handling Multiple Devices

There is a possibility that many devices may interrupt at the same time. Some of themethods of
overcoming this situation is

➢ One method of overcoming this situation is polling scheme. Normally when a device
raises an interrupt request, the IRQ bit in its status register is set to 1. In polling scheme,
the ISR polls all the I/O devices connected to the bus. The first device encountered with
its IRQ bit set is the device that should be served. Its main disadvantage is the time spent
interrogating the IRQ bits of all the devices that may not be requesting any service.
➢ Vectored Interrupts: The device requesting an interrupt can identify itself by
sending a special code to the processor over the bus. The code supplied by the device
may represent the starting address of the ISR for that device. The code length is in the
range of 4-8 bits. This arrangement implies that the ISR for the given device must always
start at the same location. However, the location pointed to by the interrupting device can
be used to store the starting address of ISR. The processor reads this address called
interrupt vector and loads it into the PC. Sometimes the processor may not be ready to
receive the interrupt vector code immediately. So the interrupting device must wait to put
the data on the bus only when the processor is ready to receive it. When the processor is
ready to receive the interrupt vector code, it activates the interrupt acknowledge line
INTA. The I/O device responds by sending its interrupt vector code and turning OFF the
INTR signal.
➢ Interrupt Nesting:
o There might be long delay in responding to an interrupt signal which mightlead
to erroneous operation. For example, a computer that keeps track of

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the time of day using a real time clock. This is a device that sends
interrupt requests to the processor at regular intervals. For each of these requests
the processor executes a short ISR to increment a set of counters in the memory
that keep track of time in seconds, minutes and so on. This interrupt request from
the clock must be accepted even during theexecution of the ISR of another device.
Hence I/O devices must be organized in the priority structure.
o In multiple level priority organization the priority level is assigned to the
processor. The priority level of the processor is the priority of the program that is
currently being executed. The processor accepts interrupts only from devices that
have priorities higher than its own. This action disables interrupts from devices at
the same level of priority or lower. However interrupt requests from higher
priority devices will continue to be accepted.
o A few bits of processor status word (PSW) denotes processor's priority. It can be
changed by program instructions that write into the PS. These are privileged
instructions which can be executed only when processor is executing OS
routine. The user program cannot change the priority. An attempt to execute
privileged instructions while in user mode leads to a special type of interrupt
called privilege exception.
o However separate Interrupt Request and Interrupt acknowledge lines can be used
for each device. Each of the interrupt request lines is assigned a different priority
level. Interrupt requests received over these lines are sent to a priority arbitration
circuit in the processor. A request is accepted only if it has a higher priority level
than that currently assigned to the processor.

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• Simultaneous Requests:
o There is a problem when simultaneous interrupt requests arrive. The requests with
highest priority can be accepted but if several devices share one interrupt request
line then there is a problem.
A Daisy Chain method of connecting the devices can solve this problem to some extent. In this
the Interrupt Request line is common to all the devices. The Interrupt acknowledgement line
INTA signal propagates serially through devices shown in figure 8a. . When several devices raise
an interrupt request INTR line is activated, the processor responds by setting the INTA line to 1.
This signal is received by device1. Device 1 passes the signal to device2 only if it does not require
any service. If device 1 has a pending request, it blocks INTA signal and proceeds to put its
identifying code on the data lines. In this arrangement the device that is electrically closest to the
processor has the highest priority and so on.

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4.4 DIRECT MEMORY ACCESS

• Direct Memory Access (DMA) is an approach in which large blocks of data re

transferred at high speed directly between an external device and the main memory
without continuous intervention by the processor.
• DMA Controller - It is a control circuit that is a part of I/O device to perform DMA
transfer. For each word transferred, it provides memory address and all the bus signals
that control data transfer. DMA controller must even increment the memory address for
successive words and keep track of the number of transfers.
• Although DMA controller can transfer data without intervention by the processor, its
operation must be under the control of a program executed by the processor. The
processor sends the starting address, the number of words in the block and the direction
of the transfer. On receiving this information the DMA controller performs the requested
operation. When the entire block has been transferred, the controller informs the
processor by raising an interrupt signal. After the DMA transfer is completed, the
processor can return to the program that requested the transfer. The OS is responsible for
suspending that requested the transfer in Blocked State, initiating DMA operation and
starting another program.
• The figure below shows an example of the DMA controller register.
o Two registers are used for storing the starting address and the word count. The
third register contains status and control flags.
o The R/W bit determines the direction of transfer. When this bit is set to 1, the
controller transfers data from memory to the I/O device (read operation).
Otherwise it performs write operation.
o When the controller has completed transferring a block of data, it sets the Done
flag to 1.
o Bit 30 is the interrupt enable flag, IE, which causes the controller to raise an
interrupt after it has completed transfer of a block of data (when set to 1).
o The controller sets IRQ bit to 1 when it has requested interrupt.

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• Burst Mode - The transfer of block of data between Main memory and I/O device by
DMA controller without interruption is called burst transfer mode (Same explanation of
DMA and DMA controller).
• Cycle Stealing - This is similar to burst transfer mode, but instead of data being
transferred all at once, it is transferred one byte at a time. The DMA controller, after
transferring one byte of data, releases control of the system buses, lets the CPU process
an instruction and then requests access to the bus by sending the bus request signal
through the control bus and then transfers another byte of data. This keeps going on until
all the data has been transferred. The transfer rate is slower but it prevents the CPU from
staying idle for a long period of time.
• The figure below shows the use of DMA controller in a computer system. Let a block of
data has to be transferred from main memory to one of the disks. A program writes the
address and word count information into the registers of the corresponding channel of the
DMA controller. Then all the steps mentioned for fig 4.18 are carried out

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4.4.1 BUS ARBITRATION

Centralized Arbitration

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Distributed Arbitration

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