28 CHAPTER TWO

FIGURE 2.10 TCON and TMOD Function Registers

7 6 4 3 2

TF1 TR1 TFO TRO IE1 IT1 IEO ITO

THE TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTER

Bit Symbol Function
7 TF1 Timer 1Overflow flag. Set when timer rolls from all ones to zero. Cleared when processor
vectors to execute interrupt service routine located at program address 001Bh.

6 TR1 Timer 1 run control bit. Set to 1 by orogram to enable timer to count: cleared to 0 by
program to halt timer. Does not reset timer

TFO Timer 0 Overflow flag. Set when timer rolls from all ones to zero. Cleared when processor
vectors to execute interrupt service routine located at program address 000Bh.

TRO Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by
program to h¡lt timer. Does not reset timer.
IE1 External interrupt 1edge flag. Set to 1when a high to low edge signal is received on port 3
pin 3.3 (INT1). Cleared when processor vectors to interrupt service routine
located at program address 0013h. Not related to timer operations.
2 IT1 External interrupt 1signal type control bit. Set to 1by program to enabie external interrupt 1
to be triggered by a falling edge signal. Set to 0 by program to enable a low level
signalon external interrupt 1 to generate an interrupt.
IE0 External interrupt Oedge flag. Set to I when a high to low edge signal is received on port 3
pin 3.2 (INTO). Cleared when processor vectors to interrupt service routine located at
program address 0003h. Not related to timer operations.
Continued

first 32K RAM (000Oh-7FFFh) can then be enabled when Al5 of port 2 is low, and the
second 32K RAM (8000h - FFFFh) when A15 is high, by using an inverter.
Note that the WR and RD Signals are alternate uses for port 3 pins 16 and 17. AlIso,
port Ois used for the lower address byte and data: port 2 is used for upper address bits. The
use of external memory consumes many of the port pins, leaving only port I and parts of
port 3 for general /0.

Counters and Timers

Many microcontroller applications require the counting of external events, such as the
frequency of apulse train, or the generation of precise internal time delays between com
puter actions. Both of these tasks can be accomplished using software techniques, but
software loops for counting or timing keep the processor occupied so that other, perhaps
more important, functions are not done. To relieve the processor of this burden, two 16-bit
up counters, named TO and TI, are provided for the general use of the programmer. Each
counter may be programmed to count internal clock pulses, acting as a timer, or pro
grammed to count external pulses as a counter.
 29
THE 8051 ARCHITEC TURE

Bit Symbol Function

program to enable external interrupt O
ITO External interrupt 0 signal type control bit. Set to 1by by program to enable a low level
to 0
to be triggered by a falling edge signal. Set interrupt.
signal on external interrupt 0 to generate an
Bit addressable as TCON.0 to TCON.7
4 3 2 1
7 6 5

MO Gate cà M1 MO
Gate M1

Timer 1 Timer O

THE TIMER MODE CONTROL (TMOD) SPECIAL FUNCTION REGISTER

Bit Symbol Function
to 1by program to enable
7/3 Gate OR gate enable bit which contros RUN/STOP of timer 1/0. Set interrupt INT1/0 pin is
timer to run if bit TRI/0 in TCON is set and signal on external
timer to run if bit TR1/0 in TCON is set.
high. Cleared to 0 by program to enable
from external
6/2 Set to 1 by program to make timer 1/0 act as a counter by counting pulses
input pins 3.5 (T1) or 34 (TO). Cleared to 0 by program to make timer act as a timer
by counting internal frequency

5/1 M1 Timer/counter operating mode select bit 1 Set/cleared by program to select mode

4/0 MO Timer/cOUnter operating mode select brt O. Set/cleared by program to select mode
M1 MO Mode

1
2
1 1 3

TMOD is not bit addressable

The counters are divided into two 8-bit registers called the tiner low (TL0, TL) and
high (TH0, THI)bytes. Allcounter action is controlied by bit states in the timer mode
control register (TMOD), the timer/counter control register (TCON), and certain program
instructions.
TMOD is dedicated solely to the two timers and can bc considered to be two duplicate
4-bit registers, cach of which controls the action of one of the timers. TCON has control
bits and flags for the timers in the upper nibble, and control bits and flags for the external
interrupts in the lower nibble. Figure 2. 10 shows the bit assignments for TMOD and TCON.
Timer Counter Interrupts
The counters have been included on the chip to relieve the processor of timing and count
ing chores. When the program wishes to count a certain number of internal pulses or
external events, a number is placed in one of the counters. The number represents the
maximum count less the desired count, plus one. The counter increments from the initial
number to the maximum and then rolls over to zero on the final pulse and also sets a timer
fag. The flag condition may be tested by an instruction to tell the program that the count
has been accomplished, or the flag may be used to interrupt the program.
 CHAPTER TWO
30

FIGURE 2.11 Timer/Counter Control Logic

Timer

Oscitlator + 12d
Frequency

cT -0(TMOD Timer Operation)

To Timer Stages

cT - 1(TMOD Counter Operation)

Counter
T1/0 Input Pin

TRI/0 Bit In TCON

Gate Bit In TMOD

INTI/0tnput Pin

Timing
internal clock frequency of the
Ifa counter is programmed to be a timer, it will count the
8051 oscillator divided by 12d. As an example, if the crystal frequency is 6.0 megahertz.
then the timer clock will have a frequency of 500 kilohertz.
Figure
The resultant timer clock is gated to the timer by means of the circuit shown in TMOD
oscillator clock pulses to reach the timer, the C/T bit in the
2.I1. In order for
be set to l
register must be set to 0 (timer operation). Bit TRX in the TCÔN register must must
(timer run), and the gate bit in the TMOD register must be 0, or external pin INTX
1. In other words, the counter is configured as a timer, then the timer pulses are gated
be a
bits INTX.
to the counter by the run bit and the gate bit or the external input
Timer Modes of Operation
the mode bits.
The timers may operate in any one of four modes that are determined by
MI and M0, in the TMOD register. Figure 2.12 shows the four timer modes.

Timer Mode 0
Setting timer X mode bits to 00b in the TMOD register results in using the THX register
so
as an 8-bit counter and TLX as a 5-bit counter; the pulse input is divided by 32d in TL
that TH counts the original oscillator frequency reduced by a total 384d. As an example,
the 6 megahertz oscillator frequency would result in a final frequency to TH of 15625
hertz. The timer flag is set whenever THX goes from FFh to OOh, or in .0164 seconds for
a 6 megahertz crystal if THX starts at 00h.

Timer Mode 1
Mode I is similar to mode 0 except TLX is configured as a full 8-bit counter when the
mode bits are set to 0lb in TMOD. The timer flag would be set in .131lseconds using
a6 megahertz crystal.
 THE 8051ARCHITECTURE 31

Modes
FIGURE 2.12 Timer 1and Timer 0 Operation
interrupt
TEX
Pulse
TLX 5 Bits THX 8Bits
Input
(Figure 2.11)
Timer/Counter
Timer Mode O 13- Bit

Puise TFX Interrupt

TLX 8 8its THX 8 Bits
Input
(Figure 2.11)

Timer Mode 1 16- Bit Timer/Counter

Pulse TEX Interrupt

tnput TX8 Bits
(Figure 2. 11)

Reload TY

THX 8 Bits

Timer Mode 2 Auto- Reload of TL from TH

Pulse TFO
TLO 8 Bits Interrupt
Input
(Figure 2.11)

THO 8 Bits TFI Interrupt

f/12

TRI Bit
In TCON
Timer Mode 3 Two8-Bit Timers Using Timer O

Timer Mode 2
Setting the mode bits to 10b in TMOD configures the timer to Use only the TLX counter as
an 8-bit counter. THX is used to hold a value that is loaded into TLX every time TLX
overfiows from FFh to 00h. The timer flag is also set when TLX overflows.
This mode exhibits an auto-reload feature: TLX will count up from the number in
THX,overflow, and be initialized again with the contents of THX. For example, placing
32 CHAPTERWO

Ch inTHX will result in a delay of exactly

if a 6 megahertz crystal is 0002 seconds beforc the overflow iag IS Sel
uscd.
Timer Mode 3
imers 0 and I may be programmed 1o be in mode 0, 1, or 2 independenly of a simlar
mode for the other timer. This is not true for mode 3: the timers do not operate indepen
dently if mode 3 is chosen for timer 0. Placing timer I in mode 3 causes it to stop count
ing: the control bit TRI and the timer Iflag TFIare then used by timer 0.
Timer Oin mode 3becomes two completely separate 8-bit counters. TLO is controlled
by the gate arrangement of Figure 2.11 and sets timer flag TFO whenever it overflows from
FPh to 00h. THO receives the timer clock (the oscillator divided by 12) under the control
of TRI only and sets the TFI flag when it overflows.
Timer I may still be used in modes 0. 1, and 2, while timer Ois in mode 3 with one
mportant exception: No interrupts will be generated by timer I while timer 0 is using the
TFloverflow flag. Switching timer I to mode 3 will stop it (and hold whatever countis in
timer l). Timer I can be used for baud rate generation for the serial port, or any other
mode 0, 1, or 2 function that does nÍt depend upon an interrupt (or any other use of the
TFI Aag) for proper operation.
Counting
The only difference between counting and timing is the source of the clock pulses to the
counters. When used as a timer, the clock pulses are sourced frorn the oscillator through
the divide-by-I2d circuit. When used as a counter, pin TO (P3.4) supplies pulses to
counter 0, and pin TI (P3.5) to counter 1. The C/T bit in TMOD must be set to I to enable
pulses from the TX pin to reach the control circuit shown in Figure 2. ll.
The input pulse on TX is sampled during P2 of state 5 every machine cycle. A change
on the input from high to low between samples will increment the counter. Each high and
low state of the input pulse must thus be held constant for at least one machine cycle to
ensure reliable counting. Since this takes 24 pulses, the maximum input frequency that
can be accurately counted is the oscillator frequency divided by 24. For our 6 megahertz
crystal, the calculation yields a maximum external frequency of 250 kilohertz.

Serial Data Input/Output

Computers must be able to communicate with other computers in modern multiprocessor
distributed systems. One cost-effective way to communicate is to send and recejve data
bits serially. The 8051 has a serial data communication circuit that uses register SBUF to
hold data. Register SCON controls data communication, register PCON controls data
rates, and pins RXD (P3.0) and TXD (P3.1) connect to the serial data network.
SBUF is physically two registers. One write only and is used to hold data to be
transmitted out of the 8051 via TXD. The other is read only and holds received data from
external sources via RXD. Both mutually excBusive registers use address 99h.
There are four programmable modes for serial data communication that are chosen by
setting the SMX bits in SCON. Baud rates are determined by the mode chosen. Figure 2. 13
shows the bit assignments for SCON and PCON.
Serial Data Interrupts
Serial data communication is arelatively slow process, occupying many miliseconds per
data byte to accomplish. In order not to tie up valuable processor time, serialdata flags are