Indonesian Journal of Electrical Engineering and Computer Science

Vol. 22, No. 1, April 2021, pp. 62~70

ISSN: 2502-4752, DOI: 10.11591/ijeecs.v22.i1.pp62-70  62

Design and analysis of RNS-based sign detector for moduli set

{2n, 2n-1, 2n+1}

Raj Kumar, Ram Awadh Mishra

Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology Allahabad,
Prayagraj-211004, India

Article Info ABSTRACT

Article history: Magnitude comparison, sign detection and overflow detection are essential
operations of residue number system (RNS) that are used in digital signal
Received Jul 20, 2020 processing (DSP) applications. Moreover, sign detection attracts significant
Revised Dec 22, 2020 attention in RNS as it can also be used in division and magnitude comparison
Accepted Jan 17, 2021 operations. However, these operations are not easy to perform in RNS. So,
there is a need arise to propose a computationally advanced RNS based sign
detector. This paper presents an area and power-efficient sign detection
Keywords: circuit for modulo {2n-1, 2n, 2n+1} using mixed radix conversion technique.
The proposed sign detector is constructed using a carry save adder (CSA), a
Digital signal processing modified parallel prefix adder and a carry-generation circuit. Based on the
Mixed radix conversion synthesized results using synopsys design compiler, the introduced design
Residue number system offers better results in terms of the area required and power consumption.
Sign detection Although, the speed will remain the same when compared to the recent sign
VLSI design detectors for the same moduli set.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Raj Kumar
Electronics and Communication Engineering Department
Motilal Nehru National Institute of Technology Allahabad
Prayagraj-211004, India
Email: [email protected]

1. INTRODUCTION
Unlike the binary number system (BNS), the residue number system (RNS) is a non-weighted and
non-conventional representation. RNS has some properties that can be used in many mathematical operations
that give better results when compared to BNS. In RNS, a large positive integer X is represented using a set
of smaller integers known as residues {x1, x2,…, xN} and a set of co-prime integers known as moduli set {m1,
m2,…, mN}. Addition [1-3] and multiplication [4-6] are two main basic arithmetic operations in RNS.
Remarkably, RNS has non-weighted representation, such that the addition and multiplication operations can
be performed simultaneously and independently in each residue channel. Therefore, no carry propagation
occurs from one residue channel to another. Hence it is also known as carry free number system. Due to this
nature of RNS, it is used in applications that require low power dissipation and high speed, such as digital
communications systems [7], digital signal processing [8-12], and cryptography [13-14]. For all such
applications, RNS provides outstanding performance with high computational speed, lesser area, and low
power dissipation, which are the major objective of today’s real-time processors. Additionally, the reverse
conversion [15-17], division [18-19], scalar [20], magnitude comparison [21-22], overflow detection [23-25]
and sign detection [26-37] are also the essential operation of RNS. These operations are not easy to perform
in RNS. Therefore, an improvement in such areas may lead to advanced DSP architectures using RNS. As,
sign detection plays an important role in DSP applications.

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Indonesian J Elec Eng & Comp Sci ISSN: 2502-4752  63

In addition, a sign detection circuit is also used in division and comparison operations. So, the sign
detection is an important arithmetic operation of RNS. The reverse converter can be used as a sign detector as
the most significant bit (MSB) of the reverse converter represents the sign of residue number. However, this
process is very complex. So, in order to avoid the complexity of the circuit, a truncated version of the reverse
converter is used as a sign detector. Recently numerous efforts have been made in the area of sign detector,
which presents different architectures of sign detector for different moduli sets. Some of them are designed
for universal moduli set [26-29], 3-moduli set [30-34] and extended moduli set [35-37]. The 3-moduli set {2n
–1, 2n, 2n+1} is very popular as this results in less complex arithmetic circuits due to the availability of the
number of modulo properties. Also, the forward and reverse converter circuits require fewer components than
other moduli sets.
Initially, the sign detector was implemented using the look-up-table concept that requires some
memories to store the look-up-table data [26]. These types of sign detectors were suitable only for small
word-length and practically, it is not realizable for larger word-length as it requires huge memories. To
overcome this problem, VLSI component based sign detector is proposed in [27] without using any look-up-
table. However, the sign detector presented in [27] is very complex as it was implemented using modulo
multipliers. Moreover, the sign detection circuit for modulo {2 n-1, 2n, 2n+1} using CRT-II was presented in
[30] that was implemented using two carry generation circuits, a carry-save adder (CSA), and some basic
gates. Again, a new sign detector was presented in [31], in which a comparator is used in place of the carry
generation circuit to improve the performance of [30]. The recent sign detection circuit using CRT-II and
scaling technique is proposed in [33], which was implemented using a carry-generator, a CSA for the
accumulation of three numbers, and a adder structure for the calculation of the most significant bit. This
paper presents a sign detection circuit for modulo {2 n-1, 2n, 2n+1} which is based on a mixed radix
conversion theorem that requires less circuit as compared to the previous one.
Section 1 itself describes the overview and applications of RNS, and also it consists of a brief
overview of sign detection. The remaining paper is ordered in the following sequence: The representation of
a number in RNS and some essential properties used to simplify the proposed algorithm are explained in
Section 2. The introduced algorithm of sign detector and their circuit implementation are discussed in Section
3. The analysis and comparison of proposed and existing designs for the same moduli set are described in
Section 4. At last, a brief summary of the proposed work is drawn in conclusion Section 5.

2. PRELIMINARIES
As per the previous discussion, a positive integer X is denoted by its residues {x1, x2,…, xN} and a
set of co-prime integers known as moduli set {m1, m2, . . . , mN}. The integer X should follow the condition
N
0  X  M , where M represents the dynamic range of X, M   m . The residues x is the remainder when
i 1
i i

number X is divided by mi (xi=X modulo mi ).

The signed representation of X can be written as Xs and the sign of Xs can be determined from the (1):

 0,if   X   M / 2  
sign( X s )   
1,if  M / 2   X  M  (1)

now, the integer Xs can be determined by given in [34].

 M M 
Xs  X     
 2 M  2 
(2)

Where, . and . are the smallest and greatest integer function, respectively, i.e. 5.2  6 and

5.2  5 .
Some of the essential properties of RNS used to design efficient sign detector circuits are discussed
here.
Property 1: The modulo of a negative integer X can be obtained by,

Design and Analysis of RNS-based Sign Detector for Moduli Set {2n, 2n-1, 2n+1} (Raj Kumar)
64  ISSN: 2502-4752

 X if m  2  1
n

X 
 X  1if m  2 
m n

here the 1’s complement of X is represented by X .

Property 2: If the integer X is multiplied by any arbitrary scalar quantity in terms of power of two, it
can be simplified by given property:

2p X  CLS ( X , p)
2n 1

where CLS (X,p) denotes the circular left shift of X by p bits.

Property 3: The modulo 2n-1 addition of two integers X and Y is given by,

X  Y 2n 1  X  Y  Co 2n

where, Co=0, when X  Y  2n  1 and Co=1, when X  Y  2n  1.

3. PROPOSED SIGN DETECTOR FOR MODULO {2n-1, 2n, 2n+1}

The proposed sign detector for modulo {2n-1, 2n, 2n+1} is described in this section. Let (x1, x2, x3) is
the residues of X and {m1, m2, m3}={2n-1, 2n, 2n+1} is taken as the moduli set in a RNS. The bit-wise
representation of the residues x1, x2 and x3 are given as:

x1  x1,n 1 x1,n  2 ...x1,0  x1,n 1:0

x2  x2,n 1 x2,n 2 ...x2,0  x2,n 1:0

x3  x3,n x3,n 1 ...x3,0  x3,n: 0

3

in this paper, the MRC theorem is used to determine integer X from its residues (x1, x2, x3) and moduli set
{m1, m2, m3}. According to the MRC theorem,

X  z3 m3 m1  z2 m3  z1
(3)

where, 0 ≤ z1 < m3, 0 ≤ z2 < m1 and 0 ≤ z3 < m2. The MSB of (3) represents the sign bit of X which is equal to
the MSB of z3. Therefore, our aim is to determine the MSB of z3.
To determine the value of z1, apply modulo m3 in (3), it gives,

z1  x3 (4)

to calculate the value of z2, applying modulo m1=2n-1 in (3), it gives,

X m1
 z2 m3  z1 m
1
(5)

substituting the value of m1, m3 and z1 in (5),

x1  2 z2  x3 m1
(6)

now, (6) can be rewritten as:

x1  km1  2 z2  x3
(7)

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Indonesian J Elec Eng & Comp Sci ISSN: 2502-4752  65

where, k is the scalar integer. Multiplying (7) by 2n-1 and rearranging the equation for z2 and take modulo m1,

z2  2n1 ( x1  x3 )
2n 1 (8)

2n1 x1  x1,0 x1,n1 ...x1,1  xˆ1

2n 1
(9)

Now, x3 2n 1
 2n x3,n  x3,n 1:0
2n 1

 x3,n 1 x3,n 2 ...x3,1 ( x3,0  x3, n )  x3

2n1 x3  ( x3,0  x3,n ) x3,n1 ...x3,1  xˆ3

2n 1 (10)

substitute the (9) and (10) into (8) and also applying properties 1 and 3, we have,

z2  xˆ1  xˆ3 2n 1  xˆ1  xˆ3  xˆ1  xˆ3  Co

2n 1 2n (11)

to evaluate z3, apply modulo m2=2n in (3), it gives:

x2  z3 (22n  1)  z2 (2n  1)  z1
2n (12)

x2   z3  z2  x3 2n
(13)

re-write the (13) for z3,

z3  ( x3  x2 )  z2  km2 (14)

applying modulo m2 on both side of (14) and also substitute the value of z2 from (11),

z3  ( x3  x2 )  xˆ1  xˆ3  Co
2n (15)
the term x3 2n
can be written as x3, n 1:0 and applying property 1 in (15),

z3  x3,n1:0  x2  1  xˆ1  xˆ3  Co

2n (16)

the term x3,n 1:0  xˆ3 of (16) can be further simplified as,
2n

x3,n1:0  xˆ3  xˆ3  x3,0  1 2n

2n (17)

substituting the value from (17) in (16),

z3  xˆ1  x2  xˆ3  x3,0  Co

2n (18)

the MSB of z3 can be determined from the simplified (18) that can be used as sign bit, i.e., sign (X)=sign (z3).
There are two cases of z3: when MSB of z3 is 0, i.e., 0  z3  2n 1 , in this case, the integer X is a positive
number. In other cases, when MSB of z3 is 1, i.e., 2n 1  z3  2n , that means the integer X is a negative
number.

Design and Analysis of RNS-based Sign Detector for Moduli Set {2n, 2n-1, 2n+1} (Raj Kumar)
66  ISSN: 2502-4752

Now, the proposed design of the sign detector can be implemented from (18) using a CSA, carry
generator, and a modified parallel-prefix adder (MPPA) as shown in Figure 1. Here, the CSA is used to
accumulate the three numbers, which is used to obtain the sum S  sn 1 : 0 and carry C  cn 1 : 1 0 in (18).
As in (18) modulo 2n is taken; therefore, the carry generation in the CSA circuit is not required, so it can now
be neglected. For the more significant architecture of sign detector, replace the bit c0=0 of carry C by x3,0 of
(18). The new carry vector will be C   cn 1 : 1 x3,0 . The carry Co of (11) can be generated using PPA
structure with some modification as depicted in Figure 2. Figure 3 shows the circuit diagram of the modified
parallel-prefix adder structure for n=8. This circuit is a modification of the parallel prefix adder structure,
which is intentionally designed to generate only MSB bit, i.e. MSB (z3).
Example: For n=8, {m1, m2, m3}={255, 256, 257} and the dynamic range, M=16776960. Let a
signed integer Xs=-440 which is equals to the integer X=16776520 in the given RNS. The residue of X is {x1,
x2, x3}={70, 72, 74}. The integers x1, x2 and x3 can be written as (01000110)2, (01001000)2 and (001001010)2,
respectively. To determine the values of z3 of (18), some intermediate terms are required that can be
determined using (9) and (10): xˆ1  00100011 and xˆ3  00100101 . Also, x2 and x3,0 can be written directly
from x2 and x3, i.e., x2  10110111 and x3,0=0. The term Co can be determine from (11), xˆ1  xˆ3  (72)10
which is less than 255 (28-1), so from property 3, Co=0. Now, substitute all these values in (18),
z3  00100011  10110111  00100101  0  0  11111111 . Since, the MSB of z3 is 1, the integer Xs represented
by {70, 72, 74} is negative number.

x̂1 x2 x̂3 x̂1 x̂33

n-bit Carry Save Adder Carry generator

C x3,0
S

C
Co
Modified parallel prefix adder

X MSB

Figure 1. The proposed sign detection circuit


x̂1,7 x̂3,7 ... 
x̂1,0 x̂3,0

p i, g i p i, g i pi, gi pi, gi pi, gi pi, gi pi, gi pi, gi

xˆ1,i xˆ3, i gi gi-1 pi pi-1

pi, gi  

Co gi pi
g p

Figure 2. Carry generation circuit

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Indonesian J Elec Eng & Comp Sci ISSN: 2502-4752  67

s6 c6 s5 c5 s4 c4 s3 c3 s2 c2 s1 c1 s0 x3,0

pi, g i pi, g i pi, gi pi, gi pi, gi pi, gi pi, gi

g6:0
p6:0 Co

s7 c7

XMSB

Figure 3. Modified parallel prefix structure [34]

4. SYNTHESIS RESULTS AND COMPARISON

This section describes a comparison between a proposed circuit and the existing circuits of the sign
detector for the same moduli set. The comparison is based on two analyses: approximate and exact analysis.
The approximate analysis is performed using the unit gate model (UGM) [4]. In this model, two-input digital
logic gates (AND, OR, NAND, NOR) are assumed with the delay and area of one unit. The exclusive gates
(XOR, XNOR) require the delay and area of two units, whereas the area and delay of NOT gate are counted
as zero. Using UGM, the approximate delay and area of all the considered designs are compared in Figure 4
and Figure 5, respectively. These two figures itself show that the proposed circuit requires the lowest area
and comparable delay as compared to the already available sign detector [30-33] for the same moduli set.
For exact result analysis and comparison, all the considered designs are verified in Xilinx ISE 8.2i
using Verilog HDL. For analysis of results, all the designs are synthesized using TSMC 90nm CMOS library
by keeping constant design constraints and environment condition, i.e., 25°C and 1.0V. The synthesis is done
using the design compiler of Synopsys tool (version L-2016.03) for n=4, 8, 12, 16, 24 and 32, which is used
to obtain the required area, delay and power. The area required for the designs is shown in Figure 6, time-
delay in Figure 7 and power dissipations is shown in Figure 8. These results show that the proposed design is
better when compared to other sign detector. The resulting figures itself dictate that the proposed design
requires lesser area upto 7%, 52% and 3% than [30, 32-33], respectively. It is faster upto 9%, 11% and 77%
than [30-32], respectively. It also consumes lesser power upto 22%, 13%, 63% and 1% than [30-33],
respectively. The power-delay product (PDP) and area-delay product (ADP) of these designs are shown in
Figure 9 and Figure 10, respectively. These figures show that the introduced design has the lowest PDP and
ADP as compared to others.

Figure 4. Delay of sign detectors based on UGM Figure 5. Area of sign detectors based on UGM

Design and Analysis of RNS-based Sign Detector for Moduli Set {2n, 2n-1, 2n+1} (Raj Kumar)
68  ISSN: 2502-4752

Figure 6. Synthesized area (μm2) of sign detectors Figure 7. Synthesized delay (ns) of sign detectors

Figure 8. Total power dissipation of sign detectors Figure 9. Power-delay product (PDP) of sign
detectors

Figure 10. Area-delay product (ADP) of sign detectors

5. CONCLUSION
In this paper, a new sign detector based on the MRC theorem for RNS {2n-1, 2n, 2n+1} is described.
Furthermore, the proposed design is validated using the numerical example and compared with the recent
sign detectors. All the considered designs are synthesized using the Synopsys tool; the synthesized result
states that the analyzed architecture requires lesser area and power dissipation than others. Also, it has the
lowest ADP and PDP that are the prime objectives for real-time processing in portable devices. The analysis
reveals that the proposed design saves upto 52% area, 77% delay and 63% power dissipation when compared
to the other sign detection circuit for the same moduli set. So, the described sign detector using RNS can give
better performance for high-speed and low power applications.

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Design and Analysis of RNS-based Sign Detector for Moduli Set {2n, 2n-1, 2n+1} (Raj Kumar)
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BIOGRAPHIES OF AUTHORS

Raj Kumar was born in Prayagraj, India. He received his B.Tech degree in Electronics and
Communication from GBTU, Lucknow, India in 2011 and M.Tech degree in Digital Systems
from MNNIT Allahabad, India in 2015. Currently he is pursuing Ph.D. degree in Electronics and
Communication Engineering at MNNIT Allahabad, India. His research interests are in Residue
number arithmetic and VLSI design.

Ram Awadh Mishra was born in Balia, India. He received the B.Tech. degree in Electronics
Engineering from Kamla Nehru Institute of Technology, Sultanpur, India in 1989, the M.S.
degree in Electronics and Control from Birla Institute of Technology and Science, Pilani, India in
1996 and the Ph.D. degree in Engineering from Jadavpur University, Kolkata, India in 2006. He
is currently an Professor in Electronics and Communication Engineering Department at Motilal
Nehru National Institute of Technology Allahabad, India. His area of research is on the subject of
Device Modeling, Residue Number System based Signal Processing and Low Power VLSI
Design. He has published various research papers in reputed journals and conferences.

Indonesian J Elec Eng & Comp Sci, Vol. 22, No. 1, April 2021 : 62 - 70