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Q.1 If the diode in the circuit shown below is ideal, the current ID will be

a. 0 mA
b. 0.5 mA
c. 1 mA
d. 2 mA

Attempt Correct Correct Ans. b

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Q.2
For the circuit shown below the value of is

a. –1
b. –2
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c. +1
d. +2

Attempt Correct Correct Ans. d

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Q.3 Consider two amplifiers A1 and A2 . The rise time for first stage is 0.3 ms and for
the second stage is 0.4 msec. If the two systems are connected in cascade form
with each other then the rise time of the combined system will be

a. 0.5 msec
b. 0.55 msec
c. 0.4 msec
d. 0.3 msec

Attempt Incorrect Your Ans. a Correct Ans. b

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Q.4 The transistor in the circuit shown below is biased to operate in

a. Active Region for V1 > V2 ; V1 , V2 < 0

b. Active Region for V1 < V2 ; V1 , V2 > 0

c. Saturation Region for V1 > V2 ; V1 , V2 > 0

d. Saturation Region for V1 < V2 ; V1 , V2 < 0

Attempt Incorrect Your Ans. c Correct Ans. b

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Q.5 Assume an amplifier with input resistance Rin and output resistance Rout . If it is

desired to increase the input resistance and decrease the output resistance, then
the type of negative feedback required is

a. Series ­ Series
b. Shunt ­ Series
c. Series ­ Shunt
d. Shunt ­ Shunt

Attempt Incorrect Your Ans. d Correct Ans. c

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Q.6 A CMOS inverter with a load capacitance ‘C ’ is biased at VDD = 5V. The inverter is

switched at a frequency of 100 kHz. If the power dissipation in CMOS invertor is

10 μW, then the load capacitance C is

a. 1 pF
b. 2 pF
c. 3 pF
d. 4 pF

Not Attempt Correct Ans. d

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Q.7 Consider the figure shown below.

If the closed loop gain of the circuit is Then the open loop gain of the

op­amp AOL will be (Assume the op­amp is ideal except finite open loop gain)

a. 1
b. 2
c. 3
d. 4

Attempt Correct Correct Ans. c

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Q.8 The feedback used in the circuit shown in figure can be classified as

a. shunt­series feedback
b. shunt­shunt feedback
c. series­shunt feedback

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d. series­series feedback

Attempt Correct Correct Ans. b

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Q.9 Cascading of two amplifiers results in (Assume no loading effect)

a. Reduction in overall gain and increase in overall bandwidth

b. Reduction in overall gain and reduction in overall bandwidth
c. Increase in overall gain and increase in overall bandwidth
d. Increase in overall gain and reduction in overall bandwidth

Attempt Correct Correct Ans. d

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Q.10 In the voltage regulator circuit with V ­ I characterstics of zener diode is shown in
the figure given below,

the power dissipation in the zener diode is

a. 0.5 Watts
b. 0 Watts
c. 0.17 Watts
d. Can’t be calculated

Attempt Correct Correct Ans. b

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Q.11 10 mV input to an amplifier gives 10 V output without feedback. With negative

feedback, 200 mV input is required to get the same output. The feedback factor
(β) is ______________ %.

Attempt Incorrect Your Ans. 0.9 Correct Ans. 1.90 (1.80 ­ 2.00)
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Q.12 Consider the tuned amplifier as shown in the figure below.

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The FET is biased at gm = 5 mA/V with rd = 20 kΩ. If the tank circuit is tuned to 1

MHz, then the gain of the circuit at the given input frequency is

___________.

Attempt Incorrect Your Ans. ­100 Correct Ans. ­50

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Q.13 Bandwidth of a 3­stage tuned amplifier with each stage having bandwidth of 10
MHz is __________ MHz.

Attempt Incorrect Your Ans. 1.65 Correct Ans. 5 (4.5 ­ 5.5)

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Q.14
A npn BJT has Cμ = 10–14 F, Cπ = 4 × 10–14 F and DC current gain β0 = 90. For the

transistor if the unity gain cut­off frequency is given as fT = 1.47 × 1010 Hz, then fβ

= _________ × 107 Hz.

Attempt Correct Correct Ans. 16.34 (16 ­ 17)

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Q.15 In the following circuit, transistor Q1 and Q2 has following parameter

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Value of V1 + V2 is ________ V

Attempt Incorrect Your Ans. 3 Correct Ans. 6 (5.8 ­ 6.2)

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Q.16 The power input to an amplifier is 2 μW and the output power of the amplifier is 20
m Watts. The power gain of the amplifier is ____________ dB.

Attempt Incorrect Your Ans. 10000 Correct Ans. 40

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Q.17 Consider the circuit shown in figure. If the β of the transistor is 30 and ICBO is 20

nA and the input voltage is + 5 V, the transistor would be operating in

a. saturation region
b. active region
c. breakdown region
d. cut­off region

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Attempt Correct Correct Ans. b

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Q.18 Consider the circuit shown below.

The two transistors T1 and T2 are identical. The value of β is

a. 15
b. 25
c. 35
d. 45

Attempt Correct Correct Ans. b

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Q.19 Consider the MOS transistor shown in the figure below. By assuming parameter

and current ID to be constant. Find the correct representation of

VGS versus graph.

a.

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b.

c.

d.

Attempt Correct Correct Ans. c

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Q.20 In the circuit shown below op­amp ideal. the total current supplied by 20 V voltage
supply is (Assume β of the transistor is to be very large).

a. 50 mA
b. 51 mA
c. 52 mA
d. 53 mA

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Attempt Correct Correct Ans. b

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Q.21 Consider the circuit shown in the figure below

Assume all the transistors are matched and VBE = 0.7 V. If β is very large, then

the value of Iout is

a. 1.4 mA
b. 0.7 A
c. 1 mA
d. 70 mA

Attempt Correct Correct Ans. c

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Q.22 The voltage gain of the circuit shown in the figure below is,

a.

b.

c.

d.

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Not Attempt Correct Ans. a

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Q.23 In the circuit shown below, assume β = 125. For all the transistors and VBE = 0.7 V

and assume the input current for transistor T3 to be negligible

The value of IC is equal to

1

a. 0.27 mA
b. 0.23 mA
c. 1.17 mA
d. 0.56 mA

Attempt Incorrect Your Ans. d Correct Ans. a

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Q.24 If the op­amp is ideal, then the below circuit represents

a. Low pass filter

b. High pass filter
c. Band pass filter
d. Band stop filter

Attempt Incorrect Your Ans. b Correct Ans. c

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Q.25 Find the value of C that yields an output pulse of 220 μs in the monostable circuit
shown below. Given R = 10 kΩ.

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a. 10 nF
b. 20 nF
c. 30 nF
d. 40 nF

Not Attempt Correct Ans. b

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Q.26 Consider the circuit shwon in the figure below,

the transfer characterstics of the circuit can be represented as (Assume the

diodes and the op­amp are ideal)

a.

b.

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c.

d.

Attempt Correct Correct Ans. a

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Q.27

Assume the transistors in the above circuit have high value of β and VBE = 0.5

Volts. The current I flowing through 3.5 kΩ resistance is __________ mA

Attempt Correct Correct Ans. 0.50 (0.45 ­ 0.55)

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Q.28 Consider the phase shift oscillator as shown in the figure below.

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If the frequency of oscillations of the circuit is 100 kHz, then the value of the
resistance R will be _____ kΩ.

Attempt Correct Correct Ans. 6.5 (6.0 ­ 7.0)

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Q.29 The gate to drain capacitance of a MOSFET is 2 pF. By assuming common source
voltage gain of “–20”, the input capacitance due to miller effect is ____________
pF.

Attempt Correct Correct Ans. 42

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Q.30 The transistor in the circuit shown below has VBE (Sat) = 0.8V, β = 100 and VCE (Sat)

= 0.2 V. The minimum value of RC for which the transistor remains in saturation is

___________ kΩ.

Attempt Correct Correct Ans. 4.67 (4.50 ­ 5.00)

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Q.31 For the circuit shown below, if V i (t) is the input voltage of the circuit, then the

value of output voltage i.e. V0 (t) at t = 16 msec is _________ volts.

(Assume the time constant RC >> T and the diode is ideal)

Attempt Incorrect Your Ans. 0 Correct Ans. 20 (19 ­ 21)

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Q.32
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Consider the circuit shown below

Both the transistors have parameters as follows VTN = 0.8 volts,

If width to length ratios of M1 and M2 are

The output voltage V0 is ___________ Volts.

Attempt Incorrect Your Ans. 4.2 Correct Ans. 2.5 (2.30 ­ 2.70)
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Q.33 The circuit shown below is a zener regulated dc power supply. The minimum
value of RL for which the output voltage remains constant is __________ kΩ.

Attempt Correct Correct Ans. 0.5 (0.45 ­ 0.55)

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