INDEX

S.NO. Name of Practical Date Sign.

1. Implementing Half Adder and Full Adder
usingBasic Gates.

2. Implementing Binary-to-Gray, Gray-to-

Binary code conversion.

3. Implementing 3-8 line Decoder and

implementing 4x1and 8x1
Multiplexer.

4. Verify the excitation table of various Flip-

Flop.

5. Design of an 8-bit input/output system with

four 8-bit internal register.

6. Design of an 8-bit arithmetic Logic Unit.

7. Design the data path of a computer

from its register transfer language
description.

8. Design the control unit of a

computer using either hardwiring
and microprogramming based on its
register.

9. Write an algorithm and program to

perform matrix multiplication of two
n*n matrix on the 2-D mesh SIMD
model,Hypercube SIMD model or
Multiprocessor system.

10. Study of scalability for Single-board ,

Multi–board, Multi-core,
Multiprocessor using Simulator.
 Introduction of Cedar Logic Simulator

1. Implementing HALF ADDER, FULL ADDER

using basic logic gates.
A half adder adds two single binary digits A and B. It produces
two outputs: the sum (S) of the two bits, and the carry (C) which
is produced when A and B are both 1.

Here's the truth table for a half adder:

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
And here's the logical expression for the outputs:
figure:- truth table of full adder
2) Gray to binary conversion :
1. The Most Significant Bit (MSB) of the binary code is always
equal to the MSB of the given binary number.
2. Other bits of the output binary code can be obtained by
checking gray code bit at that index. If current gray code bit is 0,
then copy previous binary code bit, else copy invert of previous
binary code bit.

There are four inputs and four outputs. The input variable are
defined as G3, G2, G1, G0 and the output variables are defined
as B3, B2, B1, B0. From the truth table, combinational circuit is
designed.The logical expressions are defined as :

G0 ⊕ G1 ⊕ G2 ⊕ G3 = B0

G1 ⊕ G2 ⊕ G3 = B1

G2 ⊕ G3 = B2

G3 = B3

Figure-3: Gray to Binary Code Converter Circuit

Figure-4: Gray to Binary Code Converter Truth Table
3. Implementing 3-8 line DECODER and
Implementing 4x1 and 8x1 MULTIPLEXERS.

Theory
Decoder

A slightly more complex decoder would be the n-to-2n type binary

decoders. These types of decoders are combinational circuits that
convert binary information from 'n' coded inputs to a maximum of 2n
unique outputs. In case the 'n' bit coded information has unused bit
combinations, the decoder may have less than 2n outputs. 2-to-4
decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.

The input to a decoder is parallel binary number and it is used to detect

the presence of a particular binary number at the input. The output
indicates presence or absence of specific number at the decoder input.

Let us suppose that a logic network has 2 inputs A and B. They will give
rise to 4 states A, A', B, B' . The truth table for this decoder is shown
below:
For any input combination only one of the outputs is low and all
others are high. The low value at the output represents the
state of the input.

Decoder expansion

Combine two or more small decoders with enable inputs to

form a larger decoder e.g. 3-to-8-line decoder constructed from
two 2-to-4-line decoders. Decoder with enable input can
function as demultiplexer.

3:8 decoder

It uses all AND gates, and therefore, the outputs are active-
high. For active- low outputs, NAND gates are used. It has 3
input lines and 8 output lines. It is also called as binary to octal
decoder it takes a 3-bit binary input code and activates one of
the 8(octal) outputs corresponding to that code. The truth table
is as follows:

3 to 8 Line Decoder and Truth Table

S0 S1 S2 E D0 D1 D2 D3 D4 D5 D6 D7
x x x 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 1
0 0 1 1 0 0 0 0 0 0 1 0
0 1 0 1 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 1 0 0 0
1 0 0 1 0 0 0 1 0 0 0 0
1 0 1 1 0 0 1 0 0 0 0 0
1 1 0 1 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0

4x1 Multiplexer
4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two
selection lines S0 & S1 and one output Y. The block diagram of
4x1 Multiplexer is shown in the following figure.One of these 4
inputs will be connected to the output based on the
combination of inputs present at these two selection lines.
Truth table of 4x1 Multiplexer is shown below.

Figure-2:Block diagram of 4x1 Multiplexer

 Figure-3:Truth table of 4x1 Multiplexer

8×1 multiplexer circuit

Multiplexer or Data Selector is a very widely used combinational

circuit. It has multiple inputs and one output. It accepts several
data inputs and allows only one of them at a time to get
through to the output. The routing of the desired input to the
output is controlled by the select lines. M select lines can select
one of the 2M input channels.

Circuit Diagram of 8x1 Mux

Truth Table

4.
4. Verify the excitation tables of various FLIP-FLOPS.

Introduction

A flip flop is an electronic circuit with two stable states that can be used
to store binary data. The stored data can be changed by applying varying
inputs. Flip-flops and latches are fundamental building blocks of digital
electronics systems used in computers, communications, and many
other types of systems.

1.R-S flip flop

2.D flip flop
3.J-K flip flop
4. T flip flop

1) RS flip flop

The basic NAND gate RS flip flop circuit is used to store the data and thus
provides feedback from both of its outputs again back to its inputs. The
RS flip flop actually has three inputs, SET, RESET and clock pulse.
 Figure-3:Circuit diagram of D flip flop

Figure-4:Characteristics table of D flip flop

3) J-K flip flop

In a RS flip-flop the input R=S=1 leads to an indeterminate
output. The RS flip-flop circuit may be re-joined if both inputs
are 1 than also the outputs are complement of each other as
shown in characteristics table below.
 Figure-
5:Circuit
diagram of J-K flip flop

Figure-6:Characteristics table of J-K flip flop

4) T flip flop
T flip-flop is known as toggle flip-flop. The T flip-flop is
modification of the J-K flip-flop. Both the JK inputs of the JK flip –
flop are held at logic 1 and the clock signal continuous to
change as shown in table below.
 Figure-7:Circuit diagram of T flip flop

Figure-8:Characteristics table of T flip flop

5. Design of an 8-bit Input/ Output system with
four 8-bit Internal Registers
Aim: Design and implement 8-bit Input/Output System with four 8-bit internal registers

Equipment’s & Components Required:

S.No. Equipments Specification Quantity

1 Logic Simulator - 1

S.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 15
Theory:

A register is capable of shifting its binary information in one or both directions is known
as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded
with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest
possible shift register is one that uses only flip flop. The output of a given flip flop is
connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position
to right.
LOGIC DIAGRAM:
8-bit Input/Output System with four 8-bit internal register

Procedure:

• Connections are given as per circuit diagram.

• Logical inputs are given as per circuit diagram.
• Observe the output and verify the truth table.
Result & Conclusion: Verified 8-bit Input/Output System with four 8-bit internal registers on
simulator.
6. Design of an 8-bit ARITHMETIC LOGIC UNIT.
Aim: Design of an 8- bit ARITHMETIC LOGIC UNIT.

Equipment’s & Components Required:

S.No. Equipments Specification Quantity

1 Logic Simulator - 1

Theory:

ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like and, or, xor, nand, nor etc. A
simple block diagram of a 4 bit ALU for operations and, or, xor and Add is shown in
the
Logic diagram.
LOGIC DIAGRAM:
Block diagram of a 4 bit ALU
Design Issues :
The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S1
and S0 the circuit operates as follows:

for Control signal S1 = 0 , S0 = 0, the output is A And

B, for Control signal S1 = 0 , S0 = 1, the output is A
Or B, for Control signal S1 = 1 , S0 = 0, the output is
A Xor B.
 7. Design the data path of a computer from its
register transfer language description.
In symbolic notation, it is used to describe the micro-operations
transfer among registers. It is a kind of intermediate representation
(IR) that is very close to assembly language, such as that which is used
in a compiler.The term “Register Transfer” can perform micro-
operations and transfer the result of operation to the same or other
register.

Micro-operations :
The operation executed on the data store in registers are called micro-
operations. They are detailed low-level instructions used in some designs
to implement complex machine instructions.
Register Transfer :
The information transformed from one register to another register is
represented in symbolic form by replacement operator is called Register
Transfer.
Replacement Operator :
In the statement, R2 <- R1, <- acts as a replacement operator. This
statement defines the transfer of content of register R1 into register R2.
 Symbol Description Example

Letters and MAR,

Denotes a Register
Numbers R1, R2

R1(8-bit)
() Denotes a part of register
R1(0-7)

<- Denotes a transfer of information R2 <- R1

Specify two micro-operations of Register R1 <- R2

,
Transfer R2 <- R1

P : R2 <-
: Denotes conditional operations R1
if P=1

Naming Denotes another name for an already

Ra := R1
Operator (:=) existing register/alias

A digital system is an interconnection of digital hardware module

that accomplish a specific information-processing task.

• Digital system design invariably use a modular approach. The

modules are constructed from such digital components as
registers, decoders, arithmetic elements and control logic.

• Digital modules are best defined by the registers they contain

and the operations that are performed on the data stored in
them.
• The operations on data stored in registers are called micro-
operations. A microoperation is an elementary operation
performed on the information stored in one or more registers.

• The result of the operation may replace the previous binary

information of a register or may be transferred to another
register.

• Examples of microoperations introduced are shift, count, clear,

and load.

• Registers implement micro-operations a counter with parallel

load is capable of performing the micro-operations increment
and load. A bidirectional shift register is capable of performing
the shift right and shift left microoperations.

• The internal hardware organization of a digital computer is

best defined by specifying:

1. The set of registers it contains and their function.

2. The sequence of microoperations performed on the

binary information stored in the registers.

3. The control that initiates the sequence of

microoperations.
• It is more convenient to adopt a suitable symbology to
describe the sequence of transfers between registers and the
various arithmetic and logic microoperations associated with the
transfers.

• The symbolic notation used to describe the microoperation

transfers among registers is called a register transfer language.
The term "register transfer" implies the availability of hardware
logic circuits that can perform a stated microoperation and
transfer the result of the operation to the same or another
register.

• A register transfer language is a system for expressing in

symbolic form the microoperation sequences among the
registers of a digital module.

• It is a convenient tool for describing the internal organization

of digital computers in concise and precise manner. It can also be
used to facilitate the design process of digital systems.
8. Design the control unit of a computer using either
hardwiring or microprogramming based on its
register
transfer language description.
Introduction : In computer architecture, the control unit is responsible
for directing the flow of data and instructions within the CPU. There are
two main approaches to implementing a control unit: hardwired and
micro-programmed. A hardwired control unit is a control unit that uses a
fixed set of logic gates and circuits to execute instructions. The control
signals for each instruction are hardwired into the control unit, so the
control unit has a dedicated circuit for each possible instruction.
Hardwired control units are simple and fast, but they can be inflexible
and difficult to modify. On the other hand, a micro-programmed control
unit is a control unit that uses a microcode to execute instructions. The
microcode is a set of instructions that can be modified or updated,
allowing for greater flexibility and ease of modification. The control
signals for each instruction are generated by a microprogram that is
stored in memory, rather than being hardwired into the control unit.
micro-programmed control units are slower than hardwired control units
because they require an extra step of decoding the microcode to generate
control signals, but they are more flexible and easier to modify. They are
The control hardware can be viewed as a state machine that changes
from one state to another in every clock cycle, depending on the contents
of the instruction register, the condition codes, and the external inputs.
The outputs of the state machine are the control signals. The sequence of
the operation carried out by this machine is determined by the wiring of
the logic elements and hence named “hardwired”. Fixed logic circuits
Micro-program: A sequence of micro-instructions is called a micro-
program, which is stored in a ROM or RAM called a Control Memory
(CM). Control Store: the micro-routines for all instructions in the
instruction set of a computer are stored in a special memory called the
Control Store.
9. Write an algorithm and program to perform
matrix multiplication of two n * n matrices on the 2-
D mesh
SIMD model, Hypercube SIMD Model or
multiprocessor system.
Aim: To write an algorithm and program to perform matrix multiplication of two n * n
matrices on the 2-D mesh SIMD model, Hypercube SIMD Model or multiprocessor
system.

Theory:
Mesh Network: A set of nodes arranged in the form of a p dimensional lattice is called a mesh
network. In a mesh network only neighboring nodes can communicate with each other.
Therefore, interior nodes can communicate with 2p other nodes.

ALGORITHM:

Algorithm
Procedure MATRIXMULT
begin
for k = 1 to n-1 step 1do
begin
for all Pi,j where i and j ranges from 1 to n do
if i is greater than k then
rotate a in the east direction
end if
if j is greater than k then
rotate b in the south direction
end if
end
 for all Pi,j where i and j lies between 1 and n do
compute the product of a and b and store it in c
for k= 1 to n-1 step 1 do

for all Pi,j where i and j ranges from 1 to n do rotate a in the east rotate b in the south c=c+aXb
end

HYPERCUBE ALGORITHM

Result & Conclusion:-

Design an algorithm and program to perform matrix multiplication of two n*n
matrices on the 2D – mesh SIMD model, hypercube SIMD model or
multiprocessor system.
10. Study of Scalability for Single board Multi-board,
multi-core, multiprocessor using Simulator.
Aim: To study the Scalability for Single board, Multi-board, multi-core, multiprocessor
using Simulator

Equipments & Components Required:

SL.No. Equipments Specification Quantity

Logic Simulator - 1

Theory:

A multi-core processor is a single computing component with two or more

independent processing units called cores, which read and execute program instructions. The
instructions are ordinary CPU instructions (such as add, move data, and branch) but the single
processor can run multiple instructions on separate cores at the same time, increasing overall
speed for programs amenable to parallel computing. Manufacturers typically integrate
the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP)
or onto
multiple dies in a single chip package.
Diagram of a generic dual-core processor with
CPU-local :-

A
 i. SISD = Single Instruction Single Data
ii. SIMD = Single Instruction Multiple Data ( Array Processors or Data Parallel
machines)
iii. MISD does not exist.
MIMD = Multiple Instruction Multiple Data Control

Procedure:
Study various case study related to multi processors.
Result & Conclusion: Study of case study of Multi processors.

Procedure:
Study various case study related to multi processors.
Result & Conclusion: Study of case study of Multi processors.