I3C Slave peripheral Programmer’s

Model and Arch

Background on I3C, Slave arch, and details on config

Revision history
Revision Date Description Author
1.04c 03/17/17 4/15/17 Spec should now be complete to match the Slave PK
6/29/17 use. Added some clarifications. Clarified some
more details on errors.
Added note on when EVENT status is signaled.
IBIOK and the like now IBIDIS.
Vendor ID and Time control freq/acc can be an
MMR now.
Added OFFLINE and DYNADDR optional use.
0.91d 11/21/16 Added DDRMATCH status and moved PK
CHANDLED and EVENT and EVDET.
Added TXFULL and RXEMPTY bits as well as
OWRITE error (over write). Clarify status raw bits
that are SDR only vs. HDR. S0/S1 handling.
0.9c 08/22/16 ERRWARN vs. error. CTRL bit to flush TB buff. PK
Now just WDATAB and WDATABE and
RDATAB. Removed END from DATACTRL.
Moved FLUSH to 0.
BAMATCH register field, FLUSHFB added.
Mistake in the offset of CONFIG in title.
0.8d 7/30/16 Added more status/interrupt causes. PK
Added CCC vs. CHANDLED. Fixed INTSTAT on
CHANDLED. Defined ID reg.
0.3 4/4/16 Updated with new regs and config info. PK
st
0.1 10/11/15 1 draft – requirements and arch PK

Contents
1. Introduction ............................................................................................................ 3
2. Master vs. Slave for I3C ........................................................................................ 3
2.1 Requirements for Master .........................................................................4
2.2 Requirements for Slave ...........................................................................4
2.3 I3C Slave acting as a normal I2C Slave on I3C buses ...........................4
2.4 Understanding Offline and Hot-Join for re-joining bus ............................4
3. Registers of Digital block...................................................................................... 5
3.1 CONFIG @ 0x004 – I3C Configuration register ......................................7
3.2 STATUS @ 0x008 – I3C Status register .................................................8
3.3 CTRL @ 0x00C – I3C Control register..................................................11
3.4 INTSET, INTCLR, INTMASKED @ 0x010, 0x014, 0x18 – Interrupt
enable control registers (if configured for Interrupts) ............................12
3.5 ERRWARN @ 0x01C – I3C Error and Waning register ........................14
3.6 DMACTRL @ 0x020 – DMA Control register (if configured for DMA)...15
3.7 DATACTRL @ 0x02C – Data control register (and FIFO if configured for
FIFO) .....................................................................................................16
3.8 WDATAB @ 0x030 – Write Byte Data (to-bus) register ........................17
3.9 WDATABE @ 0x034 – Write Byte Data as End (to-bus) register .........17
3.1 MWDATAH @ 0x038 – Write Half-word Data (to-bus) register ............18
3.2 MWDATAHE @ 0x03C – Write Half-word Data as End (to-bus)
register ..................................................................................................18
3.3 RDATAB @ 0x040 – Read Byte Data (from-bus) register ....................18
3.1 RDATAH @ 0x048 – Read Half-word Data (from-bus) register ............19
3.1 CAPABILITIES @ 0x060 – Dynamic Address register .........................19
3.2 DYNADDR @ 0x064 – Dynamic Address register ................................21
3.1 MAXLIMITS @ 0x068 – Maximum limits set by I3C Master (if configured
for Limits) ..............................................................................................21
3.1 PARTNO @ 0x06C – Register to allow Application to set I3C Part
number ID (if configured for Part-number from app) .............................21
3.1 IDEXT @ 0x070 – Register to allow Application to set I3C ID
components (if configured for ID parts from app)..................................22
3.1 VENDORID @ 0x074 – Register to allow Application to set I3C Vendor
ID (if configured for VID from app) ........................................................22
3.1 TCCLOCK @ 0x078 – Register to allow Application to indicate
Frequency and accuracy of time-control clock (if enabled) ...................22
3.1 ID @ 0xFFC – Optional BlockID ...........................................................23
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1. Introduction
MIPI I3C is a follow on to i2c which has major improvements in use and power, as well as providing an
alternative to SPI for mid-speed. In particular:
• 2 wire multi-drop bus capable of 12MHz clock speeds with up to 11 devices
o While using standard pads (vs. i2c special pads) with 4mA drive
o Slave addresses are dynamically assigned – does not require a static address
§ But, slaves may have a static address at start
o Slaves may use inbound clock as the peripheral clock
§ So devices may have slow/inaccurate clocks internally
o For read from Slave, Slave normally ends the read, but Master may terminate
§ Unlike i2c and SPI with the problems of Master having to “know” length
• In-Band interrupts, allowing Slaves to notify Master
o Can be both equivalent to a separate GPIO, but can also be directly data bearing
o Prioritized so that if multiple Slaves wish to interrupt at the same time, the order is resolved
§ Dynamic addresses used for this, so priority controlled by Master
o Interrupts can be started even when Master is not active on the bus, and yet no free running
clock needed
o Time-stamping option to allow resolution of initial event vs. when interrupt gets through
• Built-in Commands in separate “space” to not collide with normal Master->Slave messages
o Controls bus behavior, modes and states, low power state, enquiries, etc.
o Has additional room for new built-in commands to be used by other groups
• Organized forms of multi-master:
o Slave which can request Master to allow it to message another Slave, yet not needing to
generate its own clock – called Peer-to-Peer
o Secondary Masters which can use clean handoffs between each Master
• Hot-join onto bus allows devices to come on-line later than initial bus bringup
o May be due to late wake up (power up) or physical insertion
o Provides clean method for notification.
• Mixed i2c and i3c capable
o I3C has support for certain legacy i2c devices on the bus
o I3C Slave devices capable of operating on i2c buses
o Also support for bridging (to i2c, SPI, UART, etc.)
• High data rate modes also optionally available
o Only Master and the specific Slave has to support – other Slaves know how to ignore
o Has an HDR-DDR form which is about 2x the data rate of SDR (so about 20Mbps)
o Has an HDR-TSP (ternary symbols) which are up to 3x the data rate (so about 30Mbps)
• Slaves as small as <2K gates.
o Allowing for fully state machine driven as well as using processor
• Masters as small as 2.5K gates
o Relies on processor to handle

The I3C peripheral supports the full feature set, but uses parameterization to allow reduction of the logic to
what is needed.

2. Master vs. Slave for I3C

The I3C peripheral contains both a Master and Slave component, and can be parameterized to be only one or
the other or both. However, if Master, the peripheral should generally support Slave mode to facilitate master
handoff. This spec covers only the Slave component. The Master spec covers the Master with the
understanding that Master+Slave would be integrated in that use.

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2.1 Requirements for Master

Master mode is expected to be backed up by full software to support the various requirements of the Master
(including as Secondary Master):
• Special handling of ENTDAA – assign dynamic addresses to each slave. This is a process. It is
supported by the peripheral, but requires the Software to make choices.
• Building up a table of Slaves, including their capabilities. This is used to control what kinds of actions
and commands may be sent to them.
• Handling requests such as In-band interrupt, Peer-to-peer slave, and Master request (handoff).
• Adjusting clock speed or write-to-read timing to match the slave’s limitations. This can be done in HW
in terms of dividers and uneven duty cycle, but the SW needs to make the decisions.
• Adjusting max data length.
• Being a slave after a Master handoff to another Master
Additionally, Master needs 3 pins normally, unless a very precise high strength pullup is included in the SDA
pad. The 3 pin model allows one pad/pin to enable a system-provided pullup which is sized to the needs of the
system.
The Master needs a reasonably accurate clock, normally capable of a frequency which is a multiple of
between 11MHz and 12.5MHz. For example, 24MHz, 48MHz, 25MHz, 50MHz, 33MHz, and 66MHz are all
typical speeds. Higher ratios are also quite usable.

2.2 Requirements for Slave

The I3C Slave mode is intended to allow a much simpler model. Further, the block is designed to allow the
implementation to parameterize many aspects when space is a concern. So, the slave minimum requirements
are very small (just I3C SDR mode and a few CCC commands). But, the slave can be scaled up quite a bit in
terms of functionality, which can actually save area over software 4ost. What is important is that the Slave can
be scaled in many cases by handling more in software or by handling in hardware. This decision is made in
the build of the block.

2.3 I3C Slave acting as a normal I2C Slave on I3C buses

st
The I3C Slave, if assigned an i2c Static Address, will act as a normal I2C device when it 1 comes up. If
placed on an i2c bus with an i2c Master, it will simply stay in i2c mode and operate normally. The SW knows
this is the case because (a) there has not been a DACHG indicating a Dynamic address was assigned, and
(b) the DYNADDR register contains 0x0.
If full i2c support for Fm and Fm+ is desired, the pads should also support a 50ns Spike filter, which must be
turned off when the I3C 7’h7E broadcast address is seen (indicating an I3C Master); that turning off of the
Spike filters could be done by HW using the raw net indicating that address was seen (see uarch spec for
details), or it could be handled by software. Note that a 50ns Spike filter is not needed to operate on an i2c
bus, so this is not a requirement of the peripheral in any way.

2.4 Understanding Offline and Hot-Join for re-joining bus

Hot-join is normally thought of as being used for Hot-insertion type uses, but it may also be used when the
Slave may be powered or hard reset such that it needs to rejoin the I3C bus and will need a new Dynamic
Address (DA).
The Slave provides 3 mechanisms for different cases of rejoining:
1. If DA is lost, Hot-Join is used.
2. If DA is retained in the peripheral (e.g. with SRFFs) then the CONFIG.OFFLINE bit will be used (see
below).

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3. If DA is retained in separate always-on memory, then the DYNADDR register as writable mechanism
may be used along with the CONFIG.OFFLINE bit.
The OFFLINE bit of the CONFIG register may be set when SLVENA is set to 1. This will cause the peripheral
to safely rejoin the bus. It does this by ensuring the I3C bus is not in HDR mode, using the same approach as
st
S0/S1 exit does: wait for 1 of HDR Exit Pattern, or 60µs of SCL and SDA unchanging.
Note that after using OFFLINE, the peripheral still cannot safely use IBI until it sees a STOP (which ensures
that the next START is safe to use for IBI).
st
If the App needs to do an IBI right away, it should wait for the 1 of STOP (see STATUS), or 200µs of SCL
and SDA being High. This can be done using the STATUS and INTSET controls. If the STATUS indicates the
bus is not busy and the peripheral will interrupt on START or STOP, then use of a timer to measure 200µs can
be used. If the timer goes off with no START or STOP, then it is safe to use IBI. If a START causes an
interrupt, the timer should be turned off and STOP waited for. If STOP causes an interrupt, it is safe to use IBI.

3. Registers of Digital block

The I3C block uses parameterization by the system when instantiating, so the peripheral necessarily has
registers and fields which may be available or removed depending. To help clarify this, a RO register is used
to indicate the blocks capabilities. Additionally, the table below shows what is affected on a broad basis.

Offset Type Name Description Configuration?

0x000 RW reserved Reserved for Master. -

0x004 RW CONFIG Configuration fields for things FIELDS: Choices in build

setup before block is activated affect fields of these registers

0x008 RO STATUS Status for Master and Slave. Not

all bits used if only Slave. This
document only explains the slave
bits.

0x00C RW CTRL Control for active use – in

particular event generation (e.g.
interrupts to the Master)

0x010 R/W1S INTSET Interrupt enable REG and/or FIELDS: Choices

may remove the registers or
0x014 W1C INTCLR Interrupt disable impact which interrupts are
used.
0x018 RO INTMASKED Mask of sourced interrupts
(STATUS & INTSET)

0x01C RW ERRWARN Error and Warning state from Always available

protocol errors and issues.
Related to ERRWARN status and
interrupt.

0x020 RW DMACTRL DMA control register, if DMA is Only if DMA selected.

enabled in the block.

0x02C RW DATACTRL Allows control of data buffering FIFO Fields only if FIFO
and indicates current buffer state. enabled.

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Offset Type Name Description Configuration?

If FIFO enabled, this is also the
FIFO control.

0x030 WO WDATAB Write a byte of data, including use Available unless external
th
of a 9 bit to mark as end (last FIFO
byte)

0x034 WO WDATABE Write a byte of data, which is end

(last byte).

0x038 WO WDATAH Write a half-word of data,

th
including use of a 16 bit to mark
as end (last byte of half-word is
end).

0x03C WO WDATAHE Write a half-word of data, which is

end (last byte of half-word is end).

0x040 RO RDATAB Read a byte of data

0x048 RO RDATAH Read a half-word of data

0x060 RO CAPABILITIES Indicates what is Always used – indicates how

available/supported in this block, block is configured by HW
including Master and/or Slave,
HDR modes, etc.

0x064 RO DYNADDR Dynamic address once assigned, Always used.

else 0.

0x068 RO MAXLIMITS Indicates the limits set by the If enabled to track this.
Master (or the original requested
limits).

0x06C RW IDPARTNO Allows application to write the ID Only available if configured by

part-number if configured to ID48B.
provide by register

0x070 RW IDEXT Allows application to write the ID Separate configuration for

extension of DCR and/or BCR each field.
and/or instance if so configured.

0x074 RW VENDORID Allows application to write the If ID is completely from

Vendor ID if so configured. MMRs/Nets and not constant.

0x078 RW TCCLOCK Allows application to set Time If time-control is enabled and

control clock and accuracy info the register form is used (vs.
dynamically. constant).

0xFFC RO ID Block ID and revision. Controlled by parameter and

could be 0.

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3.1 CONFIG @ 0x004 – I3C Configuration register

The I3C configuration register allows for configuration before enabling the bus.

Bit(s) Type Name Description Config

0 RW SLVENA If 1, allows the Slave to operate on the Always available.

i2c or I3C bus. If 0, the Slave will ignore
the bus. This should not be set until
registers such as this one, PARTNO,
st
IDEXT, and the like are set 1 – if used –
since they impact data to the Master.
This is normally only setup once before
bus comes up. If used at other times,
see Hot-Join; in the case of Hot-Join,
that should be set before this, so the
device does not see a START or STOP
incorrectly.

1 RW NACK If 1, the Slave will NACK all requests to it

except CCC broadcast. This should be
used with caution as the Master may
determine the slave is missing if
overused.

2 RW MATCHSS If 1, the START and STOP sticky

STATUS bits will only be set if
MATCHED is set. This allows START
and STOP to be used to detect end of a
message to/from this Slave.

3 RW S0IGNORE If 1, the Slave will not detect S0 or S1

errors and so not lock up waiting on an
Exit Pattern. This should only be used
when the bus will not use HDR.

4 RW DDROK If 1, allow HDR-DDR messaging if Ignored if the corresponding HDR

available by setting the corresponding is not enabled. Also ignored if the
BCR bit to say HDR is available, and the BCR[5] bit is hard set to 1 by
corresponding HDRCAP HDR-DDR bit parameter (constant) or is 1 in the
and permitting use. IDEXT.BCR register field.

5 RW TSPOK If 1, allow HDR-TSP messaging if

available. This will not respond to a TSP
request if not set.

6 RW TSLOK If 1, allow HDR-TSL messaging if

available. This is separate from TSP
because it requires a clock in a special
range (for Spike filters). This will not
respond to a TSP request if not set.

8 RW IDRAND If 1, PARTNO is a random value. If 0 (or Only if enabled for in the block
not configured for), PARTNO is a part along with PARTNO register.
number and instance.

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9 RW OFFLINE If 1 when SLVENA set to 1, will wait for Only possible if CLK_SLOW is
either 60us of bus quiet or HDR Exit used, so only if IBI or MR or HJ.
Pattern; this ensures that bus is not in
HDR mode and so can safely track SDR.

23:16 RW BAMATCH Bus Available condition match value for Only if enabled for events such as
current “Slow clock”. This provides the IBI or MR or HJ, and if enabled to
count of the slow clock to count out 1us provide this as a register.
(or more) to allow an IBI to drive SDA
Width is limited to
Low when the Master is not doing so. CLK_SLOW_BITS
The max width, and so max value, is
controlled by the block.

31:25 RW SADDR If allowed by the block: Sets i2c 7 bit If enabled to use one and to be
Static address, else should be 0. provided by SW. Block may
provided in HW as well.

3.2 STATUS @ 0x008 – I3C Status register

The Status register is used to indicate both sticky status for interrupts as well as “states” and “modes” related
to the i3c bus. The fields are divided into current activity, interrupt maskable actions, then states and modes
on the bus.

Bit(s) Type Name Description Config

Activity status

0 RO STNOTSTOP Is 1 if bus is busy (activity) and 0 when in a STOP

condition. Other bits below may also be set when busy.
Note that this can also be true from an S0 or S1 error,
which waits for an Exit Pattern.

1 RO STMSG Is 1 if this bus Slave is listening to the bus traffic or Will include
responding. If STNOSTOP=1, then this will be 0 when a unhandled
non-matching address seen until next repeated START or CCCs
STOP.

2 RO STCCCH Is 1 if a CCC message is being handled automatically. Which

CCCs
handled is
configured.

3 RO STREQRD Is 1 if the REQ in process is an SDR Read from this Slave

or an IBI is being pushed out. See STHDR for DDR
handling.

4 RO STREQWR Is 1 if the REQ in process is SDR write data from the

Master to this bus Slave or all i3c Slaves, but not ENTDAA
mode. See STHDR for DDR handling.

5 RO STDAA Is 1 if in ENTDAA mode whether this bus Slave has a

Dynamic Address or not.

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6 RO STHDR Is 1 if in HDR-DDR, HDR-TSP, or HDR-TSL; is 1 whether

the HDR mode is supported by this block or not, and
whether the message is to this block or not.

Interrupt maskable actions. Write 1 to clear/acknowledge

8 R/W1C START Set to 1 if a START or repeated START seen since last

cleared. This is not usually needed, but can be used for
wake events.

9 R/W1C MATCHED An incoming header matched this device’s I3C Dynamic or

I2C Static address (if any) since last cleared.

10 R/W1C STOP A STOP state was present on the bus since last cleared.
The STNOTSTOP state will also indicate if in stop.
Note: A fast STOP/START combination may not trigger this
status. START will always be set in that case. This bit is
from a stopped state being detected.

11 RO RX PEND Receiving a message from Master, which is not being See also
handled by block (not a CCC internally processed). FIFO status
For all but External FIFO, this uses DATACTRL RXTRIG, in
which defaults to not-empty. DATACRTL
If DMA is enabled for RX, DMA will be signaled as well. if FIFO is
Will self-clear if data is read (FIFO and non-FIFO). available

12 RO TXNOTFULL Is 1 when the To-bus buffer/FIFO can accept more data to

go out. Default: 1.
For all but External FIFO, this uses DATACTRL TXTRIG,
which defaults to not-full.
If DMA is enabled for TX, it will also be signaled to provide
more data.

13 R/W1C DACHG The Slave Dynamic Address has been assigned, re-
assigned, or reset (lost) and is now in that state of being
valid or none.

14 R/W1C CCC A Common-Command-Code (CCC), not handled by block, For CCCs

has been received. This acts differently between: that the
block is not
§ Broadcasted ones, which will then also
st enabled to
correspond with RXPEND and the 1 byte will be
process.
the CCC (command).
§ Direct ones, which may never be directed to this
device. If it is, then the TXSEND or RXPEND will
be triggered with this and the RXPEND will
contain the command.

15 RO ERRWARN An error or warning has occurred, such as data underun, Some

data overrun, parity error, HDR-DDR CRC error, or other errors only
error or warning condition. See the ERRWARN register for possible if
details of the cause. Write to the ERRWARN register to configured
clear. features.

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16 R/W1C HDRMATCH An HDR command matched this device’s I3C Dynamic Only if HDR
st
Address. The Command will be available as the 1 byte is
and RXPEND will be set, whether read or write. The MSb supported.
of that command byte also indicates if a read or a write.
If a read, and there are to-bus bytes waiting, the command
will be ACKed and the data sent back, else it will be
NACKed.
Note that when this is set, the ERRWARN bit should be
checked, as the HPAR error may have be encountered
after signaling this (the parity is after the destination
address and CMD).

17 R/W1C CHANDLED A Common-Command-Code (CCC) is being handled by For CCCs

the block. This is a notification only. The result may be an that the
updated register. block is
enabled to
process.

18 R/W1C EVENT Slave: Pending IBI, P2P, MR, or Hot-Join has been sent as Only if
requested. See upper status for details. configured
Note that for IBI, this occurs on the ACK if no IBI byte, and to support
after the 1 IBIDATA byte has been sent. So, if time control events.
is used, those will go out after this EVENT is signaled.

19 - - Reserved for Master use (gaining mastership)

21:20 RO EVDET Current details of last (EVENT=1) or pending event: Only if

configured
0 None to support
events.
1 Request not sent yet. Either no START yet, or
waiting for Bus-Available or Bus-Idle (HJ).

2 Request sent and NACKed – will try again

3 Request sent and ACKed, so Done (unless time

control data being sent still).

CCC States as known by the block (depending on what is enabled)

24 RO IBIDIS Is 1 if IBIs are disabled at this time. Note that CTRL Only if
requests will be held off while disabled. enabled for
block to
process.

25 RO MRDIS Is 1 if Master Requests are Disabled at this time. Note that Only if
CTRL requests will be held off while disabled. enabled for
block to
process.

26 RO reserved reserved Only if

enabled for
block to
process.

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27 RO HJDIS Is 1 if Hot-Join is disabled at this time. Note that CTRL Only if

requests will be held off while disabled. enabled for
block to
process.

29:28 RO ACTSTATE Activity state from CCC as: Only if

enabled for
Value Meaning block to
process.
0 No Latency – normal bus operations

1 1ms of latency

2 100ms of latency

3 10s of latency

31:30 RO TIMECTRL Indicates if time control is currently enabled: If Time

control is
Value Meaning enabled
0 No time control is enabled

1 Synchronous is enabled – if supported

2 Asynchronous standard mode (0 or 1) is

enabled – if supported

3 Both are enabled – if supported.

3.3 CTRL @ 0x00C – I3C Control register

The Control register is used to activate various special operations for the Slave, but only if the block is
configured to support. This includes events such as IBI, as well as GETSTATUS fields (except the Protocol
error, which is automatically set).

Bit(s) Type Name Description Config

1:0 RW EVENT If set to non-0, will request an event. Once requested, If block is
STATUS.EVENT and EVDET will show the status as it configured for
progresses. Once completed, the field will automatically one or more of
return to 0. Once non-0, only 0 can be written (to cancel) these.
until done. Time control is
separately
Value Meaning configured.
0 Normal mode. If set to 0 after was a non-0
value, will cancel if not already in flight.

1 Start an IBI. This will try to push through an IBI

on the bus. If data associated with the IBI, it will
be drawn from the IBIDATA field.
Note that if Time control is enabled, this will
include any time control related bytes; further,
the IBIDATA byte will have bit 7 set to 1

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automatically (as is required for time control).

st
The interrupt will occur after the 1 (Mandatory)
IBIDATA, if any.

2 Start Master-Request or Peer-to-Peer request:

the meaning depending on BCR register
configured in the block.

3 Start Hot-Join request. This should only be

used when device is powered on after bus is
already up, or is connected by hot insertion.
Will wait for Bus Idle. This must be set before
the Enable in the CONFIG.

15:8 RW IBIDATA Data byte to go with an IBI, if enabled for it. If enabled If block is
(was in BCR), then it is required. configured for
IBI data.

19:16 RW PENDINT Should be set to the pending interrupt that GETSTATUS Controlled with
CCC will return. This should be maintained by the the CCC
Application if used and configured, as the Master will read handling
this. parameter.
If not configured, the GETSTATUS field will return 1 if an
IBI is pending, and 0 otherwise.

21:20 RW ACTSTATE Should be set to the Slave’s activity state that

GETSTATUS CCC will return as Activity Mode. This
should be maintained by the Application if used and
configured, as the Master will read this.
If not configured, the GETSTATUS field will always return
a 0.

31:24 RW VENDINFO Should be set to the Vendor Reserved field that Controlled with
GETSTATUS CCC will return. This should be maintained the CCC
by the Application if used and configured, as the Master handling
will read this. parameter.
If not configured, the GETSTATUS field will always return
a 0.

3.4 INTSET, INTCLR, INTMASKED @ 0x010, 0x014, 0x18 – Interrupt enable control
registers (if configured for Interrupts)
The Interrupt registers, if enabled in the block, allow masking interrupt sources as well as checking which have
activated. The normal method is to Enable an interrupt and then once it fires, it is either cleared by writing the
STATUS register or cleared by action on the corresponding data register. The Interrupt is level held, meaning
it stays set until the cause is cleared one way or the other. The block prevents races so that if a new event
comes in, it will not be lost.
The table below shows all 3 registers, with the Type indicating INTSET (R/W1S), INTCLR (WO), and
INTMASKED (RO, is STATUS&INTSET).

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INTSET allows setting enables for interrupts (connecting the corresponding STATUS source to causing an
IRQ to the processor).
INTCLR allows clearing interrupt enables without read-modify-write problems.
INTMASKED allows checking status bits in terms of which are holding the IRQ, if any.

Bit(s) Type Name Description Config

8 R/W1S, START Interrupt on START and repeated START when

W1C, needed (such as wakeup). See also STOP.
and RO

9 R/W1S, MATCHED Interrupt on Matching header for I3C Dynamic Static

W1C, Address. Also for matching header for I2C Static Addr
and RO Address, if configured and if no Dynamic Address match
set (see DYNADDR register). only if
configured

10 R/W1S, STOP Interrupt on STOP state on the bus. See START as

W1C, the preferred interrupt when needed. This interrupt
and RO may not trigger for quick STOP/START combination,
as it relates to the state of being stopped.

11 R/W1S, RX PEND Interrupt when Receiving a message from Master, FIFO and
W1C, which is not being handled by block (excludes CCCs DMA use
and RO being handled automatically). only if
If FIFO, then RX fullness trigger. configured
If DMA, then message end.
See also REQ in STATUS for context.

12 R/W1S, TXSEND Interrupt when Request data by Master (Read). This

st
W1C, interrupts on 1 request (header) as well as when
and RO ready for more; the Application indicates if more or
END.
If FIFO, triggers on TX emptiness trigger.
If DMA, then message end (DMA end or terminate).

13 R/W1S, DACHG Interrupt on Dynamic address defined (SETDASA or

W1C, ENTDAA) or lost (RSTDAA). See also DADDR
and RO register. This will not interrupt on SETNEWDA.

14 R/W1S, CCC For CCCs not handled by the block, RXPEND will For CCCs
W1C, also interrupt and the STATUS REQ field will that the
and RO indicate it is a CCC. block is
Note that the handling of broadcast vs. direct write not
vs. direct read are all subtly different. The direct enabled
read ones likely do not provide enough time to to
respond, but the i3c spec allows a single retry, process.
buying more time.

15 R/W1S, ERRWARN Interrupt when an error or warning has occurred, Some

W1C, such as data 13nderrun, data overrun, parity error, errors
and RO HDR-DDR CRC error, or other error or warning only
condition. See the ERRWARN register for details of possible if
the cause.

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configured
features.

16 R/W1S, DDRMATCHED Interrupt when DDR matched for Read or Write Only if
W1C, command. HDR
and RO enabled

17 R/W1S, CHANDLED Interrupt when a Command-Command-Code was For CCCs

W1C, received and handled by the block (is done). that the
and RO STATUS will show new results. block is
enabled
This can be used to track when Activity states and
masks on events (e.g. IBIs) occur. to
process.

18 R/W1S, EVENT Slave: Interrupt when Pending IBI, P2P, MR, or Hot- Only if
W1C, Join has been sent as requested. See STATUS for configured
and RO details (EVDET). to support
events.

3.5 ERRWARN @ 0x01C – I3C Error and Waning register

The ERRWARN register contains I3C protocol errors and issues detected on the line. This includes internal
issues such as overrun and underrun, as well as detected errors and condition such as parity errors, CRC
errors, and termination of a Read by the Master.

Bit(s) Type Name Description

General Errors and Warnings detected by slave engine

0 R/W1C ORUN The internal from-bus buffer/FIFO was overrun (too many chars coming in
and not drained by the app fast enough).

1 R/W1C URUN The internal to-bus buffer/FIFO was underrun during data read (app did
not provide the data fast enough). The END bit or register should be used
if that was the last one.

2 R/W1C URUNNACK The internal to-bus buffer/FIFO was underrun in the read header and so
the block NACKed the header.

3 R/W1C TERM The Master terminated a read from Slave when an END was not set (on
same or previous).

4 R/W1C INVSTART Invalid start with SCL falling while SDA=1 in STOP condition.

Errors in data integrity

8 R/W1C SPAR SDR Parity error on message from Master. This will also set the
GETSTATUS Protocol Error sticky bit (cleared on GETSTATUS read).
For Read, this will be set if a Read Abort (timeout) occurs due to Master
not driving clock for >100µs during an I3C SDR Read.

9 R/W1C HPAR HDR Parity error or framing error on message from Master. Note that the
corresponding CMD or Data that had the error will normally be in the RX
buffer (read via RDATAB).

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10 R/W1C HCRC HDR-DDR CRC error on message from Master. This calls into question
the data from the whole DDR command frame. Note that this includes an
HDR Restart or Exit being issued before an HDR-DDR message from
Master is complete.

11 R/W1C S0S1 S0 or S1 error has occurred and the Slave is locked waiting on an HDR
Exit Pattern. Writing 1 to this will cause it to release the lock, but that
should be used with great care. Normally, it will clear automatically when
an Exit Pattern is detected. So, writing 1 should only be used under
controlled circumstances to avoid problems. It will then wait for a START
(or repeated START) or STOP to operate normally.

Application errors (misuse)

16 R/W1C OREAD The RDATAB register was read for more bytes than were available by
app.

17 R/W1C OWRITE The WDATAB/BE register was written when FULL

3.6 DMACTRL @ 0x020 – DMA Control register (if configured for DMA)
The DMA Control register allows for DMA to be used for inbound messages and outbound messages. This is
only available if configured for it.
DMA is limited in value for Slave use. This is because the Slave has to be reactive to what happens. The two
common use models:
1. From-bus collection to avoid being overrun. The CONFIG MATCHSS bit is set, and then the processor
enables the interrupts for START, and STOP, as well as enabling the DMA to collect the data. The
START or STOP interrupt will only occur after a message directed to the Slave (MATCHED bit set),
and the DMA copied data can then be examined.
2. To-bus for larger reads. Since I3C and I2C reads are preceded by a write which indicates what will be
read (or in response to an IBI from the Slave), the DMA can be used to push through the data.
Note that for I3C, the last value needs to be handled by the processor unless the DMA moves wider
words to be able to set the END bit (i.e. 16-bit values when byte mode or 32-bit values when in half-
word)
Note that for I2C, the last value is determined by the Master, so the DMA may end early or may run
out and the Master still wants more.

Bit(s) Type Name Description Config

1:0 RW DMAFB DMA Read (From-bus) trigger. If enabled with 1 or 2, If configured for
will request DMA on RX trigger (see DATACTL). It DMA and not
will request until empty unless DMA setup as trigger. external FIFO.
Note: will cancel on ERRORWARN (since cannot be
as planned).

Value Meaning

0 DMA not used

1 DMA enabled for 1 Frame - auto clears on

STOP or repeated START (see
MATCHSS in CONFIG).

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2 DMA enabled until turned off.

3:2 RW DMATB DMA Write (To-bus) trigger. If enabled with 1 or 2,

will start request DMA on TX trigger (see DATACTL).
It will request until full unless DMA setup as trigger.
Note: will cancel on ERRORWARN (since cannot be
as planned).

Value Meaning

0 DMA not used

1 DMA enabled for 1 Frame (ended by

DMA or Terminated) - then auto-clears on
STOP or START (see MATCHSS in
CONFIG).

2 DMA enabled until turned off. Normally

should only be used with Master Message
mode.

5:4 RW DMAWIDTH Width of DMA operations, if configured to allow half-

word data access.

Value Meaning

0, 1 Byte

2 Half word (16b). If supported by

HW. This will make sure 2 bytes
free/available in FIFO.

3 reserved

3.7 DATACTRL @ 0x02C – Data control register (and FIFO if configured for FIFO)
The Data control register simply assists in data control when no FIFO, and assists in FIFO when the FIFO is
available (regardless of size). This allows some control over the FIFO behavior. In particular, it allows control
of when to interrupt on fullness/emptiness and also controls behavior related to width, when not 1 byte wide.

Bit(s) Type Name Description Config

0 WO FLUSHTB Flush the to-bus buffer/FIFO. Used

when Master terminates a to-bus
(read) message prematurely.

1 WO FLUSHFB Flushes the from-bus buffer/FIFO.

Not normally used.

3 WO UNLOCK If this bit is not written 1, the

register bits from 7 to 4 are not
changed on write.

5:4 RW TXTRIG Trigger level for TX emptiness If Internal FIFO enabled for to-bus, has
when FIFOed. Affects interrupt full meaning. If just 2 or 3 byte (ping
pong) buffer, then only 0 is special to

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and DMA (if enabled). The defaults mean “empty”. That is, 0 will cause
is 3 TXNOTFULL to be true only if TX FIFO
is empty, so Half word write can be
Value Meaning used; 1, 2, and 3 will set TXNOTFULL
when not full.
0 Trigger on empty

1 Trigger on ¼ full or less

2 Trigger on ½ full or less

3 Trigger on 1 less than

full or less. Default

7:6 RW RXTRIG Trigger level for RX fullness when If Internal FIFO available for from-bus,
FIFOed. Affects interrupt and DMA has full meaning. If just 2 or 3 byte (ping
(if enabled). pong) buffer, then only 3 is special to
mean at least 2 bytes in). That is, 3 will
Value Meaning set RXPEND only if 2 or 3 bytes are in
RX FIFO, so Half word read can be
0 Trigger on not empty
used; 0, 1, and 2 will set RXPEND if not
1 Trigger ¼ or more full empty.

2 Trigger ½ or more full

3 Trigger ¾ or more full

20:16 RO TXCOUNT Count of bytes in TX Always Available, but has less meaning
if external FIFO is used (since this will
28:24 RO RXCOUNT Count of bytes in RX be only of local buffers).
30 RO TXFULL Is 1 if TX is full

31 RO RXEMPTY Is 1 if RX is empty. Default 1.

3.8 WDATAB @ 0x030 – Write Byte Data (to-bus) register

This register allows writing a byte to the bus (to Master) unless external FIFO is used. This takes a byte and
an end-of-data (last) marker bit.
A byte should not be written unless there is room, as indicated by the TXNOTFULL bit being set in the
STATUS register.

Bit(s) Type Name Description Config

7:0 WO DATA Byte to send to master If not

external
8, 16 WO END If 1, this marks the last byte of the message. If 0, it is assumed FIFO
there are more bytes. This is required to be used in I3C and is
optional in i2c. Note that for HDR-DDR, the byte with the END
nd th th
must be an even (2 , 4 , 6 , etc) since DDR is byte-pairs.

3.9 WDATABE @ 0x034 – Write Byte Data as End (to-bus) register

Write a byte just like WDATAB, but mark as end-of-data (last byte). Note that for HDR-DDR, the byte with the
nd th th
END must be an even (2 , 4 , 6 , etc) since DDR is byte-pairs.

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A byte should not be written unless there is room, as indicated by the TXNOTFULL bit being set in the
STATUS register.

Bit(s) Type Name Description Config

7:0 WO DATA Byte to send to master If not external FIFO

3.1 MWDATAH @ 0x038 – Write Half-word Data (to-bus) register

This register allows writing a half-word (pair of bytes) to the bus unless external FIFO is used. This takes a
half-word, which will send out the Low byte and then the High byte. An end-of-data (last) marker bit is allowed
(or must be 0).
A half-word should not be written unless there is room for both, as indicated by use of TX FIFO level trigger or
TXCOUNT available space in the DATACTRL register.

Bit(s) Type Name Description Config

st
7:0 WO DATA0 1 Byte to send to Master If not external FIFO
nd
and if configured for
15:8 WO DATA1 2 Byte to send to Master half-word data

16 WO END If 1, this marks the last byte of the message. If 0, it is

assumed there are more bytes/half-words. For this
register, this always marks DATA1 as the end.
This is required to be used in I3C and is optional in
i2c. Note that for HDR-DDR, the byte with the END
nd th th
must be an even (2 , 4 , 6 , etc) since DDR is byte-
pairs.

3.2 MWDATAHE @ 0x03C – Write Half-word Data as End (to-bus) register

nd
Write a half-word (byte pair) just like MWDATAH, but mark the 2 bytes as end-of-data (last byte). Note that
nd th th
for HDR-DDR, the byte with the END must be an even (2 , 4 , 6 , etc) since DDR is byte-pairs.
A half-word should not be written unless there is room for both, as indicated by use of TX FIFO level trigger or
TXCOUNT available space in the DATACTRL register.

Bit(s) Type Name Description Config

st
7:0 WO DATA0 1 Byte to send to Master If not external FIFO and if configured for half-
nd
word data
15:8 WO DATA1 2 Byte to send to Master

3.3 RDATAB @ 0x040 – Read Byte Data (from-bus) register

This register allows reading a byte from the bus (Master) unless external FIFO is used.
A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the
STATUS register.

Bit(s) Type Name Description Config

7:0 RO DATA0 Byte read from Master If not external FIFO

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3.1 RDATAH @ 0x048 – Read Half-word Data (from-bus) register

This register allows reading a Half-word (byte pair) from the bus (Master) unless external FIFO is used.
A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated the RX FIFO level
trigger or RXCOUNT available space in the DATACTRL register.

Bit(s) Type Name Description Config

7:0 RO LSB 1st byte read from Master If not external FIFO and if configured for
nd
half-word data
15:8 RO MSB 2 byte read from Master

3.1 CAPABILITIES @ 0x060 – Dynamic Address register

The Capabilities read-only register indicates what is configured in the block, so that SW can be sure it is
matched.

Bit(s) Type Name Description

1:0 RO IDENA Indicates how the ID 48b value is to be handled.

• 0 = application
• 1 = HW
• 2 = HW but instance provided
• 3 = PARTNO register used

5:2 RO IDREG Bits indicate what is in Regs vs. in HW:

• Bit 0 = 1: ID Instance is a register. Only if no PARTNO reg
• Bit 1 = 1: IDRAND field is available
• Bit 2 = 1: DCR register is available
• Bit 3 = 1: BCR register is available

8:6 RO HDRSUPP Indicates which HDR is supported:

• Bit 0 = 1: DDR
• Bit 1 = 1: TSP
• Bit 2 = 1: TSL

9 RO MASTER 1 if Master capability included.

11:10 RO SADDR Indicates how static address is handled:

• 0 = no static address
• 1 = static address fixed in HW
• 2 = HW controls dynamically (e.g. from pin strap)
• 3 = CONFIG register supplies the static address

15:12 RO CCCHANDLE Indicates who handles CCCs between block and app:
• Bit 0 = 1: Block handles events, activities, status, HDR, and if
enabled for it, ID and static address related

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• Bit 1 = 1: Block handles max read and write length as well as max
data speed.
• Bit 2 = 1: GETSTATUS CCC will return the CTRL register’s
PENDINT and ACTSTATE fields.
• Bit 3 = 1: GETSTATUS CCC will return the CTRL register’s
VENDINFO (vendor info) bits.

20:16 RO IBI_MR_HJ Indicates which events are to be allowed:

• Bit 0 = 1: Supports application generating an IBI
• Bit 1 = 1: when Bit 0=1, means IBI has data from register
• Bit 2 = 1: Supports application generating Master request for
2ndary master or Peer to Peer.
• Bit 3 = 1: Supports application generating Hot Join
• Bit 4 = 1: Use BAMATCH register for Bus Available timing.

21 RO TIMECTRL If 1, indicates that at least one time control type is supported.

22 - - reserved

25:23 RO EXTFIFO Indicates External FIFOs is enabled. If not, check FIFOTX and FIFORX for
internal FIFO.
• 0 = no external FIFO.
• 1 = standard available/free external FIFO
• 2 = request track external FIFO
• 3= reserved

27:26 RO FIFOTX Indicates if TX (to-bus) is enabled and what size it is:

• 0 = default 2 byte TX FIFO.
• 1 = 4 byte TX FIFO
• 2 = 8 byte TX FIFO
• 3 = 16 byte TX FIFO

29:28 RO FIFORX Indicates if RX (from-bus) is enabled and what size it is:

• 0 = default 2 (or 3) byte RX FIFO.
• 1 = 4 byte RX FIFO
• 2 = 8 byte RX FIFO
• 3 = 16 byte RX FIFO

30 RO INT 1 if Interrupts supported

31 RO DMA 1 if DMA supported

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3.2 DYNADDR @ 0x064 – Dynamic Address register

The Dynamic Address register is filled in with the assigned address once the Master has assigned it via
SETDASA or ENTDAA CCC commands. It will clear if the RESETDAA CCC is used. The current validity state
is also indicated via the STATUS.DAVALID bit, which can be used to interrupt the processor.
If configured to allow write, this is only used to restore the DA after a power-down (ultra low power state that
loses power to peripheral, but retains the DA somewhere else). This is not needed if state-retention flops are
used for the DA. This mechanism only allows write when slave is disabled (will be ignored otherwise). If the
Master uses RSTDAA or SETNEWDA, it will over-ride this mechanism and cede to the Master assigned DA.
Note that when when enabling the slave, the CONFIG.OFFLINE bit should be set as well. This will wait for
evidence that the bus is not in I3C HDR mode – will exit when an HDR Exit pattern is see or when 60us has
expired. This makes it safe to monitor START and STOP. If the App needs to do an IBI, it should either wait
for a STOP (see STATUS) or make sure that 200 micro-seconds have gone by with no activity (no START or
STOP) before emitting the IBI.

Bit(s) Type Name Description Config

0 RO or RW DAVALID Is 1 if Dynamic Address is Assigned. Writable only if enabled.

Not an option for Mixed
7:1 RO or RW DADDR Assigned Dynamic Address when Master+Slave
DAVALID is 1.

31:16 WO and KEY Must set to 0xA4D9 to write DADDR

RO (and set DAVALID to 1). Only writable
when slave is not enabled (for restoral).
Reads back as 1 if overwritten, else is 0
if from Master assigned, including when
master changes it.

3.1 MAXLIMITS @ 0x068 – Maximum limits set by I3C Master (if configured for
Limits)
The Max limits may or may not be enabled in the HW, including max read and write length. If they are, the
current setting (including default request) shows up in this register.

Bit(s) Type Name Description

11:0 RW MAXRD Maximum read length. Must be between 16 and saturation at 4095 (means is set
to that or higher).
App should not set higher than Master sets, only smaller.
Default: non-0 if set by parameters in HW config.

27:16 RW MAXWR Maximum write length. Must be between 8 and saturation at 4095 (means is set
to that or higher).
App should not set higher than Master sets, only smaller.
Default: non-0 if set by parameters in HW config.

3.1 PARTNO @ 0x06C – Register to allow Application to set I3C Part number ID (if
configured for Part-number from app)
The Part number is normally hard coded into the hardware, but if the application needs to set it, this allows
that. It is only available if configured for a register based part number. Note that part number includes instance
as well. The application must write a value into this field since 0 is not normally valid.

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Bit(s) Type Name Description

31:0 RW PARTNO May be set to the part number.

3.1 IDEXT @ 0x070 – Register to allow Application to set I3C ID components (if
configured for ID parts from app)
The ID extension fields of Instance (from Part number), DCR, and BCR are normally set in the HW. But. If
configured, the Application must set them instead.

Bit(s) Type Name Description

3:0 RW INSTANCE Set the Instance of the ID if configured. Would not be used if PARTNO is
provided by the application.

15:8 RW DCR Set the DCR (device type) register if configured for it.

23:16 RW BCR Set the BCR (Bus capabilities) register if configured for it. This controls
features like Peer-to-peer or 2ndary master, Slow speed requirements, etc.

3.1 VENDORID @ 0x074 – Register to allow Application to set I3C Vendor ID (if
configured for VID from app)
The MIPI Vendor ID is normally hard coded into the hardware, but if the application needs to set it, this allows
that. It is only available if configured for a register based VID. The default will be set from the constant field
and so usually will be the chip vendor. If using the chip vendor ID, the PARTNO must then not collide with
other uses.
MIPI Vendor ID is available to all companies, MIPI member or not; it only takes a request via the mipi.org
website.

Bit(s) Type Name Description

14:0 RW VID May be set to the 15-bit MIPI Vendor ID if used.

3.1 TCCLOCK @ 0x078 – Register to allow Application to indicate Frequency and

accuracy of time-control clock (if enabled)
The Clock frequency and accuracy is normally a constant set by the HW. But, if the clock can be adjusted (e.g.
divided) or the accuracy could vary with knowable information, then it may be set via the register. This should
be updated whenever the clock source is changed.

Bit(s) Type Name Description Config

7:0 RW ACCURACY Clock accuracy in 1/10ths of %. So, If time control used and if Reg
1.5% is 15. form is selected.
Default: set by parameters if
configured.

15:8 RW FREQ Clock frequency in 0.5MHz steps (e.g. If time control used and if Reg
10MHz is 20). form is selected.

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Default: set by parameters if

configured.

3.1 ID @ 0xFFC – Optional BlockID

The BlockID, if enabled, allows software to detect the block and its version info.

Bit(s) Type Name Description

31:0 RO ID Meaning is specific to each use. Default: Parameter sets this value.

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