5.

froqrammabk Logic lindoo Dertgr Devieey

drplcaton Specitie Tnteqrated Cireuit CAsTc] :

t is clarsified into 2
types,
- Full custorn ( l00 authorty power to derign Tc]
- Semi curtom ( 50 % author'ty b design Tc]

ASTC

full- custom Semi- custom

Proqram mable cell based Gate anay based

PLA PAL PLE CPLD FPaA channel channlur

Stuctured
uhere, PLA ’ Programmable logic aay
PAL ’ Proqrammable -trray Logie
PLE ’ nqrammable logic elements
CPLD Contiqura ble froqrammable logic Device.
FPGA Field
Proqrammable Gate array
- The chip cost is calculated as,

chip cost =D+ chip + F

N

here , O Devetop ment Cost Cpaying salaner to derige

N’ Number ol chips
manufactured
F ’ Testmg
Tes tng and packing cost
Chip Unit chip cost
ful Custom

Jbis AsIC the unction and tayout ol

vEny
uansts tor is practtaly optimized. Designert has kull control
aver the design of ciruit, In this stC each transis tor is
dwign ed and optimized. The ounroll dvtlepmnt cort of ony
cost -+ chip4 F
D+
functional aspects o! As1C :

- Cast and Time Scale

- fluibility (silfiton integration)
-Eaug and accuray

vHDL
Re-layout D:sign
Simulatien baEnty

Jogic Net list Ple

ogicel Synthuris
Duig
Syuten Greoping
partiteni of componnb/
togie blect,

Post-layout | flooY
plonny
Simulation

placemtnt
Duign

Cirautt
hmulahurt Routing
Fxtracior
mish
 Enter the desiqn into a fent ile ot VHDL or
Schematic nty
Loqic Synthesis :
Use DL or
Veileq logie synthesis tool to pndue
netist rle whlch consist the desciption of toqic cls and
their con necton.
Squem partiening (patitianing) :
desin is veng larqe then divide into number
IP the design
group of logic cells or AIC Sized pieces.
re- layol Simulatton &
t is ued to check the functional ity and behaviour of
the design waueform,
is correct or not by obsening output
floor planning
Arranqt, the no. of blockg of net list fle orn the chip
layout.
Placement:
Besfde the ocations of leqie cell it varnous
blocks.
Rautirng :
Make the no. of connection between the logic cetlt and
logic blocks,
Circuit Extraction:

pekrmin resistance and capacitance of înter Connect

pattns to calculate time

fort-layo ut Simulation :
dlay.
Tt îî wed to check the deriqn stitt workS properly
oT not where w obrerued at duign entry
 proqrammable Loqic aray (PnJ :
Tt is an
aray of invertexs, AND, oR togic qaes. pLA
bth our inputsA6, c, D. These 9 inputs ate inverted to
pdute4 pairs of Complimuntary inputs ( A,n,ã &B,8 6
produce
,t& D,D). There 8 signals are then each conneced to
the înput s o no. ol AND qates -through an aay ot
Ruesable link. This fuesable
fuesable lnk detemines tht pattern
connecfions between input signal and AND gotes.
The second of tues able 1ink ?9 uged to
aray
connect the output o! AND gates to collector ot oR
qaBes. These oR gatts are combined to provide various
outputs.
A

Yi ABC+ ABC+ ABCp

Disaduantaq
Ihe
major disadvantaqe ol! PLA is that a popagation
ay ot the logic gate will pass the inveréted input to
a shor time af ter the non- inverked siqnal,
- Due to more no. of inputs to AND aray it develop,
add'tional propagatBon delay.
These disadvantages can be OVerCoMe by moditying
Structue o PLA by a parfieular symbol and
by replacing fuesable tinko.

Vesign ol nqrammabe hray toqic Cen:

Tt is also0 aranqed by N' no. oB, înputs less than
2N
AND qotes , N inverBers and few oR gaks- Tt consist
AND aray is equivalent to PLA or
prnqrammed or

has been replaced by a fixed patte of connectiong to a

set ot gates.
The uSeY constucts the Tequired tunctions by
uing AND aray
Interconnectd.
A
frnqrammable
Pattern
fed
connecton

D
 PAL 's part names are represened
as L6 L8, 16 V8, J6 A8
Where,
L ctive lou
I6 No. o} inputs to
VUariable
8 No. of inputS .
Cell Bared ASTC
Standord cell baued

fre desig ned togic cells are known as standard cells. TE

In SST
impoves AND gates, OR gates, mutiplers, Flip Peps cte.
circuitNAND, NOR , inverters, bulfers and reqis ters, are considored
u stanaard Cells.
M9I circu•ts Consist decoders, encoders trees , addeS
and comparators Cre standard cells.
parity
LSI CiTcuit consist data path sys len ike ALO, adders
shitters, bus ertra ctors memories, RAM, ROM are gtandard cells.

The architecture o! standard cell based sys tem Consist no. of

standard cells with Jlo p0TtS.

port

2
2

Standard
Cells

are desigped w'th ell

sys kems
standard cell bared combination wth (arger pe-designe
used in
anas it may
ancelgoy Such a! be
ue which qre known as eqa
Cells "
 Important Teaturt!
- Al mask layers are Cusrtomîzedtran's tore in lor
conntch'ong
- The cus tom blocks be
can be encoded and enabled by the

designtr.
Manul ockuring
Archilecure Standard
time is above 8-weeks.

cell!
t consis t P-MOs N-M0s deuics
in on
the no. of
arranged
Thit standard cell woutd
25
amy
micron
b
apponi mately
wide. The minîmum width ofmicro cell js
0A and maimum eet î o0A where Ae Oo 25 um.
This architecture alto allowr the no. o! mega cello eg
micnproce4sou, SRAM, mîco Contallers. Theee Can be placd
he same TC with standard cells. The layout is automafal
placed and outed by CAD tool.

eMOS

-N-MOr
 lstgn ot ngrammable Logic Deuicer;
Achitecture o Contigurable PLD (CPLD] :
Ilo port.

’ Micn cell

0
prngrammable
Tnter connect

etail Archf tecture o CPLD : 1

Ilo
PAL PAL
Block
Blocke &lock-1 Block-2

froqrammable Interconnct

PAL Tlo
PAL
Block Block-3
Block- y Block

PLO's may be contiqured or proqrammed to cvate a

ditterent
port custoîzed to a speciic application. PLD's use
deuice
of the deuice. The man
tchnoloqies to alloo prgramming
of CPLD, is PAL blbck. Number of
PAL blo cke are pngramaaly
inkrco
înterco nnected threugh inker connect block wbich performs
Specite togc decig.
- Features:
tomize d mark tayers/ logie cells,
 - Fast design tun aroeund aboct weeke.

Hshgle larqe bleck o prqram mable inter connect e wd

-The matrix o loqle micn cellt hat coniist of programmab),
aty legie (PnD -ote uwed by a top Hop / latch.
Applcaton
Vegn o Vancu memory RAM, ROM, PROM, EPR DM, E'PROM
-Fach micn cell consist. o! PAL folouwed by a Hip flop or
latch and muttiple micn cell in ler connec ked usinq a
ge prgramm abl interconnect bleck.

Veain ol field Irngramm able Giale Aray1 (FPGA] :

CLB od X- NOR : -

CLS
Tlo
port
r-bar :
Switch

The block o! FPGA iS CLB (contiqurable logc

main
block). These cLBs are amanqed in 2-0 for
implkmunting
arnay
Varety o togic tunctions The trackr are sed to nute
signal between logic cells. Unused Cße are Ued as
X-bar Swich which connecs ho rizontal and verhtal blocks .
port are wed for signal conditio ninq
CJes nore h
FPGAs are moTe
prekrable ! the des iqner wes
20, 000
lbqie gatec. Interconnection pattrns are °ed ar shg
(ine, double ine and tong line, wide.
 TRsting TC occur at di!erent level ol abstracttons ,
levels Cost per unlt
At waler level $0.01 to 0.1

packaqe chip levelto to 1

- At
t1 fo 410
At board tevel
$10 to $to0
At Syttem level
$100 to $1000

manufactu ning
-!the -fautts can dete cted at wafer (evel the cost et

con slderationg
-Miid signal requirements (analog digital) sped are

to be done at packagud
ay be vequire tor turtlher alen tsting
leuel or board evel.
ehip electronics might be
surtems Pke satellik. communícation
- Special
level & field level.
4sled at S q t a e
-There are two types et test pinciples ,
Test
functonaliy Test
Manufactuing
tunctonaliy Est :
the ckt is functionaly equivalent e
JE învolues that preving
ous símulatfontocls wil Support the
Same speclfica (ion, Vanious
Aunctio nality test.

Yonutacturing Test i
This test învolveS ,
short circuit
layer- to- layer
Disco nnectfon wies
Substrate.
" Thin-ozide shots w?th
grond Tails.
" Nodos shorted o pooer
 Input oating & op dsconnectien
These tests are nquired to verity the qole temninal
t t is not then
toqte eircuit is cpeating properly er not #
manulactusing defect
This test also inctude Ilo leuel test, speed test e
Ippg test.

faut Mod) Testing

Ihey are two models ured for dentiflcation ot faults ,
Stuck at zero (o) (sAo model
"Stuck at one C1) fsA11 modal
is
lhen we tduntity SA0, sA faults then the tayer
connected to qrocund (Sno) a Vpp or loqic 1 (sA1)
even -the Ilo loqjc ehanges.
Automattc Test pateyn eneratfon [ATPG)
test Ve ctors which Consist.
This model qenerates varnous
o! 4,0, p, D, X.
tlhere , 0 loqic 1 in qood machine (toqic circuit)
loqic 0 in fautt machine,

vD loqic o in qod machine .

logic 4 n fault machine.
X ’ Don' cae

Eq: Tnucrter testing under ATPG

A
C

D
AND Gae loqic :
4B lo

X
oxX X
|xD
D X

- oR Gate loqie under APTG :

A BOl X D

0-1X D

X X X X

Dsin strateqis for Test Design for Testability :

Thete are major 4 4pproaches tor ttstability
- td- hoc sting
as Scan- baued estg erting
Self test or Built-in Tuting
Iopg Tectrng
Ad-hoc
t is a collectfon ef vano us deQs a
at neducingHud
involves,
Combinationa! toqíc circuit sting This 4sting
eicuits.
partioning the tarqe sequential
tdding 4ect
test polnts

- Adding mutiplesers
- Prouiding for Teret,
 - The lonq counters aTe elampk1 ter ad. hoc testing.

Scan- based Testinq

This ertinq is inplemunted to ve ity a designtr is
foleuedA bared destgn ules.
This esttnq alse consist 3 approacher
Seial scan
-partial Serial Scan
-Parallel Scan
- Self Test or Buflt-in Test i
This tert s wed to perfon uaniout operations on themsd
that preves Comect operation . TH is a buîlt-în tert mode! tr

cyclie edundancy check which inuclues uarous test principlu

for checking the function alits ef a toqBe ciruit,
-IoDg. Testing
This test is împlemenkd on Various MOS devîces switchn
prepery bT not . Tt it is not Sottchin then t craw no De

cuent. It can be obrerued by Ippg test.

chip lewel Tert pinciplar

Thig test
pinc ple includer , bounda ny scan te st and

Tut Aceeut Port (TAP1. These 2 tertr 7epresents vañou conneckuit

bttwttn the component S. H also
Usc test sampling and the
stting Ilo perts.
It alto includts distibution and coltechion of self test
or built- in fest.