CHAPTER-4

Combinational Logic

Digital Design (with an introduction to the Verilog HDL) 6th Edition,

M. Morris Mano, Michael D. Ciletti

• Dr. Kalpana Settu

Assistant Professor
ECE, IIITDM Kancheepuram
 Outline
 Combinational Circuits
 Analysis Procedure
 Design Procedure
 Binary Adder-Subtractor
 Decimal Adder
 Binary Multiplier
 Magnitude Comparator
 Decoders
 Encoders
 Multiplexer

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 Combinational Logic
 Logic circuits for digital systems may be combinational or
sequential.
 A combinational circuit consists of logic gates whose outputs at
any time are determined from only the present combination of
inputs.
 The diagram of a combinational circuit has logic gates with no
feedback paths or memory elements.
 A combinational circuit performs an operation that can be
specified logically by a set of Boolean functions.

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 Sequential Logic
 In contrast, sequential circuits employ storage elements in addition to
logic gates.
 Because the state of the storage elements is a function of previous inputs,
the outputs of a sequential circuit depend not only on present values of
inputs, but also on past inputs.
 The circuit behavior must be specified by a time sequence of inputs and
internal states.

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 Combinational Circuits
 A combinational circuit consists of
 Input variables
 Logic gates
 Output variables

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 Combinational Circuits

 Each input and output variable is a binary signal

 Represent logic 1 and logic 0
 There are 2n possible binary input combinations for n input variable
 Only one possible output value for each possible input combination
 Can be specified with a truth table
 Can also be described by m Boolean functions, one for each output variable
 Each output function is expressed in terms of n input variables

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 Outline
 Combinational Circuits
 Analysis Procedure
 Design Procedure
 Binary Adder-Subtractor
 Decimal Adder
 Binary Multiplier
 Magnitude Comparator
 Decoders
 Encoders
 Multiplexer

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 Analysis Procedure
 Analysis: determine the function that the circuit implements
 Often start with a given logic diagram
 The analysis can be performed by
 Manually finding Boolean functions
 Manually finding truth table
 Using a computer simulation program
 First step: make sure that circuit is combinational
 Without feedback paths or memory elements
 Second step: obtain the output Boolean functions or the truth table

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 Analysis Procedure
Step 1:
 Label all gate outputs that are a function of input variables
 Determine Boolean functions for each gate output

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 Analysis Procedure
Step 2:
 Label the gates that are a function of input variables and previously labeled gates
 Find the Boolean function for these gates

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 Analysis Procedure
Step 3:
 Obtain the output Boolean function in term of input variables
 By repeated substitution of previously defined functions

Step 4:
 Build up the truth table
As we know ahead F1, F1 = S(1, 2, 4, 7), we can verify the function by truth
table

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 Analysis Procedure
 To obtain the truth table from the logic diagram:
1. Determine the number of input variables For n inputs:
 2n possible combinations
 List the binary numbers from 0 to (2n -1) in a table
2. Label the outputs of selected gates
3. Obtain the truth table for the outputs of those gates that are a function of the
input variables only
4. Obtain the truth table for those gates that are a function of previously defined
variables at step 3
 Repeatedly until all outputs are determined

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 Analysis Procedure
 Realize the truth table “level-by-level” for verification.

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 Outline
 Combinational Circuits
 Analysis Procedure
 Design Procedure
 Binary Adder-Subtractor
 Decimal Adder
 Binary Multiplier
 Magnitude Comparator
 Decoders
 Encoders
 Multiplexer

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 Design Procedure

 Design procedure:
 start from the specification of the problem and
 culminates in a logic circuit diagram or a set of Boolean functions
 Step 1: determine the required number of inputs and outputs from the
specification
 Step 2: derive the truth table that defines the required relationship between
inputs and outputs
 Step 3: obtain the simplified Boolean function for each output as a function of
the input variables
 Step 4: draw the logic diagram and verify the correctness of the design

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 Code Conversion Example
Example: Build up a logic circuit to convert a BCD code to an Excess-3
code

 The 6 input
combinations not
listed are don’t cares
 These values have
no meaning in BCD
 We can arbitrary
assign them to 1 or 0

Note: Excess 3 code is the code with “additional” 3

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 Maps for Code Converter
 Step 1: Find inputs and outputs and the truth table.
 Step 2: Making a K-map for the inputs and outputs.
 Step 3: Find the logic expressions from the K-map.
Z y

 The six don’t care minterms (10~15) are marked with X

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 Maps for Code Converter
x w

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 Logic Diagram for the Converter
 There are various possibilities for a logic diagram that implements a circuit
 A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps
 The expressions may be manipulated algebraically to use common gates for
two or more outputs
 Reduce the number of gates used

Simplified function Another implementation

z = D' z = D'
y = CD +C'D' y = CD +C'D' = CD + (C+D)'
x = B'C + B'D+BC'D’ x = B'C + B'D+BC'D' = B'(C+D) +B(C+D)'
w = A+BC+BD w = A+BC+BD = A+B(C+D)

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Logic Diagram for the Converter
z = D'
y = CD +C'D' = CD + (C+D)'
x = B'C + B'D+BC'D' = B'(C+D) +B(C+D)'
w = A+BC+BD = A+B(C+D)

C + D is commonly used
to implement the three outputs

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 Outline
 Combinational Circuits
 Analysis Procedure
 Design Procedure
 Binary Adder-Subtractor
 Decimal Adder
 Binary Multiplier
 Magnitude Comparator
 Decoders
 Encoders
 Multiplexer

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 Adder

 The most basic arithmetic operation is the addition of two binary digits
 When both augend and addend bits are equal to 1, the binary sum consists
of two digits (1 + 1 = 10)
0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10

Carry
 The higher significant bit of this result is called a carry
 A combination circuit that performs the addition of two bits is half adder
 A adder performs the addition of 2 significant bits and a previous carry is called
a full adder

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 Half Adder
 A combinational circuit that performs the addition of two bits is
called a half adder.
 two input variables: x, y
 two output variables: C (carry), S (sum)
 truth table

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 Half Adder
 Circuit implementation of a half adder

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 Full Adder
 The arithmetic sum of three input bits
 Three input bits
 x, y: two significant bits
 z: the carry bit from the previous lower significant bit
 Two output bits: C, S

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Full Adder

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Full Adder

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 Full Adder

𝑆 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 ′ + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧
= 𝑧 ′ (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ) + 𝑧(𝑥 ′ 𝑦 ′ + 𝑥𝑦)
= 𝑧 ′ (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ) + 𝑧[ 𝑥 ′ 𝑦 ′ + 𝑥 (𝑥 ′ 𝑦 ′ + 𝑦)]
= 𝑧 ′ (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ) + 𝑧[ 𝑥 ′ + 𝑥 (𝑦 ′ + 𝑥)(𝑥 ′ + 𝑦)(𝑦 ′ + y)]
= 𝑧 ′ (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ) + 𝑧[ 𝑦𝑥 ′ ′ (𝑥𝑦 ′ )′]
= 𝑧 ′ (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ) + 𝑧 𝑦𝑥 ′ + 𝑥𝑦 ′ ′

𝑆 = 𝑧(𝑥 ′ 𝑦 + 𝑥𝑦′) = 𝑧(𝑥𝑦)

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 Full Adder

Make a full adder Different?

using 2 half adders
and one OR gate
𝐶 = 𝑧 𝑥𝑦 + 𝑥𝑦

half adder
half adder

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Full Adder

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 Full Adder
 A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers.
 Can be constructed with full adders connected in cascade
 The output carry from each full adder is connected to input carry of the next full adder in
the chain
 n-bit binary ripple carry adder is connected by n FAs

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 Full Adder
 Consider two binary number A = 1011 and B = 0011

Example:
4 bit binary adder

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 Carry Propagation
 As in any combinational circuit, the signal must propagate through the gates before the
output is available.
 The total propagation time is equal to the propagation delay of a typical gate times the
number of levels in the circuit.
 The longest propagation delay time in an adder is the time it takes the carry to
propagate through the full adders.
 Each bit of the sum output depends on the value of the input carry
 The value of Si will be in final value only after the input carry Ci has been propagated

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 Full Adder with P and G
 The full adder can be redrawn with two internal signals P (propagation) and G
(generation)
 The signal from input carry Ci to output carry Ci+1 propagates through an AND and a
OR gate (2 gate levels)
 For n-bit adder, there are 2n gate levels for the carry to propagate from input to output

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 Carry Propagation

 The carry propagation time is a limiting factor on the speed with which two numbers are
added
 All other arithmetic operations are implemented by successive additions
 The time consumed during the addition is very critical
 To reduce the carry propagation delay
 Employ faster gates with reduced delays
 Increase the equipment complexity
 Several techniques for reducing the carry propagation time in a parallel adder
 The most widely used technique employs the principle of carry lookahead

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 Carry Propagation and Generation

 Gi, called “carry generate”, produces a carry 1 when Ai and Bi are 1.

 Pi is called a “carry propagate”, because it determines whether a carry into stage i will
propagate into stage i + 1.

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 Carry Lookahead Logic

C3 is propagated at the
same time as C1 and C2.

 Use “carry lookahead logic” to

reduce the propagation.

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Four-bit Adder with Carry Lookahead

Output S1 to S3 can have equal

propagation delay times
C0

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 Binary Subtractor
 The subtraction A − B can be done by taking the 2’s complement of B and
adding it to A .
 The 2’s complement can be obtained by taking the 1’s complement and adding 1.
 A - B = A + (B + 1)
 The 1’s complement can be implemented with inverters.

Example: Find 2’s complement of 10110011

01001100 1’s complement (inverted)

+ 1

01001101 2’s complement  Place inverters between each data input B and the
corresponding input of the full adder.
 C0 = 1

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 4-bit Adder-subtractor
 A B = A (2’s complement of B)
 M=0 (Adder) [M=0, A+B]
 Input of FA is A and B (B  0 = B), and C0 is 0
 M=1 (Subtractor) [M=1, A+B′+1]
 Input of FA is A and B′ (B  1 = B′), and C0 is 1

M-mode input

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 Overflow
 An overflow occurs when two number of n digits each are added
and the sum occupies n+1 digits
 An overflow can only occur when two numbers added are both
positive or both negative

The two carry bits are different

Example:

(106) (106)
(010010110) (101101010)
Overflow

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 Overflow detection
 An overflow condition can be detected by observing the carry into the sign bit position
and the carry out of the sign bit position
 If these two carries are not equal, and overflow has occurred
 If the output V is equal to 1, an overflow is detected

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 Adder-subtractor circuit
 Unsigned
 C bit detects a carry after addition or a borrow after subtraction
 Signed
 V bit detects an overflow
0: no overflow; n -bit result is correct
1: overflow; result of the operation contains n + 1 bits

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 Decimal Adder
 A decimal adder requires a minimum of 9 inputs and 5 outputs
 1 digit requires 4-bit
 Input: 2 digits + 1-bit carry
 Output: 1 digit + 1-bit carry

BCD Adder
 How do we implement a BCD adder? Let’s see the relationship between a binary
sum to a BCD sum (the table in the next page).
 The maximum value for a BCD sum will be 9 + 9 + 1, while 1 is a carry from the
previous bit.
 Remember: If the sum is 10, 11, 12, ..19. We need to add binary 6 (i.e. 0110) to
the binary sum in order to obtain a correct BCD code.

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 BCD Adder
 When the binary sum is equal to
or less than 1001b
 BCD Sum = Binary Sum
 C=0
 When the binary sum is greater
same than 1001b
 BCD Sum = Binary Sum +
0110b
 C=1
 If binary sum Z8Z4Z2Z1 > 9, we
should add 0110 to the sum, set C
= 1, and get the right BCD code. A
D=6 way to gain C is:

 Think how we get expression of

C (use “observation” to guess
the result).

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 BCD Adder
 The logic circuit that detects the
necessary correction can be
derived from the entries in the
table.
 It is obvious that a correction is
needed when the binary sum has
same an output carry K = 1.
 The other six combinations from
1010 through 1111 that need a
correction have a 1 in position Z8.
To distinguish them from binary
1000 and 1001, which also have a
1 in position Z8, we specify further
D=6 that either Z4 or Z2 must have a 1.
 The condition for a correction and
an output carry can be expressed
by the Boolean function

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 BCD Adder

C = 0  0000
C = 1  0110

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 BCD to Seven-segment display
A BCD–to–seven–segment decoder is a combinational circuit that converts a decimal
digit in BCD to an appropriate code for the selection of segments in a display indicator used
for displaying the decimal digit in a familiar form. The seven outputs of the decoder
(a,b,c,d,e,f and g) select the corresponding segments in the display, as shown in the
following figure (a). The numeric display chosen to represent the decimal digit is shown in
figure (b). Using a truth table and K–maps, design the BCD–to–seven–segment decoder
using a minimum number of gates. The six invalid combinations should result in a blank in a
display.

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Using a truth table and K–
maps, design the BCD–to–
seven–segment decoder
using a minimum number of
gates. The six invalid
combinations should result in
a blank in a display.

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50
51
BCD to Seven-segment display

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 The End

Reference:
1. Digital Design (with an introduction to the Verilog HDL) 6th Edition, M. Morris Mano,
Michael D. Ciletti

Note: The slides are supporting materials for the course “Digital Circuits” at IIITDM Kancheepuram.
Distribution without permission is prohibited.

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