Cadence Allegro X (24.

1
.1) Tutorial
(24.1)
Copyright (C) Istvan Nagy, 2025 www.buenos.extra.hu Free to share!

1. Introduction
This tutorial is targeting complex high-speed digital circuit board designs with Cadence Allegro X, using OrCAD or CHDL for
schematics. There are different grades of high-speed designs from the microcontroller boards up to the server computer motherboard
and data center line card designs, so the methodology here to be suitable for all, is based on the high-end and scalable down.
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Cadence Allegro X (24.1) Tutorial ________________1 3. High-Speed Signal Objects ____________________ 6
1. Introduction _______________________________1 4. Constraint Manager ________________________ 6
2. Basic PCB Design ___________________________1 5. Interactive High-Sp Route ____________________ 8
2.1. Projects and Editors _________________ 1 6. Signal Integrity_____________________________ 9

2.2. Schematics with OrCAD Capture _______ 1 7. Typical Examples __________________________ 10

2.3. Schematics with Concept HDL _________ 2 7.1. PCIe Gen4 SERDES bus design ________ 10
2.4. SCH Library (OrCAD) ________________ 2 7.2. DDR4 Memory-Down design ________ 10
2.5. PCB Layout Design (Allegro) __________ 2
2.6. PCB Library (Allegro footprints) _______ 5
2.7. Design Reuse (OrCAD) _______________ 5

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have upper tabs to select what we are viewing: one of the
schematic pages, or a component properties page, or a BOM
2. Basic PCB Design page... The Options> Preferences menu lets us set design
parameters, and Options> Schematic Page the page size.
2.1. Projects and Editors
In the Cadence flow we open the schematics and the layout in
separate programs, by separate teams, so there is not really an
overall project environment. We can use OrCAD capture or
ConceptHDL (CHDL) for schematic design, while the Allegro
PCB editor program is for PCB layout. The Cadence Project
Manager is only used for schematic editing in ConceptHDL.
Most companies have managed and released shared libraries,
but one-person companies can keep library files edited within
project folders. We have to add existing company libraries to be Multi-page schematics can be either hierarchical with
accessible by the project. The way to do it, and the file types are PORT connections in the module and SHEET SYMBOL in the
dependent on each program, OrCAD/CHDL/Allegro.
top level schematic, or a flat design with off-page connectors .
When we place a sheet symbol, we select what schematics it refers
2.2. Schematics with OrCAD Capture to. On the project panel we can see a tree hierarchy view. Within
OrCAD has two modes, for component library handling, the the DSN we have schematic folders, within those we have pages.
basic and the Capture CIS mode. When we start the program we On the schematic folder we can rightclick> NewPage to add
have to select license type for that mode. The file structure more. For a hierarchical design we would have modules in separate
includes an .OPJ project file with settings, and one .DSN file for schematic folders, or in separate DSN files in a library.
the drawing containing all pages. We can also have local .OLB We place parts from the network CIS company library by
library files for editing, but using the CIS company database parts Place> Component (the CIS/Component Explorer, used to be
is preferred. To create a new design: File> NewProject> “Place> Database Part”). The Place> Part uses local libraries.
Schematic. Open an existing: File>Open... the OPJ file. On the Part rotation is with rightclick> Rotate, or press “R” while
left side we have the project panel, with a hierarchical view. We placing it. Doubleclick on a part opens a full-page property editor,
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where we can see/edit/add properties. Usually we don’t edit schematic. We can also design flat schematics with no top-level,
properties here, rather in the released library, except for the then we have to use off-page connectors from the component
POPULATE property. For example, have a separate library item library.
for a 1k resistor than a 10k resistor. We should make the A component can be do not populate (DNP), to leave it out of
POPULATE property visible, by rightclick> Display in the the purchase BOM and pick&place file. Either to design for
property editor. The rows/columns can swap with the Pivot debugging (to swap a PU/PD on the prototype without trace
button. We can search for placed parts in the search bar or in the cutting), add possible future features or product variants. For DNP
browse spreadsheet (select DSN file, Edit> Browse). We can edit in CHDL we have to use variants. We have to create a variant
multiple net labels, off page names or part properties, if we select associated with the board part number in Variants> Create
multiple int eh drawing, then Edit> Properties, then copy from Variant. Then Variants> Edit Variant to set up part numbers and
the prop editor to Excel, edit there and copy back to OrCAD. such. Then we edit the design, mark intended DNPs with text
CIS library: The Options> CIS config sets our access to the comments, then save, create netlist, then Variants> View Variant
company CIS component database (spreadsheet in MS Access Schematic> select the one with the part number. Then click on
database) on the network, by selecting a DBC file. This contains marked parts, rightclick> Variants> Mark as do not install. Then
a component/property table and library file (folders for .OLB, and Variants> View Variant Schematic> Base.
footprint files) names for each part. Need a Microsoft ODBC Once done, we annotate refdes to all components and export
driver for it to work. Library file access is set in the capture.ini netlist with CHDL> File> Export> Physical, and update all off-
file, edited in the CIS Admin tool. page numbers in Project Manager> Tools> Crefer. Then export
A component can be do not populate DNP, to leave it out of a BOM with CHDL> Tools> Packager> Bill Of Materials. We
the purchase BOM and pick&place file. Either to design for also export a PDF schematic with File> Publish PDF.
debugging (to swap a PU/PD on the prototype without trace
cutting), add possible future features or product variants. We can 2.4. SCH Library (OrCAD)
do it in different ways depending on company; we could use a
POPULATE property in certain components with a value “DNP” To make our own schematic symbols, we have to create/open a
meaning not populated, or overwrite the part number with “DNP”, .OLB file using File> New> Library, that is added to the project
then delete these rows from the Excel BOM, or we can use variants. tree on the project panel. In heterogenous split components the top
level is called part, the sub-symbol is called a “section”. In the
Once components are placed, we wire them with . We can
project tree on the libraries/.OLB rightclick> New Part From
place ground symbols with , and power rail symbols with . Spreadsheet. We have to enter how many sections we will have.
We add net labels (alias) with . We can draw buses with . We can prepare a pin table in Excel in a matching format like
Diffpair nets must be named with _P and _N suffixes. Nets and below, then select data (not header), then CTRL+C to copy, then
ports are local, Off-sheet-connectors and power symbols are in OrCAD upper/left cell CTRL+V to paste.
global on all pages. Zoom works with CTRL+scroll.
Once done, we annotate refdes to all components by clicking
on the DSN file in the project tree, then Tools > Annotate, then
Tools> Create Netlist. Then export a BOM with Tools> Bill Of
Materials, ensuring that the “property string” matches our
company standard, and includes the POPULATE, company part
number, MFR_PN, description, footprint, value and anything
needed. We find all DNPs in the exported spreadsheet and delete
them, before uploading. We need to update the page numbers at the
off-page symbols by Tools> Cross Reference. Error checking
with Tools> Part Manager and Tools> Design Rules Check. On the project tree we can see our new part, we can doubleclick
We also export a PDF schematic with File> Print to PDF. to edit for manual graphical modifications. In the properties
window we have to enter properties like part number, footprint
and value. We have to add company-specific properties, for
2.3. Schematics with Concept HDL example if we work at ACME-inc., then ACME_PN,
We start this with the Cadene „Project Manager” program. It ACME_DNP, MFR_PN… In most cases this would have to be
has large buttons on it for open/create project, and for open released in the company CIS library by a librarian.
schematics. File> New> Design creates a new project. If we
open the schematics then the CHDL window opens. There is a
complex file structure for CHDL projects with many files, the 2.5. PCB Layout Design (Allegro)
important sub-folders are the name/worklib/name/physical where Allegro is also called “PCB Editor”, it opens from the windows
the Allegro board file will be. start menu. We will need the “high-speed option” license. Some
We can place components from Place> Component. There basic settings for hole visibility are in Setup> Design
are OrCAD-like buttons for wiring, net names. Press “T” for text. Parameters, and grids in Setup> Grids (5mil for placement, 1mil
The pages are listed on the left. One page is open at a time. No for routing) Allegro has to see our (company) libraries/folders, that
properties can be edited in the schematic, only in the library. We is set in Setup> User Preferences> Paths> Library> padpath
have to set part numbers Tools> Options> Custom Variables. for pads and >PSM path for footprints.
Multi-page schematics can be hierarchical with PORT We create a new layout design with File> New> Board
connections in the module and SHEET SYMBOL in the top level (Wizard), and set a few basic settings. To start the PCB design, we
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need to get a DXF file from our mechanical engineer, that contains segment, shape) we want to edit and what we don’t at the moment,
the board outline, external connector outlines and mounting holes, so when we are sliding traces the components will not move.
and import it into a mechanical layer. File> Import> DXF, then There is a free Allegro viewer software that anyone can
create and set up a layer conversion file with layer mapping to download for free, that is useful for coworkers, layout review or
Board Geometry / new mech layer, then click incremental, and lab debugging. It is lacking any editing functions, while it still has
Import. In the Setup> Subclasses we can create more mech all the layer/color commands. Starting in 2021 the Allegro Free
layers. We have to draw a closed line with Add> Line on the Viewer has the user interface of the OrCAD Presto PCB, not the
BoardGeometry/Outline layer. Set the origin Edit>Setup> Allegro’s GUI. This new viewer has more data displayed on its
Change Drawing Origin, then click on the board at the corner. Panels than the Allegro editor’s panels: The visibility panel splits
Stackup Layers: Setup> Cross Section. Add copper layers to 3 new sub-tabs, one for layers, one for nets/objects, one for
(rightclick), define their thicknesses, signal/plane type order. general display stings. The layers sub-tab shows more than just the
Selectable stackup materials are managed in Setup> Materials. Etch subclasses. The eye icon crossed means not visible. The
Layers are categorized in a 2-level hierarchy as class/subclass, the rectangles can change color here without a separate window. The
stackup copper layers are always Etch/layername. We use the options and find panels from Allegro are rearranged as the new
mechanical layers for all manufacturing comments and fab notes, Properties panel (similar to options, object filter and info) and a
created in Setup> Subclasses. The main layer classes are Etch Search panel (to browse components or nets, can search, but
(for copper traces/planes, per layer), Board geometry (outline, text, without a “*” key). For editing, the active layer is selected on the
mechanical info, fab notes), Package Geometry (outline, pin bottom of the screen on tabs. The rest of this document is not about
number from footprint, solder mask, paste), Pin (per layer), via (per the OrCAD Presto, but Allegro, although they have similar CM.
layer), Manufacturing (drill figure, legend), refdes (top/bottom), Ratsnests: Display> Show/Blank Rats> All/Net/Comp…
various keep-outs (per layer). We can have the same subclass in Layer colors can be changed in the color dialog with the color
multiple classes, like silkscreen in Board-geo and Package-geo. (old ) button. Layer visibility can be changed on the Visibility
Once the board is set up: we have to import netlist from panel, by layer and object (class) type. Temporarily enable/disable
schematic: File> Import Logic. specific layer visibility as needed, by single clicking on the color
rectangles. There is a drop-down menu for pre-defined layer sets.
Object Coloring: Nets can be displayed either in layer color,
or net color. Net coloring mode/command is selected with (old
) and decoloring with (old ). First we enable the coloring
mode, then we click the object type filter on the find panel, then
either click on an object in the drawing, or find by name on the
Find panel (select type: Symbol or Net, then enter a partial name
extended with “*”).
All Allegro edits are based on object filtering. Before moving,
selecting, deleting objects, we can disable for example components
on the Find panel, to avoid deleting/moving them.
The info button (old ) is used to check what we are
seeing on the screen, like component refdes or part number, or net
name; select filter on the find tab, then click an object, and a popup
will tell what it is. We can also use this to find/search objects, by
pressing the info button, then on the Find panel find by name (select
type: Symbol or Net, then enter a partial name extended with “*”).
Measure distance or object size: Use the (old ) button.
Component placement: First we need to place all parts next to
the board using Place> QuickPlace, click Place, then Ok. After
this we move component symbols from the auto placed area to the
real board design. Click the move button , then the object filter
(a “symbol” is a component =on, others =off), then left click/hold
the comp and move it. Once we moved enough parts and want to
The allegro user interface has 3 standard panels, some buttons do something else, rightclick>Done. The rightclick menu has
and top drop-down menus. The panels can auto hide and seen as a many options, but the most important are Done, Cancel, and Oops
tab, or they can be fixed visible. The Options panel is for setting (the last click undo), that are also used for all command types.
things for the current command. The Visibility panel is for enabling Rotate with rightclick>Rotate, or move to bottom side with
visibility for a matrix of object type vs layer. The Find panel is to rightclick> Mirror. Moving refdes, vias, traces works the same
control object filtering for click edits or type in net or component way, with the object filter set accordingly. When moving or
name to be highlighted. In Allegro everything that is on a layer editing, we can set the rightlick> SnapPickTo object types or off-
(pads, vias, traces) can be visible or invisible independently, set as grid. If the refdeses are too large, then we can Edit> Text, set the
a matrix. The object filter on the Find panel is used to control what new size on the Options or Properties panel, then click the refdes
object type (package symbol, net, pad, via, text, line, cline, cline text. We can lock a component to prevent moving it, by typing “fix”
in the bottom command window, enter, then on the Find panel
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select “symbols”, then click on the part. The reverse is typing with VIPPO we do complete tenting on top/bottom (no object on
“unfix”, then click a part or rightclick>UnfixAll. Component SM layer). On cheaper non-VIPPO designs we need complete
spacing constraint is set in CM> Manuf> DesignforAssy> tenting on top-SM (no object, especially under BGAs) and a small
PkgToPkg Spacing. opening on bottom-SM (for outgassing) in their padstack designs.
We can place footprints for floorplanning from: Place> We have to create vias before using them in the layout, in a separate
Manually> advanced> Lib=on, then PlList tab, dropdown = program in Start> Cadence> Pad Stack Editor, and saved into
PackSym, select checkbox next to the symbol name, click on our library. Vias in Allegro PCB editor can display a layer span
layout. We can also place mounting holes and fiducials from here, label like “1:8”, if enabled in Setup> Design Parameters> Drill
although using schematic is preferred. MNT holes can also be Labels. Here we can enable display of holes, and filled pads too.
placed by copying a via, then editing it in the Tools> Padstack> To use microvias, we have to create as many padstacks in the
Modify Design Padstack, then assign GND net. library as valid microvia layer pairs we have in the vendor stackup.
Design Constraints: We set all of them in the Constraint Then in CM>Physical vias list has to include all of them
manager. We should set up at least some basic ones like clearance, (doubleclick on the cell to open via list selector).
trace width, via (browse), shape connect, and diffpair rules. Fanout: Set the constraints like width and vias, spacing first.
The signal length (Package Length (PL) or Pin Delay A to B On the part Route> Create Fanout, set the options panel (via,
on diagram) within large BGA packages have to be entered for fanout style), then click the component.
accurate length tuning later. We do this in the Allegro layout, not Draw Power Shapes: on any layer, for power delivery or VRM
in the schematic. We might have to enable it in Setup> circuit power nets. Select with Shape> Polygon, then on the
Constraints> Modes> Electrical> Pin Delay> include =on, and Options panel select layer, parameters and net, then click to draw
also Zaxis> include=on. Prepare the PL data in excel (same unit it. Voids can be drawn with similarly using Shape> Manual
as the tool, mils), sorted by pin number, in 2 columns (pin number, Void> Polygon or Rectangular, then set parameters on the Options
delay ”123 MIL”), and save it as a .CSV file. In Allegro File> panel, draw it, then rightclick> Assign Net. A shape in Allegro
Import> Pin Delay, then click the component. The PL shows up can be dynamic or static-solid. Dynamic pours around objects.
in the CM but only at the relative propagation delay worksheet. Some of the shape rules and behaviors (like thermal/direct via
contact, and spacing/clearance oversize) are set in Shape> Global
Dynamic Parameters. Also here, we need to update all dynamic
shapes often, especially before review and fab-out. To edit an
existing one: Shape> Select Shape or Void> click, then
Shape> Edit Boundary or Merge, or rightclick>Assign Net.
Keepout shapes: We place regular shapes on keepout layers,
Interactive routing starts with the (old ) icon. Zoom in like via keepout class, having subclasses associated with every
Allegro works by scrolling, or by click/release the middle button routing copper layer. Component keepout, route keepout.
wheel and draw a zoom rectangle. Pan works with middle/when We can specify areas where different rules would apply
button press and hold while moving the cursor, or by arrows on locally. These areas are called „Regions” and can be specified in
keyboard. Set the grids to about 1mil for routing (Setup>Grids). the CM> Physical> Region> All Layers, add constraint values
Active layer is selected on the Options tab, but we also select a (like neck down trace width, or smaller via pad for “CLASS-3 with
second layer, in case we want to place a via while routing, it will exception”). Then we can use Shape> Polygon to place a shape
continue on that second layer. Routing mode can be controlled on a Constraint Region class and whatever subclass (like layer 1),
from the properties panel during editing, for example push/shove, and assign a CM-created region on the Options panel.
width, layer, via padstack, angles, corners. We can select the Power plane layers: Allegro prefers positive planes, as set in
the stackup. Although negative can also be used. On positive plane
(old ) button to slide/edit traces, or the button (old ) to
layers we place regular shapes, from the Shape> menu. We have
tune the trace length. Allegro calls the routed traces either as net, to keep them off the board outline by 1mm.
or “cline”, while a part of the cline is the “cline segment”, these are Plane voids: All signal vias and through pins passing through
all selectable on the Find panel. To delete anything, we have to
planes will have a circle antipad. The antipad size is defined in
select the (old ) delete command first, then Find filter, then Allegro by a combination of parameters from multiple places: The
click. To delete voids: Shape> Manual> Delete. padstack editor (antipad size and BD clearance), the clearance
Add Vias: doubleclick while routing. The via size and padstack constraints (CM>Spacing), pad suppression, and the shape
is selected on the Options panel. We could also use GSSG via parameters (oversize parameter and drop-down void-mode selector
structures while routing by Rightclick> ReturnParth, using a “DRC vs padstack”, in Shape> Global Dynamic Parameters).
template drawn earlier manually then recorded by Route> Struct> Whenever we alter padstacks, voids or traces near shapes, we have
Create. Ground stitching vias can be placed by copy/paste a routed to also update the backdrills (BD setup dialog) and the shapes (in
via, then reassign net on the Options panel, or Place> Via_Array. global dynamic parameters). We have to use the measure tool to
Vias and Component-Pads in Allegro are handled through the verify the actual AP size.
padstack editor, separate padstack .PAD files are called in the Allegro does not automatically remove all non-functional pads
footprints, but we can edit them in the layout using Tools> (NFPs), but we can “suppress pads” to reduce the Swiss-cheese
Padstack> Modify Design Padstack, then on the Options panel effect. It is useful for signal layer rout-ability under finer pitch
select definition (all) or instance (just the selected one), click edit BGAs, and for via impedance for SERDES. It also creates smaller
to open the padstack editor. The via tenting of soldermask (or antipads. To suppress NFPs we have to enable the "Unused Pin
expansion) is also set in the padstack editor. On modern designs Suppression" and "Unused Via suppression" in Cross-section
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Editor, per layer, and for the specific vias that need it "Suppress Gerber layer visible. Then Manufacture> Artwork, then on one
unconnected internal pads" enabled in the Padstack Editor. of the existing films rightclick> Add> enter name. Redo the above
Backdrilling requires a large BD-antipad AP= for all needed layers. Then back to the artwork dialog, rightclick>
BD+2*drillclearance. Allegro places a route keepout circle Select All, then click [create artwork]. This will generate several
automatically on all affected layers, that DRC-checks any traces files with the extension .ART, to be sent to the PCB fab vendor.
and pushes the planes. The drill clearance is usually 5…10mil on We can export data reports from the Tools> Reports menu.
each side, depending on our fabricator. The BD tool size is usually Select the desired report types and run it. We commonly export
6…12 mil larger in diameter than the via drill size (BD oversize). “Etch Length by Pin Pair”, and “Component Pin” reports for
Dual-voids are required for high-speed diffpairs on plane hardware engineering analysis, DRC report or “Unconnected Pin”
layers. On Allegro’s positive plane layers this means drawing report for helping finish up the layout. These are HTML, but with
Shape> Manual Void> a CTRL+C we can copy it and paste it in Excel.
Polygon or Rectangular. We
could also draw a regular 2.6. PCB Library (Allegro footprints)
shape on the route keepout
layer instead. Since we need To make our own footprint symbols, we have to create a new
these on all ground planes, we can use Edit> Zcopy. We can also .DRA file in Allegro. Each pin in the footprint is a padstack, that
copy this to signal layer route keepouts, to prevent signals passing has its own file. Within the padstack, if we want to use a thermal
between p/n vias. To delete a void: Shape> Manual> Delete. relief plane connection, then we define the pad diameter here, and
DRC check: Tools>Update DRC. The list of DRC violations the Shape> Global dynamin param describes the spoke size.
should be worked down to zero by interactive layout editing, Padstacks have to be designed for pins, before using them in
except a few items that are reviewed and accepted/waived. The footprints, and also save them into the library. From the Start
Tools> DRC Browser lists all remaining ones. The CM also menu> Cadence> Padstack Editor. File> New, select SMD,
shows all the signals and their relations to constraints with actual via or through type. On different tabs we set different parameters.
length values with green/red coloring for pass/fail. Allegro also has We also have to specify pad size and antipad size on every layer
DRC markers per layer that can be enabled for visibility on the type separately. SMD will only be on etch/top. Backdrill enable,
Visibility tab. They look like a bow tie; we can use the info button soler mask and paste mask is defined too. We can enable NFP
on them if we selected DRC errors on the Find filter. Spacing is removal (pad suppression). File>Save, in to a .PAD file.
enforced during editing, if Setup> Enable Online DRC =on. To make the footprint in Allegro: File> New> Package
What to include in DRC: Setup> Constraints> Modes. To find Symbol. In that Layout> Pins, then on the Options panel we set
unconnected pins, Tools> Quick Reports> Unconnected Pins. how many pins (quantity X & Y), what padstack, then click the
Thieving can be applied in Allegro, using Manufacture> drawing and place all pins at once, rightclick> Done. Place an
Thieving. We could also use polygon pours between traces, or rely outline with Add> Line, on the Options tab select layer Package
on our PCB fab to apply thieving for us. Geometry / Silkscreen-Top, then draw the body. Add pin1 marker
Preparing for manufacturing: Every layer should have text dots, copper corner marks, numbers or anything that’s needed.
outside of the outline about layer name, layer number, whether it is Setup> Change Drawing Origin, to the center or pin1. Setup>
upside-down (mirrored), company info and design part numbers. Areas> Package Boundary, draw it, it will be used with
On one mechanical layer (and Gerber layer) meant for fab drawing, placement DRCs. Similarly, Setup> Areas> Package Height.
we place tables for drilling, impedance and stackup, then we Save it. It will save both the .DRA file and a .PSM file that we
manually add text about technology statements, materials, surface will use in the layout.
finish, coupons, impedance and loss tables. The drill chart/table is An old free program called FPM Allegro Footprint Maker
created using Manufacture> NC> Drill Legend, on a could generate complete footprint and padstack files.
MANUFACTURE / NCLEGEND-xx layer. We also create an For large BGAs with irregular pattern, we should get an
assembly drawing on another mechanical (and a Gerber layer), for allegro reference board design file .BRD. Then export footprints
verifying the build, by using a dimensioned DXF from our ME. On with: File> Export> Libraries into a folder.
mech layers we can place line or text. Add>Text or Edit>Text,
Add>Line. Once all done we fab-out: Manufacture> Artwork to 2.7. Design Reuse (OrCAD)
set up and generate Gerber file layers as combinations of Allegro Design-reuse with a project is done using hierarchical designs,
Class/subclasses. We also generate drilling files with with single/multiple instances of the same sch sheet symbol. The
Manufacture> NC> NC drill, but enable the checkbox “include hierarchical block (sheet) symbol parameters dialog has 3 drop-
backdrill”, […] to create a file name, then press [drill]. We generate down menus. In the first one (Implementation Type) we select
a pick and place file using File> Export> Placement (origin = “schematic”, in the second (Impl. Name) we select the SCH folder
body center), or Tools> Reports> Custom. We send a 3D name for in-design hierarchy, or leave it blank and browse to a
drawing to our ME to check system fit: File> Export> IDF (EMN). saved external reuse block in the third (Path) menu.
PDF fab and assembly drawings to be exported from File> To edit the block’s schematic: rightclick> Descend Hierarchy.
Export> PDF, and select which Gerber layers to be used (one The block should not contain global power symbols, except GND,
Gerber layer per PDF sheet). rather use ports to deliver power nets and all signals. Once
The Gerber films have to be set up: We have to create extra instantiated, the refdes and net names will be overridden as
Gerber film layers, for example silkscreen, solder mask and paste, netname_instancexx. Instance and occurrence property.
fab notes and assembly notes. In the colors dialog turn off all Reusing designs from external projects can also be done by
layers, then make only the layers that we want to add to a new creating a separate OrCAD project with a .DSN schematics, an
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.OLB library file and a .BRD layout file (in the allegro subfolder), ECSETs in the Electrical
a generated .MDD board snippet file. All with the same filename. worksheets, PCSs on the
We will be referencing it in a hierarchical block properties. The physical trace width sheets,
properties will look like this: Implementation Path property = SCS in spacing. All CM
“C:\path\ filename.DSN”, the PCB Footprint property = categories have a tree structure
“filename”, the Source Library = “filename.OLB”. If we have of worksheets, half of the tree is
multiple copies of a block, then we will see yellow “occurrence” for CSETs (one row is one
property columns, one for each copy, and a white instance property CSET) and the other half called
column for the overall. “Net” (one row is one object)
for individual entry or CSET
application (CSET name from a
3. High-Speed Signal Objects drop down). One parameter has
The connection objects define the signals, or groups of signals. one column. Some constraint
They can be browsed in the CM. Categories: domains also have a sub-tree for
Net: created using net labels in schema. Net length does regions.
not include via length and package length. In the Spacing Worksheet
Bus: create using bus symbols in schema, it uses indexed we can define a clearance
net names, like ABC1_[7:0]  ABC1_0. For serdes- between Net or net class and
based interfaces, it is better not to use buses, unless we other objects by object type
have a hierarchical schematic on a large line card design. (pad, trace, via, shape), in a
Diffpair (DPr): Create them in the CM Electrical/ matrix. Constraints sets (SCS)
Diffpairs worksheet with Objects> Create> Differential can be created here too. Spacing
Pair> Auto Setup, then in the setup dialog w specify the in PCB design has two aspects:
_P and _N suffixes, and then press [Create]. manufacturability and crosstalk
Net Class (NCl): A group object, used for trace width levels. For the first aspect, we
(impedance) related constraints in Allegro. In CM> set up a CM> Spacing> SCS>
Physical> Net> All Layers worksheet, select all needed All Layers, which is normally the min spacing that our PCB
nets, then rightclick> Create> Class. manufacturer recommends. Basic spacing is enforced by a
PinPair (PPr): This is to control propagation delay from a push/shove force in interactive routing. The CM> Electrical>
pin and another pin on a multi-point net. On a DDR4 fly- Routing> Differential Pair rules also contain a field called „Gap”,
by address bus, on every address net we would have but this is a related to the differential impedance of the diffpair. We
several PinPairs from CPU-DRAM0, CPU-DRAM1… can enter more spacing object type combinations, if we select a
CPU-DRAM7. PinPairs should be created in CM> column header, rightclick> Show More.
Electrical> Net> Relative Prop, by selecting a net,
rightclick> Create> PinPair. They only appear in
relative prop delay and min/max prop delay rules. PPr
length does include via length and package length.
Matched group (MGrp): We create one MGrp for all the
PinPairs of all address nets between CPU-DRAM1. Then
enter a length matching constraint number set for that The Max Parallel constraint is used for crosstalk control
spacing: CM> Electrical> Net> Routing> Wiring> Parallel-
MGrp. Another MGrp and a numbers entered for CPU-
DRAM2. MGrp’s should be created with the CM> column. This rule only checks spacing if the two traces run in
Electrical> Net> Relative Prop, by selecting one or parallel longer than specified. We have to enter a weird string into
this field, containing up to 4 length/separation number pairs:
more PPr’s, rightclick> Create> Matched Group.
“<len1>:<space1>;<len2>:<space2>”. For example, “60 mil:4 mil;
XNET: XNETs are for two nets passing a series passive
part. First the components have to have .DML models 200 mil:8 mil;16000 mil: 16 mil”, which means up to 60mils
parallel length we enforce 4mil space, 60…200 mil length we
assigned to them, in Analyze> Model Assignment, then
enforce 8mils, between 200mil and 16 inches we enforce 16mil. If
they are auto created and appear in CM.
we click on the field, we can set them up in a box/matrix window.
In the Physical Worksheet we can see most signal object types
4. Constraint Manager (DPr, Net, NCl, bus) in a tree hierarchy browser view, and specify
Open the Allegro CM: Setup > Constraints> Constraint trace width and a via padstack file to them. Net classes are created
here by selecting multiple nets, rightclick> Create> NetClass.
Manager, or use the button (old ), for design rules. This way we only have to apply constraints to their members in one
It has several types of worksheets: Electrical (lengths), row. The diffpair constraints reappear here in the physical
Physical (width), Spacing, Same Net Spacing, Properties. Each worksheets, although we prefer to set them in the Electrical>
type (domain) has a tree structure of categories (folder/ workbook/ Routing worksheet. We either enter the constraint numbers for each
worksheet). row in Phys> Net, or select a physical constraint set PCS. Normally
We can create Constraint sets, that are sets of rule-number we put a group of nets based on characteristic impedance into a Net
values, that can be applied to multiple objects (Net, DPr, PPr…) Class. Then we set up a PCS for every class separately, and also a
instead of typing those numbers in for every object separately. default width rule for all other or non-impedance controlled traces
6
(4mil). The PCS folder has 2 worksheets, “All Layers” and “By topology pin pairs for all selected nets. It will also put all of them
Layer”. The All Layers has entries like “4.5:5.2:4.0:5.2…”, but into the right matched groups like the first net was. If we need
clicking the arrow opens a tree/table showing regular values per multiple independent MGrps, like separate byte lanes on a memory
layer. We should use width rules instead of impedance rules, interface, then we will use a separate ECSET for each lane. Basic
because we have to use the fab vendor’s impedance/width/space nets do not include via length and package length, only PPr’s do,
calculations (from the negotiated approved stackup document), so we have to use PPr’s in MGrp’s, even on point-to-point nets. We
instead of Allegro’s calculator. can still use Nets for SERDES link lane-to-lane matching.
The Electrical worksheet is for high-speed design trace length
constraint categories. Its constraint set is called ECSETs. Both the
ECSET and the Net has the same sub categories. On the Net tab the
most used categories are the “Differential Pair” (phase tolerance,
trace/gap, uncoupled length), the “Total etch length”, the “Relative
Propagation Delay” (for matching trace lengths in MGrp’s) and the
“Min/Max Trace length”. The PPr/MGpr/DPr objects are created
in CM by selecting multiple objects and rightclick>Create>...
The Electr> Routing> Differential Pair category is for phase
tolerance length matching, diffpair gap and uncoupled length
constraints (numbers), applied to diffpairs. We either create a new
ECSET for each diffpair impedance type (like 85, 93 Ohm…), or
we just enter the constraints (numbers) into the rows of specific
diffpairs. We set static phase typically 5mils. If we use dynamic
phase tolerance, then usually 5mil on 5” “max length”. The width The Electr> Routing> Min/Max Propagation Delay:
is inherited from the physical worksheets. Saved GSSG via category is for specifying min or max trace lengths for synchronous
structures can be added to nets in Electr> Routing> Vias> ViaStr. or asynchronous buses, so they can meet setup and hold timing. We
The Electr> Routing> Relative Prop Delay category is for can create ECSETs for them, and apply it to as many PinPairs, nets,
trace length matching constraints (numbers), applied to matched buses, or diffpairs as needed. On a multi-drop PCIX bus we would
groups (MGrp’s). MGrp’s are usually applied to PinPairs, but in need constraining from CPU to each target device, as PinPairs. We
some cases we can apply them to nets, XNETs, buses or diffpairs can specify max length in the MinMax Prop (supporting PinPairs
too. We can use this for single-ended buses, or lane-to-lane and package length) or in the CM> Electr> Routing> Total Etch
matching of diffpairs. The diffpair P-to-N phase tolerance Length (nets only, no PL). For SERDES diffpairs we might need
matching is not here, it is on the diffpair worksheet. Typically, we loss-budget-based max length constraints. At 200Gbps/lane the
enter a delta and a tolerance value as numbers, to the MGrp, then budget includes the PL too, while below that PL is excluded.
all members immediately inherit these numbers below. Tolerance Maximum Length constraint values for SERDES buses come
is the max deviation, while delta means a fixed offset. For example, from insertion loss budget calculations. The dB/inch loss data,
if we want SIG1 to be matched to SIG2 within 5mils, while SIG2 specific to a fabricator and material combination, comes from VNA
is already routed to 200 mils, but SIG1 needs to be 50 mils longer, measurements on Delta-L test boards, then the max trace length is
then the correct range for SIG1 will be 245…255mils once routed calculated as L<budget/dBpi. The total budget comes from the
and tuned. The constraint format to enter is “50 MIL:5 MIL”. One relevant standards like IEEE802.3xx, or SFF8418. For
member of the MGrp can be the main signal (like strobe on a DDR4 synchronous, asynchronous, source-synch and clock forwarding
byte lane), so for that one we can override the inherited value and buses the rule values are either obtained from the chip vendor’s
type in text “TARGET”. datasheet or design guide document, or we calculate them using a
PinPairs and Matched groups, as well as their associated pre-layout setup/hold timing analysis calculator spreadsheet, like:
https://www.buenos.extra.hu/iromanyok/PCB_Timing_analysis.xls
design rules could be created in the constraint manager, Rel Prop
Delay worksheet. We can create PinPairs from nets (rightclick>
Typical high-speed objects and constraints:
Create), and then select those PPr’s and create a MGrp for them
Case Objects Constraints entered in CM
(rightclick> Create). To speed up PinPair creation, we create all
Differential Pair point- •DPr • CM> El> Rout> Diffp (DPr)
useful pin pairs on one net, for example CPU-DRAM0, CPU-
to-point signal •ECSET • CM> El> Rout> Wir> Paral.
DRAM1…, by selecting the first net name rightclick> Create>
(DPr)
PinPair, select the CPU refdes on the left, all DRAM refdes on the If >8Gbps:
right, OK. This creates as many PPr’s as the number of memory • CM> El> Rout> TotalE (DPr)
chips on the net. For a DDR4 mem-down fly-by address bus we • CM> Prop> Comp> Pin>
would have several PPr’s on a net, for the data bus we would have Manu> backdrill (comp pin)
one PPr on a net. Next, we create a separate MGrp for each new • CM> Prop> Net> Gen>
PPr by clicking on the PPr then rightclick> Create> MGrp, give Backdrill (Net)
it a name, redo for all PPr’s on the net. Then on the net name again Single-ended Sync/ •ECSET • CM> El> Rout> Wir> Paral.
rightclick> Create> Electrical CSET, give it a name. Then click Async point-to-point (Net)
the ECSET column for the net and select the new ECSET’s name bus with min/max len. • CM> El> Rout> Minmax
from the drop-down menu. Then select all other net names that we (Net)
wanted to be in the same group, click the ECSET column and select
the new ECSET from the drop-down menu. It creates the same
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 Single-en Source-sync •PPr • CM> El> Rout> Wir> Paral. and change to the alternate layer
point-to-point bus •MGRP (Net) (shown on the options panel).
with matched lengths (1/lane) • CM> El> Rout> Relat (MGrp We can slide traces by selecting
•ECSET of PPr)
the slide menu first then
(1/lane)
clicking the trace. First we route
Multi-lane Point-to- •DPr • CM> El> Rout> Diffp (DPr) all traces with plenty of spacing,
point diff SERDES •MGpr • CM> El> Rout> Wir> Paral. then we tune them later. We
bus •ECSET (DPr) might want to hide most
(1/port) • CM> El> Rout> Relat (MGrp connection lines (ratsnests), to
of Nets) see clearly: Display> Hide
If >8Gbps: Rats> All, then enable a few on
• CM> El> Rout> TotalE (DPr) the PCB drawing after selecting
• CM> Prop> Comp> Pin> the Display> Show Rats>
Manu> backdrill (comp pin)
Component or net.
• CM> Prop> Net> Gen>
For several constraints (physical, spacing, diffp) there is a
Backdrill (Net)
Single-ended Sync/ primary and a neck-down width/gap. During routing, especially
•PPr • CM> El> Rout> Wir> Paral.
Async multi-drop bus •ECSET (Net) while under a BGA, we can rightclick> Neck Mode to switch
(1/bus) • CM> El> Rout> Minmax to/from the neck-defined width/gap. We could also use regions.
(PPr) Length tuning: We can delete then re-route trace segments,
auto-meander traces with the delay-tuning button , or slide
Single-ended Source- •PPr • CM> El> Rout> Wir> Paral.
them (select, drag) to increase/decrease the signal length. While
sync multi drop bus •MGrp (Net) starting the tune, after pressing the tuning button, the Options panel
(1/chip) • CM> El> Rout> Relat (MGrp displays meander pattern and parameters. The tuning can be ended
•ECSET of PPr) by the rightclick> Done, cancel or Next. Single-ended and diff
(1/lane) traces are both tuned by the same tuning button. We can just add
phase tolerance tune bumps by enabling rightclick> Single
Diff multi drop bus •DPr • CM> El> Rout> Diffp (DPr) Trace Mode, or disabling it and tune the lane-to-lane matching.
(like RS485) •PPr • CM> El> Rout> Wir> Paral. We can also do phase tolerance matching using Route> Phase
•MGrp (DPr)
Tune (instead of Route> Delay Tune). The first thing for phase
(1/chip) • CM> El> Rout> Relat (MGrp
•ECSET of PPr) tolerance is to twist at the pads, only after that we use meanders.
(1/bus) The Route> Auto-Interactive tunes multiple selected signals.
Mixed SE/Diff multi- •DPr • CM> El> Rout> Diffp (DPr)
drop matched lengths •PPr • CM> El> Rout> Wir> Paral.
•MGrp (Net)
(1/chip) • CM> El> Rout> Relat (MGrp
•ECSET of PPr)
(1/bus)

Single-ended Source- •PPr • CM> El> Rout> Wir> Paral.

sync tree topology •MGrp (Net)
(one/chip) • CM> El> Rout> Relat (MGrp
•ECSET of PPr)
(1/lane) The Allegro on-screen Length Meter/ Gauge pops up during
sliding/tuning the traces, which measures the signal lengths of the
currently edited trace in real time, relative to all active constraints.
They also need net classes, for spacing and physical/width
The CM also shows all signal object type lengths as a table, but
constraints sets (PCS and SCS), if impedance controlled.
first we have to enable it in CM>Analyze> Analysis Modes>
Electr> RelativeProp =on, all others we need also on, then
5. Interactive High-Sp Route OnLineDRC =on, OK). Then we can measure by selecting cells in
During interactive routing, the Options panel should be visible, CM and rightclick> Analyze. Must have a constraint entered.
that allows us to alter routing parameters like width, active layer, Package and via length is only included in PinPairs, not in nets.
angle, corner style and vias. We can manually route traces by left Traces can be pass/fail colored using the Route> Timing Vision.
clicking the routing mode button , then clicking a pad, then start
pulling the trace. During routing the right click menu offers
important commands, like cancel, done, oops (undo the last click),
next (net), snake routing mode, switching between “single trace
mode” (twist one leg of a diffpair) and default diff routing. For
diffpairs it will automatically use diffpair routing, unless we click For long 10Gig+ SERDES signals, we use wavy routing and
single trace mode. While routing we can doubleclick to place a via odd-angle routing, to mitigate fiber weave effect. In Allegro angled
8
routing is done by changing the Line Lock angle to “off” instead button then OK. The BD antipad size is set in the footprint’s
of 45deg, on the Options panel before routing. Click the route padstack design. BD always starts from (Top or) Bottom, and ends
button, then options, then click the trace. Wavy routing is achieved one layer away from our routing MNC layer. We should enable the
by enabling the [route offset] checkbox. We can also do it by “drill labels and backdrill holes” in setup> User Parameters.
Route> UnsupportedP> Fiber Weave Effect> Add zigzag. This will put a B40-28-27 style text on it, meaning layer 40 to 28,
Curved routing is enabled by selecting arc instead of line, on the with layer 27 being MNC. Once the design is done, we have to go
Options panel Line Lock section. SERDES links should always use back and press the backdrill button again, to update (depths, drills,
the curved corners. We can enable curvy snake fanout under offset- voids and keepouts). Then we manually review it: Enable one
grid hex-BGAs, while routing we can right click>Snake Mode to routing layer to be visible, then also enable a layer
enable it. Intel-style “tabbed routing” can be added to memory manufacturing/ncbackdrill-x-y, then check if every high-speed
traces to lower their impedance in the escape route pin field, using: diffpair ends with a BD symbol. A separate NC drill file will be
Route> Unsupported Prot> Tabbed Routing> Generate. generated for each BD depth. Note that the CM> Electrical>
Routing> Wiring> Stub Length is not for via stubs, but for daisy
chain traces. For press-fit connectors we have to set a property to
prevent drilling into the minimum barrel length area, in CM>
For low-cost and aerospace boards teardrops are used, that we Properties> Component> Pin> Manufacturing> backdrill
enable: Route> Gloss> Param> Fillet> Dynamic=on> OK. column. Find refdes, select multiple pins, then exclude= “exclude
Pin swapping might be required on many designs, if a parallel top”, and enter MBL value from connector datasheet. We also get
bus seems un-routable due to connection-line (ratsnest) crossings. route keepouts/antipads on plane and signal layers, around
With hard chips like CPUs the datasheet might tell us which pins backdrilled vias, as described in the section about voids.
can be swapped with which (within groups), while with FPGAs we The CM lists all the constraints and related DRC violations
can likely swap most signals (maybe except the diffpairs that must with details (e.g., deviation from preferred length). We have to
be on diff capable pin pairs), if we also update the FPGA pinout select several cells, rightclick> analyze. The numbers in the actual
file. In Allegro, once we are done with the escape routes and some fields appear green if they meet the constraints, or red if there is a
long distance routes from both ends, then we can set up swapping. failing object that does not meet it. We can browse by category. If
we fix a violation then it disappears from the list. We can also see
DRC violations in the DRC report, and in the drawing as markers.

Steps for swapping in Allegro: In the schematics symbols the 6. Signal Integrity
pins have to be allocated pin groups. In the Allegro PCB editor, To ensure good signal integrity, we utilize
Place> Swap> Pins, then select 2 pins to swap, swap group high-speed design techniques, as explained in the
members will be highlighted. Repeat until all look good, book titled “Complex Digital Hardware Design”.
rightclick> Done. Then either we back annotate the data into the It also provides guidance about architecture,
schematic, or generate a swap report (Tools> Quick Reports> debugging, simulations, measurements, con-
Pin Swap Report) and manually update the schematic (by editing straints, timing-based trace length calculations,
net labels or off-page) and export new netlist from SCH-to-PCB. trace impedance control, crosstalk control, ground returns, stackup
If we have used bus symbols, then implementing swaps in design, materials, backdrilling, via impedance optimization, loss
schematic might be harder. To help it, we can create separate net budget calculations and insertion loss control techniques.
swapping pages, where 2 offpage symbols are shorted to the same Most SI simulations should be done in proper external tools,
wire, the left side goes to one component, the right to the other, for example pre-layout and decoupling in Keysight ADS, or post
with similar signal names but with a prefix. The bus offpage layout in Hyperlynx, HFSS or Simbeor. Power plane DC voltage
(OUT[1:2]) on the device page splits to separate net offpage drop can be simulated with the Allegro's built-in (Sigrity) IR Drop
symbols (OUT1) on the swap page. Then swaps can be analysis, that requires a separate license. Might need to File>
implemented by editing the signal names on the off-page (=select Change Editor, Logic> Identify DC Nets, then run: Analyze>
multiple, rightclick> edit properties). Then copy the table with Workflow Manager> IR Drop Workflow, mode=VRM/S,
CTRL+insert, paste it in Excel, edit there, copy, then back paste Options, setup VRMs/sinks, Start, IRD Table.
with shift+insert. We will have something like this: OUT1>--- For differential SERDES links operating at 8Gbps/lane or
<COUT2 and below it OUT2>---<COUT1. above we need to ensure that the impedance of the via structures
Backdrilling is set up in 2 places together: First the stub also comply to the target impedance requirement, for example 93
constraint is created in CM> Properties> Net> General Ohm diff for backplane Ethernet. We do this by recreating the via
Properties> Backdrill, by typing in the value for the SERDES nets structure in HFSS or Simbeor, optimize the dimensions (via-to-
that need it. The maximum value means any stub longer than that via spacing, via diameter, and void shape/size), then adjusting
will be backdrilled. The constraint is set slightly longer than what them until the TDR response is flat enough, then replicating the
we write in the fab notes. Up to 64Gbps we don’t backdrill from structure in Allegro layout to match the dimensions.
bottom to L(N-2) routes, that results in a 2-layer deep stub
(6…16mil), so we set the constraint slightly longer than that. In the
second step we open the Manufacture> NC> Backdrill Setup,
and we create all backdrill layer pairs automatically, set up BD
oversize (diameter) and other parameters, then press the Backdrill 
9
 lane to lane using interactive length tuning. We can monitor our
7. Typical Examples progress on the popup length gauge or in the CM. Finally, we run
analyze in CM and verify all objects green.
7.1. PCIe Gen4 SERDES bus design We also need to set up backdrilling. In the Manufacture>
The lane-to-lane matching groups setup depends on the NC> Backdrill Setup, we define all BD depths. Then we define
architecture. If we have an AC-cap then it creates a short segment the max stub length related constraints on nets or net class in CM>
between the chip and Properties> Net> General Properties> Backdrill, and CM>
the cap, and a long Properties> Component> Pin> Manufacturing> backdrill
segment between the column.
cap and the other chip. We should add a net name on both sides in
the schematic. 7.2. DDR4 Memory-Down design
If we had a DC coupled Hyper Transport bus, then one MGrp The „Memory-Down” is the design technique where we design
would be enough. If our PCIe link is between two chips on the same a complete DIMM memory on to the motherboard, so we don’t
board, then we have AC-caps on both RX and TX signals on our need to use DIMM sockets, all the memory chips will be soldered
board. So, we would need 2 MGrp’s, one group for the long down. The design rules come from CPU design guide documents.
segments including both TX and RX signals, and the other group We have to create objects for the address bus signals: A net
is for the short segments. If we are designing a PCIe link that passes class for trace width rules, PinPairs for each CPU-to-DRAMn
through a connector (a motherboard, add-in card or backplane component pair on every address bus signal, one MGRP+ECSET
system), then our constraints will only be created for the segments (match 5mil) for each CPU-to-DRAMn component pair
that exist on one board. This case we likely have an AC cap only (containing address and clock PPr). Then we enter the width data
on TX or on RX on our board, and now we have 3 types of diffpairs for the net class in CM>Physical, and match-length data for each
(short to cap, long from cap, very long), so we need 3 MGrp’s. MGRP. If we had 25 signals and 4 DRAM chips, then we will have
4*25=100 PinPairs and 4 MGRPs. The PPr/MGrps/ECSETs
creation is done at once, first we manually create all PPr’s on one
net, then MGrp’s for all the new PPr’s, then one ECSET for the
net, then select all other nets, apply the same ECSET, the rest is
We also need to calculate an insertion loss budget at the Gen4 auto created. Finally enter delta, tolerance and TARGET values.
16Gbps speed. We have a budget of 25dB@8GHz. If our PCIe link The clock needs diffpairs created, and a net class for trace
is on one board, then we have the whole 25dB available, but if it width/impedance and diffpair parameters. We have to create
goes through a connector, then we only have a portion, budgeted PinPairs for the clocks too, while we are creating them for address
between 2 boards. Let’s assume we have 70% available for the bus, and they will go into the MGrp of the address bus.
motherboard, that means 25dB*0.7=17.5dB. We have to obtain a The data bus: Since we have DQS diffpairs and DQ SE signals
fabricator and material related dB/inch loss data from our SI team in one matched group, we have to create PinPairs for every signal,
or fab vendor, let’s say we got 2dB/inch@8GHz. With 17.5dB and MGrp+ECSET (match 5mil) for every lane. We use net classes
budget and 2dB/inch we can have our max total etch length only for width/impedance. We will need one net class for DQ width
17.5dB/2=8.75”. On our motherboard we have 3 groups (enter and one for DQS width. We will need as many MGRPs and
values for several DPr’s), the longest one can have 8.75” max set ECSETs as the number of data byte lanes (containing DQ and DQS
in the CM> Electr> Routing> Total Etch Length worksheet, XS). These are created the same way as the address bus groups.
while the other 2 groups have to share that 8.75”, so one would
have let’s say 3” max and the other 8.75-3=5.75” max.
The diffpairs need setting up. We create the diffpairs in the
CM> Electr> Routing> Differential Pair, and 3 net classes. Every
separate refdes-to-refdes interface is a separate net class. The
impedance-driven width is in CM>Physical (PCS on nets). The
_P/_N phase tolerance matching is typically 5mils, that we set in
CM> Electr> Routing> Differential Pair in ECSET applied on
the diffpairs. We also set up a constraint for crosstalk control on all
PCIe signals with CM> Electrical> Net> Routing> Wiring>
Parallel-column. For any reference clocks, we only need diffpair
rules and phase tol matching in ECSET, and PCS trace width.
Embedded clock interfaces (like PCIe or HDMI) usually have
De-Skew circuits built-in, so they only need loose lane-to-lane
matching, maybe within 2 inches. Clock forwarding interfaces
(e.g., Hyper Transport 1.0 or XGMII) do tight matching, maybe
within 5 mils. We apply this in CM> Electr> Routing> Min/Max
Propagation Delay, on each MGrp-of-DPr’s separately.
During routing, we route all diffpairs using interactive routing
loosely. Then we match the phase tolerance within each diffpair by
twisting first then single ended tuning. After this we match them

10