UNIT-IV

Introduction to A/D & D/A convertors & their types, sample and hold circuits, Voltage to
Astable,
Frequency & Frequency to Voltage conversion. Multivibrators :Bistable, Monostable,
Schmitt trigger, IC 555 & Its applications. TTL, PMOS, CMOS and NMOS logic. Interfacing
between TTL to MOS.
ANALOG TO DIGITAL CONVERTER (ADC):
Figure 4.1 shows the general block diagram of ADC. An ADC takes an analog input voltage and
input.
after acertain amount of time produces a digital output code that represents the analog
Timing for operation is provided by
Analog the input clock signal.
+Start
Input CNTL Control (CNTL) unit contains the logic
VA UNIT +Clock circuitry for generating the proper
sequence of operations in response
Comparator Endof to the start command, which initiates
conversion
the conversion process.
D/A Regist OPAMP comparator has two analog
VAX Conve er inputs and a digital output that
rter switches states, depending upon
which analog input is greater.

Digital result

Figure 4.1: General block diagram of ADC

a rate determined by the clock, the
Operation: START command pulse initiates the operation. At
stored in register. The binary number
control unit continually modifies the binary number that is
DAC. The comparator compares VAx with V .
in register is converted into analog voltage, VAx, by
VAx > VA, by atleast an amount equal to
When VAX < VA, comparator output stays HIGH. When
stops the process of modifying the
threshold voltage, the comparator output goes LOW and
Va.
register number. At this point Vax is close approximation withequivalent of VAX, is also the digital
the digital
The digital number in the register, which is
system. The control logic activates the
equivalent of VA, within the resolution and accuracy of the
complete.
end of conversion signal, when the conversion is

DIGITAL RAMP ADC (COUNTER TYPE ADC):

ADC.
Figure 4.2 shows the diagram of digital ramp
Analog
Clock
Input. EOC
VA Start
Conversion
Comparator complete.

VAX
D/A
Conve
H Count
er
EOC
Counter
stops
counting.

rter
(DAC)
Time
Digital Yesult Start
Figure 4.2: Digital Ramp ADC
AND
Operation: Assume that Va iS positive. START pulse is applied to RESET the counter to 0 and
gate is disabled. With all 0s as its input, DAC output will be VAx= 0v. Since VAx < VA Comparator
Output, (EOC), is HIGH, When START is LOW, AND gate is enabled and clock pulses get through to
the counter. As the counter advances, DAC output, Vax, increases one step at a time. This
continues until Vax > V, by an amount equal or greater than threshold voltage (typically 10 to
100uv). At this point comparator output, (EOC), goes LOW and counter stop counting. The
conversion process is now complete and the contents of the counter are the digital representation
of Va. Counter will holdthe digital value until the next START pulse initiates a new conversion.
Conversion time, Tc, is the interval between the end of the START pulse and the activation of the
(EOC' output. Tc depends upon VA.
For N-bit converter: TCima) =(2-1) clock cycles. Tcavg) = Tc(max)/2 clock cycles.
Major disadvantage of digital ramp ADC is that it is not suitable for where the repetitive A/D
conversion of a fast changing analog signal occurs. In this method the conversion time essentially
doubles for each bit that is added to the counter.

SUCCESSIVE-APPROXIMATION ADC (SAC):

Analog Figure 4.3 shows the general block diagram
Start of SAC. Basic arrangement is similar to
Inputt
VA
Comparator
CNTL
UNIT +Clock
digital ramp ADC except that, instead of
counter SAC uses a control register. The
control logic modifies the contents of the
+End of
conversion register bit by bit until the register data are
the digital equivalent of the analog input VA
D/A Control within the resolution of the converter.
VAX Conve Registe Most widely used ADC. Circuitry is more
rter complex but much shorter conversion
time

Digital result
Figure 4.3: General block diagram of SAC

Operation of 4-bit SAC using DAC Sstep size of 1Volt and VA= 10.4 Volts:
MSB VAX
From Q4 DAC
CNTL I Regis Q3 Step Conversion
size=lv VAx 11
logic ter Q2 tompleted
10
Q1 LSB 9

VA=
To CNTL logic
TO T1 T2 T3 T4 T5 T6 Time
Figure 4.4: 4-bit SAC using step size 1V
Operation: Figure 4.4 shows the 4-bit SAC using DAC step size of 1Volt. Let assume that the
analog input is Va=10.4V.
At time TO, VAx = 0V, i.e VA > Vax, comparator output is HIGH. Control logic clearing all bits so,
Q3=Q2=Q1=Q0=0 ie [Q]= 0000.
At time T1, control logic (CNTL) sets MSB = 1. So (Q)= 1000. This produces Vax = 8V. Since, VA >
VAX, Comparator output is HIGH. This HIGH tells the CNTL logic that the setting of MSB did not
make Vax exceeds Va, S0 that MSB is kept at 1.
Now, CNTL logic proceeds to next lower bit, Q2. Q2=1 to produce [Q) =1100 and VAx =12V at time
T2. Since Vax >Va, comparator output goes LOW. The value of Vax is too large, so CNTL logic then
clears register contents back to 1000 ie VAX =8V. Thus, at T3, VAx =8V.
 1010 and Vax = 10V.
At time T4, CNTL logic sets the next lower bit Q1 = 1, ie (Q) =
With VA > VAX, Comparator output is HIGH and tells the CNTL logic to
keep Q1 set at 1.
= 1011 and VAX = 11V. Since VAx
Final step, time TS, CNTL logic sets the next lower bit Q0 =1 ie (Q)
and the CNTL logic clears back Q0 to 0
> VA, COmparator goes LOW to signal that VAx 0S too large,
at time T6.
conversion is complete and the CNTL
At this point, all of the register bits have been processed, the
iS now in the register. So,
logic activates (EOCY' output to signal that is digital equivalent of VA
digital output for VA = 10.4V is (Q) = 1010.
it to 1, decides
Conversion time,Tc, for SAC: The control logic goes to each register bit, set takes one
processing of each bit
whether or not to keep it at 1, and goes on to the next bit. The
cycles.
clock cycle, so that the total conversion time for an N-bit SAC will be N-clock
Tc = Nx1 clock cycles

than other types

FLASH ADC: It is the highest speed ADC, but its circuitry requires much more
requires 255 comparators.
ADC. Example: 6-bit flash ADCrequires 63 analog comparators; 8-bit

3-Bit Flash Converter:

Figure 4.5 shows the 4-bit flash converter.

10V

3KO C7

7V MSB
1K0S C6
C

6V
1KOS Priority
C5 Encoder
Digital
5V B output
1KO C4

1KOS 4V
C3
A
3V
1KO2 C2

1KQ
2v
C1

1KO Analog
Input
VA Figure 4.5: 4-bit Flash Converter

divider set up a
Operation: 3-bit flash converter has a resolution (step size) of 1V. Voltage
corresponding to 1v
reference levels for each comparator, so that there are seven levels
input of
(weight of LSB), 2V, 3V, 4V, SV, 6V and 7v (Full Scale). Analog input is connected to other
each comparator. 3-bit flash converter ADC operation table is shown below:
 Analog In Comparator outputs DigitalOutputs
(VA) C1 C2 C3 C4 C5 C6 C7 C A
OV -1V 1 1 1 1 0 0
1V - 2V 0 1 1 1 1

2V -3V 0 0 1 1 1 0 1
3 V- 4V 0 0 0 1 1 1 1 0
4V - 5V 0 0 1 1 1 1 0
5V - 6V 0 0 oloo
0 0 1 1
6V - 7V 0 1 1 1 0
>7V 0 0 0 0 1 1 1
TABLE of 3-bit Flash Converter ADC
With VA < 1V, all comparator output is HIGH. With VA > 1V, one or more comparators output will
be LOw. Comparator output is feed into active lowpriority encoder that generates a binary
output coresponding to the highest numbered comparator output, that is LOW. For example, if
VA is between 3V 4V, output C1, C2 and C3 will be LOW and all others are HIGH. Priority encoder
willrespond only tothe LOW at C3 and willproduce binary output CBA =011.
Conversion Time, Tc of flash converter: Flash converter uses no clock signals. Conversion time
depends only on the propagation delays of the comparators and encoder logic. So, flash converter
has extremely short conversion times.

ADC USING VOLTAGE TO FREOUENCY CONVERTER:

Figure 4.6 shows the ADCusing voltage to frequency converter.

Monostable
Multivibrator

N-bit
Vout
count
Vin + Display
er
-Vref
V-F Converter
Figure 4.6: ADC using V-F converter

Voltage to frequency ADC does not require DAC. Instead it uses a linear voltage controlled
oscillator (VCO), that produces an output frequency that is proportional to its input voltage. The
analog input (Vin) that is to be converted, is applied to the VCO to generate the output frequency.
Thisfrequency is fed to the counter to be counted for a fixed time interval (VEN). The final count is
proportional to the value of the analog voltage. Circuit diagram of ADCusing V-F converter shown
in figure.
Operation: The Vin is applied to an integrator whose output is applied at the inverting terminal of
acomparator. Non-inverting terminal is connected to -Vref. When switch S is open, Voltage Vout
decreases linearly with time. Thus AND gate is disabled as long as Vout < Vref. As soon as Vout =
Vref, the output Vc becomes positive, enabiling AND gate and hence counter starts
When the switch S is closed, the capacitor discharges and thereby counting.
returning integrator output,
Vout, to zero. After the delay time of multivibrator the switch S is again
the
open and Vout starts
decreasing again and ADC repeats its function.
 FREQUENCY TO vOLATGE cONVERTER (INTEGRATING TYPE:
Block diagram of a voltage to frequency converter is shown in figure4.7. The analog input is
Ppled to an integrator.The integrator produces a ramp signal whose slope is proportional to the
input voltage signal.

R
Comparator Counter
Input Digital Output
Voltage Integrator

Pulse
Generator
Pulse Trigger O/P
Output of Integrator, a ramp Signal
*Zero Level

Trigger Level

Time between two

threshold levels
Figure 4.7: Frequency to Volatge converter

When this ramp signal reaches a preset threshold voltage level, atrigger pulse is produced. Also a
current pulse is produced which discharges the capacitor of the integrator, after which a new
ramp is initiated. The time between successive threshold level crossings is inversely proportional
to the slope of the ramp. Since the slope of the ramp is proportional to the input analog voltage,
hence the frequency of output pulses from the comparator is directly proportional to input
voltage. The output frequency can be measured with the help of digital frequency meter.

SAMPLE AND HOLD CIRCUIT:

When an analog voltage is connected directly to the input of an ADC, the conversion process can
be affected if the analog voltage is changing during the conversion time. This stability of
conversion process can be improved by using a sample-and-holdcircuit to hold the analog voltage
constant while the A/D conversion is taking place.
Digital control (CNTL)input CNTL= 1,Sclosed= sample mode
CNTL=0, S open+ hold mode

|TÍ ADC input

Analog
Input
VA

Figure4.8: Sample and Hold Circuit

Sample and hold circuit as shown in figure4.8, contains a unity gain buffer amplifier Al that
presents a high impedance to the analog signaland low output impedance that can rapidly charge
the hold capacitor, Ch. Capacitor Ch is connected to output of Al when digitally controlled switch
is closed. This is called sample operation. The switch is closed long enough for Ch to charge to the
current value of the analog input.
When switch opens, Ch willhold this voltage so that the output of A2 willapply this voltage to the
ADC. The unity gain buffer amplifier A2 presents high input impedance that will not discharge the
capacitor voltage during the conversion time of the ADC.
DIGITAL TO ANALOG CONVERSION (DAC):
DAC is the process of taking digital code as input and converting it to a voltage or current that is
proportional todigital value.
Vref 15V TABLE of 4-bit DAC:
Inputs Output
MSB
D C B A Vout
Digital D DAC
Vout 0
Inputs JC 0
B Analog O/P 00 1 1
0 0 0 2
|A LSB 0 0 3
0 1 0 4
Figure 4.9:Block diagram 4-bit DAC 0 1 0 5
0 1 1 6
1 7
0 0 0 8
0 0
1 0 1 0 10
0 1 11
1 12
1 0 1 13
1 1 14
1|1 1 15

From the block diagram as shown in figure 4.9 of 4-bit DAC ,Vref as input is used to determine the
full scale output or maximum value that DAC can produce. For each input number, DAC output
voltage is unique value. In general, Analog output (Vout) = K x Digital Input; Where, Kis
proportionality constant. In above block,DAC has K=1, so that, Vout =1 xDigital Input.
Example: For digital input (1100)2 =(12)10, we obtain Vout =1 x 12 = 12V.
RESOLUTION OR STEP SIZE OF DAC: Resolution of DAC is defined as the smallest change that can
occur in the analog output as a result of achange in the digital input. Resolution is always equal to
the weight of the LSB and also referred to as step size, since it is the amount that Vout will change
as the digital input value is changed from one step to the next.
Resolution= K= Ass /(2^- 1) where, As is analog full scale output; n is the number of bits
% Resolution = (Step size / As ) x 100 OR %Resolution = (1 /Total no. of steps )x 100

DAC USING OP-AMP SUMMING AMPLIFIER WITH BINARY WEIGHTED RESISTOR:

Resistor R1 = 1KQ
Resistor R2 = 2KQ
MSB Resistor R3 = 4KQ
Digital Resistor Rr = 8K2
input 0v
or 5V Vout

LSB
Figure4.10: OP-AMP as Summing Amplifier

From the figure4.10 , opamp as summing amplifier, inputs A, B, Cand Dare binary inputs that are
assumed to have a values either 0V or 5V. OP-AMP as summing amplifier, which produces the
weighted sum of the input voltages. So that, Vout =Vo+ 2 Ve+ 1/4 Va+ 1/8 VA)
 So, the summing amplifier output is the analog voltage which
represents a
digital inputs. The resolution of this DAC using opamp as summing amplifier weighted sum of the
using binary
weighted resistor, is equal to the weighting of the LSB, which is 1/8x5 =0.625V.

DAC USING R/ 2R LADDER CIRCUIT:

In R/2R Iladder circuit, the resistor values span arange of only 2 to 1.

+Vref

2R S2R S2R 2R 2R

2R

R lout
R R
Vout
B3 B2 B1 BO
(MSB) (LSB)
Figure 4.11: R2R Ladder Circuit
In R/2R ladder network as shown in figure 4.11, only two different values are used, R and 2R.
Current lout depends on the positions of the 4- switches and the binary inputs B3, B2, B1 and BO,
which controls the states of the switches.
Vout =(-Vref / 8) xBwhere "B value of binary input from 0000 to 1111.
Example: Assume the Vref = 5V. What are the resolution and full scale output of this R/2R
converter?
Solution: Resolution is equal to weight of LSB. Suppose, [B)= 0001 = (1),0
Resolution = (-5V x 1)/8 = -0.625V. The fullscale output occur for [B]=1111 =(15)10
So, full scale output = (-5V x 15)/8 = -9.375V.
BISTABLE MULTIVIBRATOR:
If both the states of a multivibrator are stable i.e. the circuit which is in a particular state
continues to remain in that state until it is triggered from an external source to change the state.
Flip Flops are bistable multivibrator circuits as shown in figure 4.12.
Vcc
Input S

Rc
Vcc
Output
of T1
R -Ve8
0
R2
Vcc
Output
R of T2
Trigger input 1 Trigger input 2
Figure4.12: Bistable Multivibrator

Transistor TË and T; are npn transistors and are resistively crosscoupled with each other. Qand Q'
are outputs. Rc is the collector resistance. C, and C, are commutating capacitors, to fast turn OFF
and ON of two transistors (C, for T, and C, for Ti). Supply -Vo and resistor Rz are used to keep
the base of the transistors at negative in one state and in other state provides large base current
to drive the transistor into saturation.
Operation: When supply is ON, say T, is ON, So, Vc1 =0v, the base of T, is connected to Vc, so T; is
OFF. This makes V= Vc since base of T, is connected to Vez, S0 T, is ON. This is the first stable
state (ie. T;=ON and T,=0FF ie. Q=1 and Q'=0).
To change the state of transistor TT,a positive pulse is applied at the base of T2. The OFF transistor
T2 will be forced to turn ON (to > ton ie. Pulse width should be greater than turn ON time of
transistor). Thus Ve is forced to 0v. Since base of T, is connected to Ve2, so TË is OFf. This is the
second stable state (ie. T,=0FF and T,=ON ie. Q=0 and Q'=1).

MONOSTABLE MULTIVIBRATOR:
Monostable multivibrator as shown in figure 4.13 has one stable state and the other one is not
stable (quasistable).It is also called as one-shot multivibrator. Transition from stable state to quasi
stable state is done by an external trigger pulse. After transition from stable to quasi stable state,
the multivibrator remains in the quasi stable state for a definite period of time, decided by
comoponents R and C, and then returns to the stable state automatically.

Vcc Trigger
I/P
Rc C ER Rc
Q Vcc Output
tp
T T of T1
0
R2 Va8
Vcc
Output
of T2
Trigger input
Figure4.13: Monostable Multivibrator

In this circuit the base of transistor T, is capacitively coupled to the collector of Ti, while the base
of T, is resistively coupled to the collector of T2.
Operation: When no trigger pulse applied, T, is ON, a proper base drive through Vcc and R to the
base of T2. So, Ve2 = 0v. TË is OFF, because of resistively coupled of base TË with V(Ve1 = Vcc). At
the instant when T;is ON, capacitor C charged towards Vce through Re. This is the stable state of
multivibrator.
When a sufficient positive trigger pulse is applied to the base of T, T, is ON, so V = Ov. Now the
capacitor discharges through TË and R. Thus discharge current through R creates a negative
potential at the base of T2. Thus T, is OFF as long as the voltage drop across R is negative. This
condition is quasi stable state. When the capacitor fully discharges the negative voltage at the
base of T; reduces to zero and Vee nowdrives the T, ON, So Vz = 0v. So, TË=OFF and Vei=Vec- This is
the stable state andcircuit remains in the stable state until the next triggerpulse is applied.
Time duration of quasi stable state or the pulse width: t, =0.693(R.C)

ASTABLE MULTIVIBRATOR:
Astable multivibrator as shown in figure 4.14,has no stable states but has two quasi stable states.
 triggering ,therefore
The output oscillates between two quasi stable states without any external
collector of transistors is a
this circuit is also called as free running multivibrator. The output at the
square wave, therefore also called as square wave generator.

Vcc

Ra C1 R1 R2 Rcz
Q Vcc Output
of T2
T, T;

Vcc Output
Figure4.14: Astable Multivibrator -of T1

and
OFF due to circuit unbalance. So, Ve = 0v
Operation: Initialy assume that T, is ON and T, is Meanwhile C; which was charged to
ON, C charges towards Vcc through Rez.
Ve2 = Vce. Since TË is
was ON willdischarge through TË and R1. This makes the potential at Vs2 negative and
Vce when T; current provided by Vc through R2. The charging
causes T,to turn OFF. T, is kept ON by the base
through Re2 has reduced to zero. The time duration for which T; is held OFF is
current of C,
base drive from Vc through Ri, then Ci gets
determined by the R1.C,. Once T, turns ON due to the
discharges through T; and R2 making Ve1 negative
charged through Rei and T2. At the same time Cz the time
that T, is turned OFF, thus Ve = Vcc. TË is held OFF by the discharging current for
so discharge through TË and then Cz recharges
duration Rz.Cz. After this TË turns ON and allow C, to
through T,.
SCHMITT TRIGGER:
the circuit remans in the active region for a
Indigital circuits, fast waveforms are required so that
the effects of noise or undesired parasitic
very short time (of order of nano seconds) to eliminate
time of the input waveform is long,
oscillations causing malfunction of the circuit. Also if the rise
circuits which ca convert a slow-changing
it requires a large oupling capacitor. Therefore
time) are required. The circuit
waveform (long rise time) into a fast-changing waveform (small rie
which performs this waveform is known as Schmitt trigger.
LOW or HIGH. From the figure
In a Schmitt trigger circuit, the output is in one of the two levels, input passes
4.15,when the input voltage is rising, the level of the output changes when the
voltage is falling,
through a specific voltage Vr. (upper triggering level). Similarly, when the input
V- (lower
the level of the output changes when the input passes through a specific voltage than
triggering level), the level of the output changes. V. (upper triggering level) is always greater
V-(lower triggering level). The difference of these two voltages is known as
hysteresis as shown
in figure 4.16.
 4+Vo
+Vo(sat.)
V Input
-Vi
+Vo
Output -Vo(sat.)
0
LTL UTL
-Vo -Vo
Figure4.16: Hysteresis Loop
Figure4.15: Schmitt Trigger l/P &o/P Waveform

Schmitt Trigger circuits:

From the figure 4.17 of transistor
Vcc Schmitt trigger, resistor Ri and RT are
voltage divider resistors.
Rci R1
Rcz
Ve1
T

RE
Vi R2

Figure4.17: Transistor Schmitt Trigger

Operation: When Vi = 0V, when circuit is ON, T, is ON (Ve2 = 0V). As T is ON, there is a voltage
due to which T:
drop across R2. This drop acts as a reverse bias across emitter-base junction of T;,
saturation(Vez =
is OFF (Vi = Vc). This Vee is coupled to base of T; through R1. So T, is ON ie. In
VCE(sat) = OV).
Vi >
When Vi = applied AC input, and approaches till it crosses Vr. (upper triggering level). Now,
through resistor
Vr. (upper triggering level), TË conducts. So, V = 0V. This fall of voltage is coupled
= 0FF ie. Ve =
Ri to the base of T2, which reduces its forward bias voltage. So, T, = ON and T;
below V- (lower
VCEISat) and Ve2 = Vcc- The TË continues to conduct till the input voltage falls
junction of TË is reverse
triggering level). When Vi > V- (lower triggering level), base-emitter
biased. So, TË is OFF. So, Ve1 = Vee and V2= VcE(sat):
IC-555 TIMER:
Figure 4.18 shows the
Control functional block
Vcc Discharge Threshold Voltage diagram of IC-555
P8 7 6 timer. It consists of a
voltage divider
network, which
provides bias voltage of
Comparator-1 (2/3)Vcc to the inverting
input of the
(2/3)Ve R
comparator-1 and
(13)Vcc to the
E/E
(13)M. S non-inverting input of
Comparator-2 the comparator-2.
These two voltages fix
Vret the Comparator

Output threshold voltage and

also determine the
2 3 4 timing interval.
Ground Trigger Output Reset Electronically, possible
to vary time by
Figure 4.18: Functional block diagram of IC-555 Timer applying a modulation
voltage to the control
voltage input (pin-5).
If no such modulation is proposed, a 0.01uf capacitor is connected between control voltage and
ground to bypass noise and ripple from supply. The other two inputs to the comparator are
threshold and trigger inputs. The output of these two comparators, SET or RESET the flip flop,
whose Q'output is fed to base of transistor Q. When Q'=high, Q, is ON and capacitor (externally
connected between pin 7 and ground) will discharge.
The output stage is basically an inverting buffer stage used toprovide a low output resistance and
also to invert the flip flop output. Output stage has acapability of sourcing and sinking 200mA
current. Q (PNP transistor) whose emitter is connected to an internal reference voltage which is
less than Vcc. When Vret> Vcc (Pin-4 potential is less than Vcc), Q, is ON, which causes Q, to turn
ON and output at pin-3 is brought to ground level.
Applications include oscillator, pulse generator, ramp and square wave generator, voltage monitor
and may more applications.

IC-555 AS MONOSTABLE MULTIVIBRATOR:

Figure 4.19 (a)shows the circuit diagram of IC-555 as monostable multivibrator and (b) shows
the waveform of trigger pulse, capacitor voltage and output pulse. Since it has only one stable
state (output low), hence name monostable.
 Vcc Trigger
R} 0
t
Vcc
2/3Vcc Capacitor
H 6 555 3
Vo Voltage (Vc)
t

T tp Output
Pulse (Vo)

t
Figure 4.19(a): Monostable Multivibrator
0

Figure 4.19(b):Waveforms
It is also called as one-shot multivibrator. From the circuit diagram, Pin-8 is connected to Vcc and
pin-4 (reset pin) also connected to Vcc so that reset condition is disabled. The time interval for
which the output remains high (tp, pulse width) is decided by the external RC network. The
capacitor Cis connected between pin 7and 1so that it charges through the resistance Rwhen the
transistor Qi is OFF.
Operation: Initially, trigger pulse is high (Vcc), this drives the output of comparator-2 to low
condition. As the capacitor Cis indischarged state, pin-6 and 7 are at ground potential. The inputs
to the flip flop will be S=R=0, hence Q' = high, so, Q, is ON, and Cdischarges to 0V ie. Vc = 0V.
Since Q' = 1,output pin-3 =0 is actually the stable state of multivibrator.
When the trigger input (negative trigger pulse) goes low(from Vcc to 0), comparator-2 output =
high ie. S = 1. The comparator-1 output continue to be 0 ie. R=0, hence the flip flop is in set
condition ie. Q' = 0, pin-3 = 1(High state). Since Q' = 0, transistor Q, is OFF and the capacitor C
starts charging exponentially towards Vcc through the resistor R. When Vc becomes greater than
((23) Vcc), comparator-1 output changes form low to high ie. R =1. Since the trigger input has
returned back to Vcc from 0, comparator-2 output is equal to zero ie. S =0. So, S = 0 and R= 1, RS
flip flop get RESET and Q' = 1. AS Q= 1, transistor Q1 = ON and capacitor C starts discharging
towards zero through the transistor Qand capacitor voltage Vc becomes zero. While discharging,
when Vc < (23) Vcc), the comparator-1 output goes to zero ie. R=0. Since the trigger input = Vcc,
the comparator-2 output will be =0 ie. S=0. Hence, S=0 and R=0, so no change in the Q' output
condition and hence continuous to be High. Thus, pin-3 output = LOW(0-state).
The monostable multivibrator, thus goes from stable state into quasistable state and then returns
back to the stable state after a time, tp (1.1)R.C
The output remains to be in LOW state until the next trigger pulse is applied to change the state.

IC-555 AS ASTABLE MULTIVIBRATOR:

Figure 4.20 (a) shows the circuit diagram of lC-555 as astable multivibrator and (b) shows the
waveform of capacitor voltage and output pulse. Since no stable state, hence name astable.
 pVcc
RA 8 Vcc Output
7 Voltage
Re 0 ToN ToFF
6
S5s 3 T
Vo
Vec
2/3Vre Capacitor
/3Vc Voltage

Figure 4.20(a): Waveforms

Figure 4.20(a): Astable Multivibrator
Astable multivibrator does not requires an external trigger pluse to change the output state,
hence called as free-running multivibrator. The time duration for which the output will remain
high or low is decided by the externally connected two resistors (RA and Rs) and a capacitor (C).
Operation: Initially, when output is high (pin-3 = High), Flip flop output Q' = 0, hence transistor
Q is OFF. Now the capacitor C starts charging towards Vcc through RA and Rg. As soon as the
and
voltage across the capacitor Vc, becomes equal to[ (23)Vcc], the comparator-1 output is high
transistor Q, = ON and tne
will RESET the flip flop ie. Q' = 1. Hence the output = 0. As, Q' =1,
discharging mode of
capacitor C starts discharging through resistor Rg and transistor Q,. During
to (13)Vcc],
capacitor C, as soon as the voltage across the capacitor C becomes equal
comparator-2 output will SET the flip flop, Q'=0, and output = high. Then the cycle repeats.
given by the
Charging time duration of the capacitor C, is equal to the time the output is high is
expression: tç = ToN = 0.69(RA + Re )C
low is given by the
Discharging time duration of the capacitor C, is equal to the time the output is
expression: ty = ToFF = 0.69(Rs )c
Hence the total time period of output waveform: T =tc + to = ToN + ToFF = 0.69(Ra + 2Ra )C

145
Hence, the frequency of oscillation is, fo = 1/T= (RA-2RgC
From the equation of frequency of oscillation fo, frequency is independent of the supply voltage
VCc.
the total
Duty Cycle: Duty cycle is the ratio of the time during which the output is high (ToN) to
time period T.
%duty cycde = (Ton / T] x 100 = R *Rg x 100
RA-2Rg
Applications: Astable multivibrator can be used to produce a square wave output. It can be used
as a free running ramp generator.

DIGITAL IC LOGICFAMILIES:
1. RTL- Resistor Transistor Logic 2.DTL-Diode Transistor Logic 3.1TL
Transistor Transistor Logic 4.ECL-Emitter Coupled Logic 5.'
6.PMOS- P-Channel Metal Oxide Semiconductor
Integrated Injection Logic
7.NMOS- N-Channel Metal Oxide Semiconductor 8.CMOS
Complementary Metal Oxide Semiconductor

Characteristics of Digital IC's:

1.FAN-IN: Number of inputs connected to gate, without the degradation in the voltage levels.
2.FAN-OUT: Number of standard loads that the output of the gate can drive without degrading
Page 65 of $4
he normal operation.
3.POWER DISSIPATION: Power consumed by the gate.
4.PROPAGATION DELAY: Average transition time for theavailable from power supply.
signal to propagate from input to outpul.
5.NOISE MARGIN: Noise margin is the imit os nico voltage
which may be present without
imparing or degrading the proper operation of the
circuit.
TTL- Transistor TransistorLogic:
A)TTL-2 input NAND gate having totem pole (active pull-up) output stage:
The circuit diagram of a 2-input TTL
Vcc
NAND gate having an active pull-up
(totem-pole) output stage is shown in
figure 4.21. In this circuit, if one or both
of the inputs are at logic 0, the
T corresponding B-E junction of TË will be
forward biased, and the voltage at point
YDo P will become nearly equal to 0.7V
ER3 Voooutput which will keep the T; and T; OFF. (The
voltage at P must be at least equal to
1.8V for turning T; and T3 ON.)
Figure 4.21: TTL- 2-Input NAND Gate(Totem Pole o/P) Therefore, the output voltage will be at
logic 1, equal to Vcc - (drop across Ra)
(VcE of Ta) - Vpo, Which is nearly equal to
3.5V.
If both the inputs are held at logic 1 level, the 8-E junctions of TË willbe reverse biased, and the
current flowing through R, and the C-8 junction of TË will turn ON the transistors T, and Tz. Hence,
the output voltage willbe at logic 0, equal to VcEsat Of T3. When the voltage at the input terminal
corresponds to 1 level, the gate sinks an input current (reverse saturation current of the B-E
junction of Ti), whereas when the voltage at the input terminal corresponds to 0 level, the gate
sources an input current(forward current of the B-E junction of Ti).
Advantages: 1)when T4 is OFF and T3 is ON, Disadvantage: T3 turns OFFmore slowly than
no current through R4, so, no power T4 turns ON. So, before T3 completely turns
dissipation. OFF, T4 comes into conduction. So, for a very
2)1f output is high, T4 is ON and T3 is OFF, short duration of timeboth T3 and T4 are ON.
hence T4 is acting in the emitter follower This is called cross conduction and draws
mode, its output impedance is low. Therefore large current.
output time constant for charging of any
capacitive load is very short.

B) TTL- 2 input open-collector TTL NAND gate :

The circuit diagram of a 2-input open collector TTL NAND gate is shown in
figure 4.23 and
TTL-logic symbol (open collector) is shown in figure 4.22. Note that the collector of the
T3 is floating. For the proper functioning of the device, this open
transistor
collector terminal ofT3 must be
tied to Vcc through resistor R, known as pull-up resistor (passive
pull-up). Once a suitable pull-up
resistor is connected, the characteristic of open collector and totem pole will be almost
same.
 Vcc
Indicates open collector

Output Rz

Figure 4.22: TTL- Logic Symbol T2

(Open Collector)
output

Collector O/P)
Figure 4.23: TTL- 2-Input NAND Gate(Open

Advantage of open collector output is that wired ANDing becomes possible.

Wired ANDing as shown in figure 4.24, means tieing the outputs of gates together to obtain AND
function.
Vcc It is possible to connect the outputs of two or
more gates together.

Figure 4.24: Wired ANDing of NAND gate O/P

Comparision of Totem-Pole and Open-Collector outputs:

Parameters Totem-Pole Open-collector
Circuit components on T4 (pull up transistor), T3 Only T3 (pull down transistor)
output side (pull down transistor) and
diode D0.
Wired ANDing NO Yes
External pull up resistor Not required Required
Power Dissipation Low due to Pull up transistor. High due to current flowing
through external pull up resistor.
Speed High Low

C) TTL- TRI-STATE TTL Gate:

In anormal logic circuits there are two states of the output- LOW and HIGH. When a number of
such outputs are connected to a common line, there are loading problems. To avoid this, tri-state
outputs are used. In tri-state output circuits, there are three distinct states of which two are the
logic 0 and logic 1 states and third is a high impedance state. In the figure 4.25 of a tri-state TTL
inverter circuit, when control input is LOW, the drive is removed from T, and T, and the output is
in the third state (High impedance). When the control input is high, the output is 1or 0 depending
on the input. Figure 4.26 logic symbol of tristate TTL inverter.
 Vcc
Control
ER Data Input Data
R2
Controle
Output
Figure 4.26: Tri-state TTL
Data
inverter logic symbol
Data Input Output

Figure4.25: Tri-state TTL inverter

PMOS, NMOS, and CMOS logic:

A NMOS switch is closed when controlling signal is HIGH.
DRAIN An arrow indicates the direction of positive current flow
from drain (D) to source (S) in NMOS.
soURCE
Logic Symbol of NMos

APMOS Switch is closed when controlling signal is LOW.

SOURCE An arrow indicates the direction of positive current flow
DRAIN from source (S) to drain (D) in PMOS.
Logic Symbol of PMos

Realization of logic gates using MOS logic family:

VoD Voo

to output A' D output (A.By

Input Agliys Input Ag liys D

Inverter using NMOS

Input BHs
NAND using NMOS

VoD
pVoo
PMOS
D
Input A Output A'
Input Ae Input BeE Output (A+B)Y
NMOS S
NOR using NMOS
Inverter using CMOS
 fVoo
PMOS PMOS Voo
s Input A PMO^
D D
Output (A.B)'
Input B
Input A
D
Input B D JD Output (A+B)
NMOS S
NAND using CMOS NOR using CMOS

Advantages of MOS logic: 1)Low power dissipation. 2)Excellent noise immunity.

S)High packing density. 4)Wide range of supply voltages (+3V to +18V)
INTERFACING BETWEEN TTL to MOS:
to a loading device. Here TTL is the driving
Intertacing refers the way a driving device is connected
a supply voltage of 5V and CMOS needs
device and CMOS is the loading device. TTL device needs
of +3V to +15V.
15V 5V
TTL High CMOS High
2.4V 3.5V

Intermediate Intermediate
state state
1.5V
0.4V
TTL LOw CMOS Low
OV OV
TTLOutput profile CMOS output profile
Figure 4.26: Outprofile of TTL and CMOS
CMOS low ie.
Figure 4.26 shows the output profile of TTL and CMOS, a TTL low fits inside the
CMOS load always interprets the TTL low state drive as a low. The problem is with TTL high state
ie. there is indeterminate action ie. no reliable operation. So, the standard solution is to use a pull
up resistor between TTL driver and CMOS load. It raises the high state to approximate 15V.
In figure 4.27, VWhen TTL output is low, 3.3K
5V
resistor is grounded, therefore TTL driver sink
S3.3KO current of 1.52mA. when TTL output is high, pull
up resistor, output raises above +2.4V ie. The
supply voltage is pulling up the output upto +5V
IrL driver LCMOs load (1.52mAx3.3K). If more than one TTL chip is
Figure 4.27:TTL driver & CMOS interface being interfaced to the CMOS load, connect each
TTL driver to a separate pull-up resistor.
5Ve
If CMOS IC is operated with Voo greater than 5V
10V then the TTL driving high voltage CMOS design is
used as shown in figure 4.28. Buffer is used to
interface between TTL and CMOS. IC7406 as
Buffer
inverting buffer has an output voltage rating of
TL driverCMOS load 30V.
Figure4.28:TTL driving high voltage CMOS