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27 views25 pages

Cap 2

Uploaded by

kasulakarthikeya2005
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EC2003E COMPUTER ARCHITECTURE AND PROCESSORS

Monsoon 2024-25
8086 - Introduction
• 16-Bit Data Bus
• 20-Bit Address Bus
• Capability to access and work on 8-bit Data
8086-Internal Block Diagram
8086-Internal Block Diagram
• Partitioned into two logical units
• Bus Interface Unit (BIU)
• Execution Unit (EU)
• Interact directly with each other through internal bus
Concept of Registers
• All processors have internal registers
• On-chip RAM
• Some are visible to programs and some are not
• Used for temporary storage of data
• General purpose or special function registers
• Faster access
• Cost
• More number of registers – More number of bits required to
identify – More length for instructions
Register Model of 8086
Scratchpad Registers
• Used for temporary storage
• 8086 has four (4) 16-bit scratchpad registers – AX, BX, CX and DX
• Can also be used as separate 8-bit registers – AH, AL, BH, BL, CH,
CL, DH, DL
• Special purposes as well
Pointer and Index Registers
• SP – Stack Pointer – Points to Top of Stack
• BP – Base Pointer - Points to any location in Stack

• SI – Source Index
Used in various addressing modes
• DI – Destination Index
Flag Register
Flag Register - Example
Find the status of CF, SF, AF and ZF after executing the following
instructions

MOV AL, 35H - Move 35H to AL


ADD AL, 0CEH - Add 0CEH to AL and store the result in AL
Flag Register - Example
Find the status of CF, SF, AF and ZF after executing the following
instructions

MOV AL, 35H - Move 35H to AL


ADD AL, 0CEH - Add 0CEH to AL and store the result in AL

Final answer = 1 0000 0011


CF = 1 - There is a carry out from D7
SF=0 - Sign bit is 0
AF=1 – There is a carry from D3 to D4
ZF =0 - Answer is not 0
Arithmetic Logic Unit (ALU)
• The Most important unit of a processor
• All arithmetic and logic operations are performed in this unit
• Has Direct access to all the registers
Bus Interface Unit
• Responsible for performing all external bus operations
• 16-Bit data bus and 20-bit address bus

• Sends address of the memory or I/O.


• Fetches instruction from memory.
• Reads data from port/memory.
• Writes data into port/memory.
• Supports instruction queuing.
• Provides the address relocation facility.
Instruction Queue
• It can pre-fetch six instruction bytes from memory
• Pipe-lining
Instruction Queue
• Queue operates in FIFO mode
• Instructions are fetched sequentially
• Instructions like JUMP, CALL etc will change the sequence of
execution
• Pre-fetched instructions in the queue will have to discarded
Memory Segmentation
• The physical address of the Internal Architecture of 8086 is 20-bits
wide to access 1 Mbyte memory locations.
• Its registers and memory locations which contain logical
addresses are just 16-bits wide.
• Hence 8086 uses memory segmentation.
Memory Segmentation
• It treats the 1 Mbyte of memory as divided into segments, with a
maximum size of a segment as 64 Kbytes.
• Thus any location within the segment can be accessed using 16
bits.
• The Internal Architecture of 8086 allows only four active segments
at a time
• For the selection of the four active segments the 16-bit segment
registers are provided within the BIU of the 8086
Segment Registers
• Code segment (CS) register
• Data segment (DS) register
• Stack segment (SS) register
• Extra segment (ES) register
• These are used to hold the upper 16-bits of the starting addresses
of the four memory segments
• Offsets are added to calculate the actual address of a particular
memory location
• Represented as, base address: offset
Memory Segmentation
Example Calculation of memory address
• Data Segment Register contains the value 2222H
• Offset is 0016H

• Physical Address: 22220 H+


0016 H
----------------------
22236H
Segments and Corresponding Registers
Segment Offset Registers Function

CS IP Address of the next instruction

DS BX, DI, SI Address of Data

SS SP, BP Address of the Stack

ES BX, DI, SI Address of destination data


(for string operations)
Segmentation – Some Points
• Base address should be divisible by 16
• Segments can overlap – There can be more than one logical
address for the same memory location
• There can be many segments with the same base address.
• Maximum size of a segment is 64K
• A Program need not have all the 4 segments – But at least code
segment should be there
Segmentation – Some Points
• Address used by instructions are called logical address and are
translated by BIU to physical address
• Program and Data are re-locatable. They can be saved at any
location in the memory – Only base address of the corresponding
segment need to be changed
Some Examples
• The contents of some registers are as follows: Calculate the
physical address
• CS=1111H
• DS=3333H
• SS=2526H
• IP=1232H
• SP=1100H
• Offset in Data Segment =0020H
Some Examples
• CS+IP=11110H+1232H = 12342H
• DS+Offset=33330H+0020H=33350H
• SS+SP=25260H+1100H = 26360H

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