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Tutorial No2 Digital VLSI

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16 views2 pages

Tutorial No2 Digital VLSI

Class

Uploaded by

sumuzhe201
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital VLSI : Tutorial Questions for 4th November

Q1 (a) An NMOS transistor can be used with a restive load to construct an inverter.
The positive supply voltage is 5V and the negative supply voltage is 0V. The
NMOS has a gain of 1mA/V2 and a threshold voltage of 1V.

(i) Draw the circuit diagram for an NMOS inverter. [5]

(ii) Considering that this inverter will drive a capacitive load of another
FET, derive an expression for the rise time of the output from the
10% to 90% voltage. [8]

(iii) Assuming for simplicity that after switching on, the FET is in
saturation and that the output voltage swing is rail to rail. Derive an
expression for the fall time of the output from the 90% to 10%
voltage. [8]

(iv) If the capacitance on the output of this inverter is 1pF, what value of
load resistor would we need to match the rise and fall times? [2]

(v) What is the implication for static power consumption in a VLSI chip
using these NMOS inverters? [2]

Q2 Efficient adder circuits can be made using the Carry Propagate Generate (CPG)
method.

(a) Write down the Boolean expressions for Carry (C), Propagate (P), Generate
(G), Delete (D), Sum (S) and Carry Out (Cout) signals in terms of the inputs A,
B and Carry In (Cin). [8]

(b) A mirror adder is a CMOS circuit design that is used to implement a CPG
circuit efficiently.

(i) Sketch the transistor-level circuit diagram for the mirror adder. [10]

(ii) Using sketches of the relevant portions of the mirror adder circuit show
which parts are responsible for producing the Propagate, Delete and
Generate operations. Describe how the portions you have identified
deliver the required behaviour. [7]

Continued overleaf
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Q3 (a) Figure Q1 shows a circuit symbol for a 1-bit full adder. Sketch the circuit for
a 4-bit adder. [5]

(b) The method of “pushing bubbles” is used to reduce circuit size and increase
speed.

(i) Draw two new circuit symbols for 1-bit adders and show how they
may be combined to make a 4-bit adder. [10]

(ii) By deriving Boolean expressions for the sum and carry outputs of a
simple 1-bit CMOS adder show how the method of pushing bubbles
leads to a smaller and faster circuit. [10]

Cin

A
S
B

Cout

Figure Q1. A 1-bit adder symbol.

Q4 Sketch the circuit diagram for a static edge-triggered latch and draw the timing
diagram assuming a two-phase clock (C1 and C2) with no non-overlap
between phases. Label the set-up, hold and clock-to-Q times on the diagram.[10]

Q5 A pipelined system architecture is required to have the ability to arbitrarily shift data
bits either to the left or the right, or not at all, in a single clock cycle. Sketch,
using pass-transistor logic, a circuit that will do this. You may assume that
there is an input and an output register associated with the device. [8]

End of question paper


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