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313303 - Digital Techniques (Sem III)

As per MSBTE’s K Scheme
CO / CM / IF

UNIT 2 Logic Gates and Boolean Algebra Marks : 12

Sr.
Questions Year Marks
No.
1 Draw the circuit diagram for AND and OR gates using diodes. W- 2
18
Ans

2 Draw the symbol, truth table and logic expression of any one universal logic gate. W- 4
Write reason why it is called universal gate. 18

Universal Gates: NAND or NOR Symbol:

Truth table:
 Logic expression:

NAND and NOR gates are called as “Universal Gate” as it is possible toimplement any
Boolean expression using these gates.
(i) Propagation delay

(ii) Power Dissipation

(iii) Fan-out

Ans (iv) Basic gate

Parameter CMOS TTL

Propagation delay 70-105 nsec/more 10 nsec/Less than
than CMOS
TTL
Power Dissipation Less 0.1 mW/Less More 10 mW/ More
than than CMOS
TTL
Fan-out 50/More than TTL 10/Less than CMOS

Basic gate NAND/NOR NAND

4 Realize the basic logic gates, NOT, OR and AND gates using NOR gates only. W- 4
18
( NOT GATE USING NOR GATE:1 M )
Ans W- 4
22

where, X = A NOR Ax = Ā

(AND GATE USING NOR GATE:1.5 MARKS)

Q=Ā¯ +̅B = Ā¯ +̅B

=A.B
= A.B
 (OR GATE USING NOR GATE:1.5 MARKS)

Q=A+B
=A+B

5 State De Morgan’s theorem and prove any one. W- 4

18

S-19 4

S-22 4

W- 4
23
6 Draw Symbol, Truth Table and logic equation of Ex-OR gate. W- 2
19

Logic Equation = A𝐵̅+𝐵 ̅ B OR Truth Table:

7 State the DeMorgan's Theorems W- 2

19

8 Compare TTL, CMOS and ECL logic family on the following points. W- 6
19
(i) Basic Gates

(ii) Propogation delay

(iii) Fan out

(iv) Power Dissipation

(v) Noise immunity

(vi) Speed Power Product

9 Define fan-in and fan-out of a gate. S-19 2

Fan-in is a term that defines the maximum number of digital inputs that a single logic
gate can accept. Most transistor-transistor logic (TTL) gates have one or two inputs,
although some have more than two. A typical logic gate has a fan-in of 1 or 2.
Fan-out is a term that defines the maximum number of digital inputs that the output of a
single logic gate can feed. Most transistor-transistor logic (TTL) gates can feed up to 10
other digital gates.

10 Draw the logical symbol of EX-OR and EX-NOR gate S-19 2

11 Explain the flowing characteristics w.r.t logic families: S-19 4

(i) Noise margin

(ii) Power dissipation

 (iii) Figure of merit

(iv) Speed of operation

Noise margin: indicates the amount to noise voltage circuit can tolerate at its input for both
logic 1 and logic0.

Power Dissipation: It is the amount of power dissipated in an IC.

Figure of Merit: It is defined as the product of propagation delay and power dissipated by
the gate.

Speed of Operation: Speed of a logic circuit is determined by the time between the
application of input and change in the output of the circuit.

12 Realize the following logic operation using only NOR gates: AND, OR, NOT. W- 4
22
13 Draw symbol, truth table and logical output equation of OR and EX-OR gate W- 4
22
14 Draw the circuit and explain the principle of TTL gate with totempole output W- 6
22
15 State and prove two De-Morgan’s Theorems S-22 4
16 Draw symbol, truth table of NAND gate. W- 2
23

17 Design basic logic gates using NAND and NOR gate W- 8

23
18 Draw the OR gate and NOR gate using NAND gate only. S-23 4
19 State the advantages of using tri state logic in combinational logic S-24 2

Advantages of using tri state logic in combinational logic are:

1) It reduces crosstalk in a bus.

2) It prevents a bus conflict over a state of signal.
3) It allows multiple devices to share the same bus without interference.
20 Realize the following logic operation using only NOR gates. S-24 4

I) OR

II) EX-NOR

I) OR gate using NOR gate: -

Boolean expression for an OR gate using NOR gate

Q = A+B

II) EX-NOR gate using NOR gate: -

 Boolean expression for an EX-NOR gate using NOR gate

Output of EX-NOR.
21 Draw the symbol , truth table and logical expression of following gates: S-24 4

I) EX-OR gate

II) NAND gate

I) EX-OR gate:

II) NAND gate:

22 Draw the circuit diagram of 3-input TTL NAND gate and explain its working. S-24 6

Circuit Description:
The 3-input TTL NAND gate circuit consists of three input terminals and one output
terminal. Each input terminal is connected through an input resistor, and the output is
taken from the connection point between these resistors. The circuit operates with a
positive power supply voltage (Vcc) and a ground reference (GND).
Working:
1. Input Signals:
 The gate has three input terminals (A, B, and C), each connected through a
resistor.
 Inputs can be at logic level HIGH (typically Vcc, representing a binary '1') or
logic level LOW (typically GND, representing a binary'0').
2. Voltage Divider Network:
 When any input terminal is at logic level LOW (GND), it pulls the
corresponding node of the voltage divider network to LOW.
 When all input terminals are at logic level HIGH (Vcc), the voltage at the
common node between the resistors is pulled up to HIGH.
3. Transistor Configuration:
 The output transistor configuration of a NAND gate ensures that when any
input is LOW, the base voltage of the transistor(s) is pulled downto LOW.
 As a result, the transistor(s) conduct and pull the output voltage to LOW.
When the transistor Q3 is ON, the output at terminal Y is HIGH. The outputis LOW when the
transistor Q4 is turned ON. The first and second states arethe normal operation of TTL. In
the third state, both the transistors Q3 and Q4 are turned OFF, which results in neither
LOW nor HIGH output.
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