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Vivado Design Suite Tutorial

Programming and Debugging

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Table of Contents
Debugging in Vivado Tutorial.................................................................................. 5
Navigating Content by Design Process.................................................................................... 5
Objectives..................................................................................................................................... 6
Getting Started............................................................................................................................ 7

Lab 1: Using the Netlist Insertion Method to Debug a Design........... 12

Step 1: Creating a Project with the Vivado New Project Wizard.......................................... 12
Step 2: Synthesizing the Design.............................................................................................. 13
Step 3: Probing and Adding Debug IP.................................................................................... 14
Step 4: Implementing and Generating Bitstream.................................................................22

Lab 2: Using the HDL Instantiation Method to Debug a Design........ 23

Step 1: Creating a Project with the Vivado New Project Wizard.......................................... 23
Step 2: Synthesize, Implement, and Generate Bitstream.................................................... 25

Lab 3: Using a VIO Core to Debug a Design in Vivado Design

Suite................................................................................................................................. 26
Step 1: Creating a Project with the Vivado New Project Wizard.......................................... 27
Step 2: Synthesize, Implement, and Generate the Bitstream..............................................32

Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design
Suite to Debug a Design....................................................................................... 33
Step 1: Create a Synplify Pro Project.......................................................................................33
Step 2: Synthesize the Synplify Project................................................................................... 39
Step 3: Create DCPs for the Black Box Created in Synplify Pro........................................... 40
Step 4: Create a Post Synthesis Project in Vivado IDE.......................................................... 40
Step 5: Add More Debug Nets to the Project.........................................................................41
Step 6: Implementing the Design and Generating the Bitstream...................................... 44

Lab 5: Using the Vivado Logic Analyzer to Debug Hardware...............45

Step 1: Verifying Operation of the Sine Wave Generator.....................................................45
Step 2: Debugging the Sine Wave Sequencer State Machine (Optional)...........................56

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Vivado Design Suite Tutorial: Programming and Debugging 2
 Lab 6: Using the ECO Flow to Replace Debug Probes Post
Implementation........................................................................................................ 74

Lab 7: Debugging Designs Using the Incremental Compile Flow..... 87

Procedure................................................................................................................................... 87
Step 1: Opening the Example Design and Adding a Debug Core....................................... 87
Step 2: Compiling the Reference Design................................................................................91
Step 3: Create New Runs.......................................................................................................... 92
Step 4: Making Incremental Debug Changes........................................................................ 94
Step 5: Running Incremental Compile....................................................................................97
Conclusion..................................................................................................................................99

Lab 8: Using the Vivado Serial Analyzer to Debug Serial Links.........100

Design Description..................................................................................................................100
Step 1: Creating, Customizing, and Generating an IBERT Design.................................... 101
Step 2: Adding an IBERT Core to the Vivado Project...........................................................102
Step 3: Synthesize, Implement, and Generate Bitstream for the IBERT Design............. 108
Step 4: Interact with the IBERT Core Using Serial I/O Analyzer........................................ 110

Lab 9: Using the Vivado ILA Core to Debug JTAG-AXI

Transactions.............................................................................................................. 126
Design Description..................................................................................................................126
Step 1: Creating a New Vivado Project and Generating the IP Integrator Design with
JTAG-to-AXI and System ILA.............................................................................................. 127
Step 2: Program the KC705 Board and Interact with the JTAG to AXI Master Core........ 140
Step 3: Using ILA Advanced Trigger Feature to Trigger on an AXI Read Transaction.... 146

Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial
Links...............................................................................................................................150
IBERT PS-GTR Flow.................................................................................................................. 150
Step 1: Generating a Zynq UltraScale+ MPSoC PS Xilinx Support Archive....................... 152
Step 2: Using AMD Software Command-line Tool Flow to Generate a First Stage
Boot Loader.........................................................................................................................162
Step 3: ZCU102 Board Settings.............................................................................................. 163
Using FSBL with Serial I/O Analyzer to Bring Up IBERT PS-GTR........................................164
Troubleshooting...................................................................................................................... 171

Appendix A: Additional Resources and Legal Notices........................... 173

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 Finding Additional Documentation.......................................................................................173
Support Resources.................................................................................................................. 174
Revision History....................................................................................................................... 174
Please Read: Important Legal Notices................................................................................. 174

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Vivado Design Suite Tutorial: Programming and Debugging 4
 Debugging in Vivado Tutorial

Debugging in Vivado Tutorial

This document contains a set of tutorials designed to help you debug complex FPGA designs.
The first four labs explain different kinds of debug flows that you can choose to use during the
course of debugging. These labs introduce the AMD Vivado™ Design Suite debug methodology
recommended to debug your FPGA designs. The labs describe the steps involved in taking a
small RTL design and the multiple ways of inserting the Integrated Logic Analyzer (ILA) core to
help debug the design. The fifth lab is for debugging high-speed serial I/O links in the Vivado
tool. The sixth lab is for debugging JTAG-AXI transactions in the Vivado tool. The first four labs
converge at the same point when connected to a target hardware board.

Example RTL designs are used to illustrate overall integration flows between the Vivado logic
analyzer, ILA, and the Vivado Integrated Design Environment (IDE). To be successful using this
tutorial, you should have some basic knowledge of the Vivado tool flow.

TRAINING: AMD provides training courses that can help you learn more about the concepts presented in
this document. Use these links to explore related courses:

• Designing FPGAs Using the Vivado Design Suite 1

• Designing FPGAs Using the Vivado Design Suite 2
• Designing FPGAs Using the Vivado Design Suite 3
• Designing FPGAs Using the Vivado Design Suite 4
• Vivado Design Suite User Guide: Programming and Debugging (UG908)

Navigating Content by Design Process

AMD Adaptive Computing documentation is organized around a set of standard design
processes to help you find relevant content for your current development task. You can access
the AMD Versal™ adaptive SoC design processes on the Design Hubs page. You can also use the
Design Flow Assistant to better understand the design flows and find content that is specific to
your intended design needs.

• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware
platform, creating PL kernels, functional simulation, and evaluating the AMD Vivado™ timing,
resource use, and power closure. Also involves developing the hardware platform for system
integration. Topics in this document that apply to this design process include:

• Lab 1: Using the Netlist Insertion Method to Debug a Design

• Lab 2: Using the HDL Instantiation Method to Debug a Design

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Vivado Design Suite Tutorial: Programming and Debugging 5
 Debugging in Vivado Tutorial

• Lab 3: Using a VIO Core to Debug a Design in Vivado Design Suite

• Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a Design
• Lab 5: Using the Vivado Logic Analyzer to Debug Hardware
• Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation
• Lab 7: Debugging Designs Using the Incremental Compile Flow
• Lab 9: Using the Vivado ILA Core to Debug JTAG-AXI Transactions

• Board System Design: Designing a PCB through schematics and board layout. Also involves
power, thermal, and signal integrity considerations. Topics in this document that apply to this
design process include:

• Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation
• Lab 7: Debugging Designs Using the Incremental Compile Flow
• Lab 8: Using the Vivado Serial Analyzer to Debug Serial Links
• Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

Objectives
These tutorials:

• Show you how to take advantage of integrated Vivado logic analyzer features in the Vivado
design environment that makes the debug process faster and simpler.
• Provide specifics on how to use the Vivado IDE and the Vivado logic analyzer to debug
common problems in FPGA logic designs.
• Provide specifics on how to use the Vivado Serial I/O Analyzer to debug high-speed serial
links.

After completing this tutorial, you are able to:

• Validate and debug your design using the Vivado Integrated Design Environment (IDE) and the
Integrated Logic Analyzer (ILA) core.
• Understand how to create an RTL project, probe your design, insert an ILA core, and
implement the design in the Vivado IDE.
• Generate and customize an IP core netlist in the Vivado IDE.
• Debug the design using Vivado logic analyzer in real-time and iterate the design using the
Vivado IDE and a KC705 Evaluation Kit Base Board that incorporates an AMD Kintex™ 7
device.
• Analyze high-speed serial links using the Serial I/O Analyzer.

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Vivado Design Suite Tutorial: Programming and Debugging 6
 Debugging in Vivado Tutorial

Getting Started
Setup Requirements
Before you start this tutorial, make sure you have and understand the hardware and software
components needed to perform the labs included in this tutorial.

Software

Vivado Design Suite 2024.1.

Hardware

• AMD Kintex™ 7 FPGA KC705 Evaluation Kit Base Board

• Digilent Cable
• Two SMA (Sub-miniature version A) cables

Figure 1: KC705 Board Showing Key Components

Tutorial Design Components

Labs 1 through 4 include:

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Vivado Design Suite Tutorial: Programming and Debugging 7
 Debugging in Vivado Tutorial

• A simple control state machine

• Three sine wave generators using AXI4-Stream interface, native DDS Compiler
• Common push buttons (GPIO_BUTTON)
• DIP switches (GPIO_SWITCH)
• LED displays (GPIO_LED) VIO Core (Lab 3 only)

• Pushbutton Switches: Serve as inputs to the de-bounce and control state machine circuits.
Pushing a button generates a high-to-low transition pulse. Each generated output pulse is
used as an input into the state machine.

• DIP Switch: Enables or disables a de-bounce circuit.

• De-bounce Circuit: This example, when enabled, provides a clean pulse or transition from high
to low. Eliminates a series of spikes or glitches when a button is pressed and released.

• Sine Wave Sequencer State Machine: Captures and decodes input from the two push buttons.
Provides sine wave selection and indicator circuits, sequencing among 00, 01, 10, and 11 (zero
to three).

• LED Displays: GPIO_LED_0 and GPIO_LED_1 display selection status from the state machine
outputs, each of which represents a different sine wave frequency: high, medium, and low.

Lab 5 includes:

• An IBERT core
• A top-level wrapper that instantiates the IBERT core

Board Support and Pinout Information

Table 1: Pinout Information for the KC705 Board

Pin Name Pin Location Description

CLK_N AD11 Clock
CLK_P AD12 Clock
GPIO_BUTTONS[0] AA12 Reset
GPIO_BUTTONS[1] AG5 Sine Wave Sequencer
GPIO_SWITCH Y28 De-bounce Circuit Selector
LEDS_n[0] AB8 Sine Wave Selection[0]
LEDS_n[1] AA8 Sine Wave Selection[1]
LEDS_n[2] AC9 Reserved
LEDS_n[3] AB9 Reserved

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 Debugging in Vivado Tutorial

Design Files
1. In your C: drive, create a folder called /Vivado_Debug.
2. Download the Reference Design Files from the AMD website.

CAUTION! The tutorial and design files can be updated or modified between software releases. You
can download the latest version of the material from the AMD website.

3. Unzip the tutorial source file to the /Vivado_Debug folder. There are six labs that use
different methodologies for debugging your design. Select the appropriate lab and follow the
steps to complete them.

• Lab 1: This lab walks you through the steps of marking nets for debugging in HDL and the
post-synthesis netlist (netlist insertion method). The following are the required files:

• debounce.vhd
• fsm.vhd
• sinegen.vhd
• sinegen_demo.vhd
• sine_high/sine_high.xci
• sine_low/sine_low.xci
• sine_mid/sine_mid.xci
• sinegen_demo_kc705.xdc

• Lab 2: This lab reviews the details of marking nets for debugging in the source HDL (HDL
instantiation method) and instantiating an ILA core in the HDL. The following are the required
files:

• debounce.vhd
• fsm.vhd
• sinegen.vhd
• sinegen_demo_inst.vhd
• ila_0/ila_0.xci
• sine_high/sine_high.xci
• sine_low/sine_low.xci
• sine_mid/sine_mid.xci
• sinegen_demo_kc705.xdc

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Vivado Design Suite Tutorial: Programming and Debugging 9
 Debugging in Vivado Tutorial

• Lab 3: You can test your design even if the hardware is not physically accessible using a VIO
core. This lab walks you through the steps of instantiating and customizing a VIO core that
you hook to the I/Os of the design. The following are the required files:

• debounce.vhd
• fsm.vhd
• sinegen.vhd
• sinegen_demo_inst_vio.vhd
• sine_high/sine_high.xci
• sine_low/sine_low.xci
• sine_mid/sine_mid.xci
• ila_0/ila_0.xci
• sinegen_demo_kc705.xdc

• Lab 4: Nets can also be marked for debugging in a third-party synthesis tool using directives
for the synthesis tool. This lab walks you through the steps of marking nets for debugging in
the Synplify tool and using Vivado to perform the rest of the debugging. The following are the
required files:

• debounce.vhd
• fsm.vhd
• sign_high.dcp
• sign_low.dcp
• sine_mid.dcp
• sine_high.xci
• sine_low.xci
• sine_mid.xci
• sinegen.edn
• sinegen_synplify.vhd
• synplify_1.sdc
• synplify_1.fdc
• sinegen_demo_kc705.xdc

• Lab 5: Take designs created from Lab 1, Lab 2, Lab 3, and Lab 4 and load them onto the
KC705 board.

• Lab 6: Enhance post-implementation debugging by using the ECO flow to replace debug
probes.

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Vivado Design Suite Tutorial: Programming and Debugging 10
 Debugging in Vivado Tutorial

• Lab 7: Use the Incremental Compile flow to enable faster debugging flows. Using the results
from a previous implementation run, this flow allows you to make debug modifications and
rerun implementation.

• Lab 8: Debug high-speed serial I/O links using the Vivado Serial I/O Analyzer. This lab uses
the Vivado IP example design.

• Lab 9: Use Vivado ILA core to debug JTAG-to-AXI transactions. This lab uses the Vivado IP
example design.

• Lab 10: Use the IBERT UltraScale+ PS-GTR transceiver to evaluate and monitor PS-GTR
transceivers in AMD Zynq™ UltraScale+™ MPSoC devices. This lab is purely software-based,
setting up and testing the processing system (PS) side of the Zynq UltraScale+ MPSoC with no
programmable logic (PL).

Connecting the Boards and Cables

1. Connect the Digilent cable from the Digilent cable connector to a USB port on your
computer.
2. Connect the two SMA cables (for lab 5 only) as follows:
a. Connect one SMA cable from J19 (TXP) to J17 (RXP).
b. Connect the other SMA cable from J20 (TXN) to J66 (RXN).

The relative locations of SMA cables on the board are shown in Setup Requirements.

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Vivado Design Suite Tutorial: Programming and Debugging 11
 Lab 1: Using the Netlist Insertion Method to Debug a Design

Lab 1

Using the Netlist Insertion Method

to Debug a Design
In this lab, you mark signals for debugging in the source HDL and the post-synthesis netlist. You
can create an Integrated Logic Analyzer (ILA) core and take the design through implementation.
Finally, you use the AMD Vivado™ tool to connect to the KC705 target board and debug your
design with the Vivado Integrated Logic Analyzer.

Step 1: Creating a Project with the Vivado

New Project Wizard
To create a project, use the New Project wizard to name the project, to add RTL source files and
constraints, and to specify the target device.

1. Invoke the Vivado IDE.

2. In the Getting Started page, click Create Project to start the New Project wizard. Click Next.
3. In the Project Name page, name the new project proj_netlist and provide the project location
(C:/Vivado_Debug). Ensure that Create Project Subdirectory is selected and click Next.
4. In the Project Type page, specify the type of project to create as RTL Project. Click Next.
5. In the Add Sources page:
a. Set Target Language to VHDL.
b. Click the “+” sign, and click Add Files.
c. In the Add Source Files dialog box, navigate to the /src/lab1 directory.
d. Select all VHD source files, and click OK.
e. Verify that the files are added, and Copy Sources into the project is selected.
6. Click Add.
7. In the Add Directories dialog box, navigate to the /src/lab1 directory.
8. Select sine_high, sine_low, and sine_mid directories and click Select.
9. Verify that the directories are added. Click Next.

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Vivado Design Suite Tutorial: Programming and Debugging 12
 Lab 1: Using the Netlist Insertion Method to Debug a Design

10. In the Add Constraints dialog box, click the “+” sign, and click Add Files.
11. Navigate to /src/lab1 directory and select sinegen_demo_kc705.xdc. Click Next.
12. In the Default Part dialog box, specify the xc7k325tffg900-2 part for the KC705 platform.
You can also select Boards and select Kintex 7 KC705 Evaluation Platform. Click Next.
13. Review the New Project Summary page. Verify that the data appears as expected, per the
previous steps, and click Finish.
Note: It could take a moment for the project to initialize.

Step 2: Synthesizing the Design

1. In the Project Manager, click Settings, as shown in the following figure.

IMPORTANT! As an optional step, in the Settings dialog box, select Synthesis from the left and
change flatten hierarchy to none. The reason for changing this setting to none is to prevent the
synthesis tool from performing boundary optimizations for this tutorial.

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Vivado Design Suite Tutorial: Programming and Debugging 13
 Lab 1: Using the Netlist Insertion Method to Debug a Design

2. In the Vivado Flow Navigator, expand the Synthesis drop-down list, and click Run Synthesis.
In the Launch Runs dialog box, accept all the default settings (Launch runs on local host), and
click OK.
Note: When synthesis runs, a progress indicator shows that synthesis is occurring. This could take a
few minutes.

3. In the Synthesis Completed dialog box, click Cancel, as shown in the following figure. You
implement the design later.

Step 3: Probing and Adding Debug IP

To add a Vivado ILA core to the design, take advantage of the integrated flows between the
Vivado IDE and Vivado logic analyzer.

In this step, you accomplish the following tasks:

• Add debug nets to the project.

• Run the Set Up Debug wizard.
• Implement and open the design.
• Generate the bitstream.

Adding Debug Nets to the Project

Following are some ways to add debug nets using the Vivado IDE:

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Vivado Design Suite Tutorial: Programming and Debugging 14
 Lab 1: Using the Netlist Insertion Method to Debug a Design

• Add MARK_DEBUG attribute to HDL files.

• VHDL:
attribute mark_debug : string;
attribute mark_debug of sine : signal is "true";
attribute mark_debug of sineSel : signal is "true";

• Verilog:
(* mark_debug = "true" *) wire sine;
(* mark_debug = "true" *) wire sineSel;

This method lets you probe signals at the HDL design level. This can prevent optimization that
might otherwise occur to that signal. It also lets you pick up the signal tagged for post-
synthesis, so you can insert these signals into a debug core and observe the values on this
signal during FPGA operation. This method gives you the highest probability of preserving
HDL signal names after synthesis.
• Right-click and select Mark Debug or Unmark Debug on a synthesized netlist.
This method is flexible because it allows probing the synthesized netlist in the Vivado IDE and
allows you to add/remove MARK_DEBUG attributes at any hierarchy in the design. In
addition, this method does not require HDL source modification. However, there can be
situations where synthesis might not preserve the signals due to netlist optimization involving
absorption or merging of design structures.
• Use a Tcl prompt to set the MARK_DEBUG attribute on a synthesized netlist.
set_property mark_debug true [get_nets -hier [list {sine[*]}]]

This applies the MARK_DEBUG on the current, open netlist.

This method is flexible because you can turn MARK_DEBUG on and off by modifying the Tcl
command. In addition, this method does not require HDL source modification. However, there
might be situations where synthesis does not preserve the signals due to netlist optimization
involving absorption or merging of design structures.

In the following steps, you learn how to add debug nets to HDL files and the synthesized design
using Vivado IDE.

TIP: Before proceeding, make sure that the Flow Navigator on the left panel is enabled.

Use Ctrl-Q to toggle it off and on.

1. In the Flow Navigator under the Synthesis drop-down list, click Open Synthesized Design as
shown in the following figure.

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Vivado Design Suite Tutorial: Programming and Debugging 15
 Lab 1: Using the Netlist Insertion Method to Debug a Design

2. In the Window drop-down menu, select Debug. When the Debug window opens, click the
window if it is not already selected.
3. Expand the Unassigned Debug Nets folder. The following figure shows those debug nets that
were tagged with MARK_DEBUG attributes in sinegen_demo.vhd.

4. In the Netlist window, select the Netlist tab and expand Nets. Select the following nets for
debugging as shown in the following figure.
• GPIO_BUTTONS_IBUF[0] and GPIO_BUTTONS_IBUF[1]: Nets folder under the top-level
hierarchy
• sel(2): Nets folder under the U_SINEGEN hierarchy

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Vivado Design Suite Tutorial: Programming and Debugging 16
 Lab 1: Using the Netlist Insertion Method to Debug a Design

• sine(20): Nets folder under the U_SINEGEN hierarchy

Note: These signals represent the significant behavior of this design and are used to verify and debug
the design in subsequent steps.

5. Right-click the selected nets and select Mark Debug as shown in the following figure.

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Vivado Design Suite Tutorial: Programming and Debugging 17
 Lab 1: Using the Netlist Insertion Method to Debug a Design

6. Mark nets for debug in the Tcl Console. Mark nets “sine(20)” under the U_SINEGEN hierarchy
for debug by executing the following Tcl command.
set_property mark_debug true [get_nets -hier [list {sine[*]}]]

TIP: In the Debug window, you can see the unassigned nets you selected. In the Netlist window, you
can also see the green bug icon next to each scalar or bus, which indicates that a net has the attribute
mark_debug = true as shown in the following two figures.

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Vivado Design Suite Tutorial: Programming and Debugging 18
 Lab 1: Using the Netlist Insertion Method to Debug a Design

Running the Set Up Debug Wizard

1. From the Debug window tool bar or Tools drop-down menu, select Set Up Debug. The Set up
Debug wizard opens.

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Vivado Design Suite Tutorial: Programming and Debugging 19
 Lab 1: Using the Netlist Insertion Method to Debug a Design

2. When the Set up Debug wizard opens, click Next.

3. In the Nets to Debug page, shown in the following figure, ensure that all the nets are added
for debug and click Next.

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Vivado Design Suite Tutorial: Programming and Debugging 20
 Lab 1: Using the Netlist Insertion Method to Debug a Design

4. In the ILA Core Options page, go to Trigger and Storage Settings section and select both
Capture Control and Advanced Trigger. Click Next.
5. In the Setup Debug Summary page, make sure that all the information is correct and as
expected. Click Finish.

Upon clicking Finish, the relevant XDC commands that insert the ILA core(s) are generated.

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Vivado Design Suite Tutorial: Programming and Debugging 21
 Lab 1: Using the Netlist Insertion Method to Debug a Design

Step 4: Implementing and Generating

Bitstream
1. In the Flow Navigator, under Program and Debug, click Generate Bitstream.

2. In the Save Project dialog box, click Save. If a dialog box appears indicating this causes the
Synthesis results to go out of date, click OK. This applies the MARK_DEBUG attributes on
the newly marked nets. You can see those constraints by inspecting the
sinegen_demo_kc705.xdc file.
3. When the No Implementation Results Available dialog box pops up, click Yes. In the Launch
Runs dialog box, accept all of the default settings (Launch runs on local host) and click OK.
4. When the bitstream generation completes, the Bitstream Generation Completed dialog box
pops up. Click OK.
5. In the dialog box, asking you to close the synthesized design before opening the implemented
design. Click Yes.
6. Examine the Timing Summary report to ensure all the specified timing constraints are met.

Proceed to Lab 5: Using the Vivado Logic Analyzer to Debug Hardware to complete the rest
of the steps for debugging the design.

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Vivado Design Suite Tutorial: Programming and Debugging 22
 Lab 2: Using the HDL Instantiation Method to Debug a Design

Lab 2

Using the HDL Instantiation Method

to Debug a Design
The HDL instantiation method is one of the two methods supported in the AMD Vivado™ tool
debug probing. For this flow, you generate an ILA IP using the Vivado IP catalog and manually
instantiate the core in a design, as you would with any other IP.

Step 1: Creating a Project with the Vivado

New Project Wizard
To create a project, use the New Project wizard to name the project, add RTL source files and
constraints, and specify the target device.

1. Invoke the Vivado IDE.

2. In the Quick Start tab, click Create Project to start the New Project wizard. Click Next.
3. In the Project Name page, name the new project proj_hdl and provide the project location
(C:/Vivado_Debug). Ensure that the Create project subdirectory is selected. Click Next.
4. In the Project Type page, specify the Type of Project to create as RTL Project. Click Next.
5. In the Add Sources page:
a. Set Target Language to VHDL.
b. Click the “+” sign, and click Add Directories.
c. In the Add Source Directories dialog box, navigate to the /src/lab2 directory, and
choose the sine_high, sine_low, sine_mid, and ila_0 directories. Click Select.
d. Verify that the directories are added, and Copy Sources into Project is selected.
e. Click the “+” sign, and click Add File.
f. In the Add Source Files dialog box, navigate to the/src/lab2 directory and choose
debounce.vhd, fsn.vhd, sinegen.vhd, and sinegen_demo_inst.vhd files. Click
OK.
g. Verify that the sources and directories are added, and that Copy Sources into Project is
selected. Click Next.

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Vivado Design Suite Tutorial: Programming and Debugging 23
 Lab 2: Using the HDL Instantiation Method to Debug a Design

6. In the Add Constraints dialog box, click the “+” sign, and click Add Files.
7. Navigate to /src/lab1 directory and select sinegen_demo_kc705.xdc. Click Next.
8. In the Default Part dialog box, specify the xc7k325tffg900-2 part for the KC705 platform.
You can also select Boards and select Kintex 7 KC705 Evaluation Platform. Click Next.
9. Review the New Project Summary page. Verify that the data appears as expected per the
previous steps. Click Finish.
10. In the Sources window in Vivado IDE, expand sinegen_demo_inst to see the source files for
this lab.
Note: ila_0 core is added to the project.

11. Double-click the sinegen_demo_inst.vhd file, shown in the following figure to open it
and inspect the instantiation and port mapping of the ILA core in the HDL code.

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Vivado Design Suite Tutorial: Programming and Debugging 24
 Lab 2: Using the HDL Instantiation Method to Debug a Design

Step 2: Synthesize, Implement, and Generate

Bitstream
1. From the Program and Debug drop-down list in Flow Navigator, click Generate Bitstream.
This synthesizes, implements, and generates a bitstream for the design.

2. The No Implementation Results Available dialog box appears. Click Yes. In the Launch Runs
dialog box, accept all of the default settings (Launch runs on local host) and click OK.
3. After bitstream generation completes, the Bitstream Generation Completed dialog box
appears. Open Implemented Design is selected by default. Click OK.
4. In the Design Timing Summary window, ensure all timing constraints are met.

5. Proceed to Lab 5 to complete the rest of this lab.

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 Lab 3: Using a VIO Core to Debug a Design in Vivado Design Suite

Lab 3

Using a VIO Core to Debug a Design

in Vivado Design Suite
The Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive
internal FPGA signals in real time. The number and width of the input and output ports are
customizable in size to interface with the FPGA design. Because the VIO core is synchronous to
the design being monitored and/or driven, all design clock constraints that are applied to your
design are also applied to the components inside the VIO core. Run time interaction with this
core requires the use of the AMD Vivado™ tool's logic analyzer feature. The following figure is a
block diagram of the new VIO core.

Figure 2: VIO Block Diagram

VIO

CLK

PROBE_IN0[0:0] PROBE_OUT0[255:0]

PROBE_IN1[255:0] Input Registers and PROBE_OUT1[0:0]

... Out Registers ...
Activity Detectors PROBE_OUT255[127:0]
PROBE_IN255[31:0]

Interface to JTAG through Debug Hub

X27387-111522

This lab walks you through the steps of instantiating and configuring the VIO core. It walks you
through the steps of connecting the I/Os of the design to the VIO core. This way, you can debug
your design when you do not have access to the hardware or the hardware is remotely located.

The following ports are created:

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 Lab 3: Using a VIO Core to Debug a Design in Vivado Design Suite

• One four-bit PROBE_IN0 port. This has two bits to monitor the two-bit Sine Wave selector
outputs from the finite state machine (FSM) and other two bits to mimic the state of the other
two LEDs on the board. You configure these four-bit signals as LEDs during run time to mimic
the LEDs displayed on the KC705 board.
• One two-bit PROBE_OUT0 port to drive the input buttons on the FSM. You configure it so
one bit can be used as a toggle switch during run time to mimic PUSH_BUTTON switch SW3,
and the second bit is used as PUSH_BUTTON switch SW6.

Step 1: Creating a Project with the Vivado

New Project Wizard
To create a project, use the New Project wizard to name the project, add RTL source files and
constraints, and specify the target device.

1. Invoke Vivado IDE.

2. In the Quick Start tab, click Create Project to start the New Project wizard. Click Next.
3. In the Project Name page, name the new project proj_hdl_vio and provide the project
location (C:/Vivado_Debug). Ensure that the Create project subdirectory is selected. Click
Next.
4. In the Project Type page, specify the Type of Project to create as RTL Project. Click Next.
5. In the Add Sources page:
a. Set Target Language to VHDL.
b. Click Add Files.
c. In the Add Source Files dialog box, navigate to the /src/lab3 directory.
d. Select all VHD source files, and click OK.
e. Verify that the files are added, and Copy Sources into Project is selected.
6. Click the “+” sign, and click Add Directories.
7. In the Add Source Directories dialog box, navigate to the /src/lab3 directory and choose
the sine_high, sine_low, sine_mid, and ila_0 directories. Click Select.
8. Verify that the directories are added, and Copy sources into the project are selected. Click
Next.
9. In the Add Constraints dialog box, click the “+” sign, and click Add Files.
10. Navigate to the /src/lab3 directory and select sinegen_demo_kc705.xdc. Click Next.
11. In the Default Part page, specify the xc7k325tffg900-2 platform. You can also select Boards
and select Kintex 7 KC705 Evaluation Platform. Click Next.

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 Lab 3: Using a VIO Core to Debug a Design in Vivado Design Suite

12. Review the New Project Summary page. Verify that the data appears as expected by the
previous steps. Click Finish.
Note: It might take a moment for the project to initialize.

13. In the Sources window in Vivado IDE, expand sinegen_demo_inst_vio to see the source
files for this lab.
Note: The ila_0 core is added to the project. However, vio_0 (the VIO core) is missing.

14. Instantiate and configure this VIO core as follows. From the Flow Navigator, click IP Catalog,
expand Debug & Verification, expand Debug, and double-click VIO. The Customize IP dialog
box opens.
15. On the General Options tab, leave the Component Name as its default value of vio_0, set
Input Probe Count to 1, Output Probe Count to 1, and select the Enable Input Probe Activity
Detectors check box.

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 Lab 3: Using a VIO Core to Debug a Design in Vivado Design Suite

16. On the PROBE_IN Ports tab, set Probe Width to 4.

17. On the PROBE_OUT Ports tab, set Probe Width to 2 and Initial Value to 0x0.

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 Lab 3: Using a VIO Core to Debug a Design in Vivado Design Suite

18. Click OK to generate the IP. The Generate Output Products dialog box appears. Click
Generate. An additional dialog box can appear, indicating an out-of-context module run is
launched. If so, click OK.

Output product generation should take less than a minute. At this point, you have finished
customizing the VIO. This core is already instantiated in the top-level design.

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 Lab 3: Using a VIO Core to Debug a Design in Vivado Design Suite

At this point, the Sources window should look as shown in the following figure.

19. Double-click sinegen_demo_inst.vhd in the Sources window to open it, and inspect the
instantiation and port mapping of the ILA core in the HDL code.

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 Lab 3: Using a VIO Core to Debug a Design in Vivado Design Suite

Step 2: Synthesize, Implement, and Generate

the Bitstream
1. From the Program and Debug drop-down list in Flow Navigator, click Generate Bitstream.
This synthesizes, implements, and generates a bitstream for the design
2. The Missing Implementation Results dialog box appears. Click OK.
3. After bitstream generation completes, the Bitstream Generation Completed dialog box
appears. Open Implemented Design is selected by default. Click OK.
4. Inspect the Timing Summary report and ensure all timing constraints are met.

5. Proceed to Lab 5: Using the Vivado Logic Analyzer to Debug Hardware to complete the rest
of the steps for debugging the design. Proceed to the Verifying the VIO Core Activity (Only
Applicable to Lab 3) section in Lab 5 Step 2 to complete the rest of this lab.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

Lab 4

Using the Synplify Pro Synthesis

Tool and Vivado Design Suite to
Debug a Design
This simple tutorial shows how to do the following:

• Create a Synplify Pro project for the wave generator design.

• Mark nets for debug in the Synplify Pro constraints file and VHDL source files.
• Synthesize the Synplify Pro project to create an EDIF netlist.
• Create an AMD Vivado™ project based on the Synplify Pro netlist.
• Use the Vivado IDE to setup and debug the design from the synthesized design using Synplify
Pro.

Step 1: Create a Synplify Pro Project

1. Launch Synplify Pro and select File → New.
2. Set File Type to Project File (Project) as highlighted in the following figure.
3. In the New File Name box, enter synplify_1.
4. Click OK.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

5. If you get a dialog box asking you to create a non-existing directory, click OK.

6. In the left panel of the Synplify Pro window, click Add File as shown in the following figure.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

7. In the Add Files to Project dialog box, change the Files of Type to HDL File. Navigate to
C:\Vivado_Debug\src\lab4, which shows all the VHDL source files needed for this lab.
Select the following three files by pressing the Ctrl key and clicking on them.
• debounce.vhd
• fsm.vhd
• sinegen_demo.vhd
8. Click Add.

9. In the same dialog box, set Files of type to Constraints Files. This shows the
synplify_1.sdc file. Select the file and click Add as shown in the following figure.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

10. In the same dialog box, set Files of type to FPGA Constraint Files. This shows the
synplify_1.fdc file. Select the file and click Add as shown in the following figure. Click OK.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

11. Now, you need to set the implementation options.

12. Click Implementation Options in the Synplify Pro window, as shown in the following figure.

13. This includes the Implementation Options dialog box, as shown in the following figure. In the
Device tab, set Technology to Xilinx Kintex7, Part to XC7K325T, Package to FFG900, and
Speed to -2. Leave all the other options at their default values. Click OK.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

14. You need to preserve the net names that you want to debug by putting attributes in the HDL
files. These attributes are already placed in the sinegen_demo.vhd, file of this tutorial.
Open the sinegen_demo.vhd file and inspect the lines shown.

15. You also can specify the MARK_DEBUG attributes in the source HDL files to mark the signals
for debugging, as shown in the code snippet from singen_demo.vhd file.

16. The synplify_1.sdc file contains various kinds of constraints, such as pin location, I/O
standard, and clock definition. The synplify_1.fdc file contains directives for the
compiler. Here is where the nets of interest marked for debugging are located. The attribute
and the nets selected for debugging are shown in the following figure.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

In the previous constraints, sinegen is defined as a black box by using the syn_black_box
attribute. Second, the syn_no_prune attribute is used so that the I/Os of this block is not
optimized away. Finally, two nets, sine[20:0] and sel[1:0], are assigned the
MARK_DEBUG attribute such that these two nets should show up in the synthesized design
in AMD Vivado™ IDE for further debugging. For further information on these attributes, refer
to the Synplify Pro User Manual and Synplify Pro Reference Manual.

Step 2: Synthesize the Synplify Project

1. Before implementing the project, you need to set the name for the output netlist file. By
default, the name of the output netlist file is synplify_1.edf. To change the name of the
output file, type the following command at the Tcl command prompt:
%project -result_file "./rev_1/sinegen_demo.edf"

You use this file in Vivado IDE.

2. With all the settings in place, click the Run button in the left panel of the Synplify Pro window
to start synthesizing the design.

3. During synthesis, status messages appear in the Tcl Script tab. Warning messages are
expected, but there should not be any Error messages. To see detailed messages, click the
Messages tab in the bottom left-hand corner of the Synplify Pro console.
4. When synthesis completes, the output netlist is written to the file: rev_1/
sinegen_demo.edf
[Optional] To view the netlist select View → View Result File.
5. Click File → Save All to save the project, and click File → Exit.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

Step 3: Create DCPs for the Black Box Created

in Synplify Pro
The black box, sinegen, created in the Synplify Pro project, contains the Direct Digital Synthesizer
IP. You need to create a synthesized design for this block. To do this, create an RTL-type project
in Vivado IDE by the following steps:

1. Launch Vivado IDE.

2. Click Create Project. This opens up the New Project wizard. Click Next.
3. Under Project Name, set the project name to proj_synplify_netlist. Click Next.
4. Under Project Type, select RTL Project. Click Next.
5. Under Add Sources, click Add Files, navigate to the Vivado_Debug/src/lab4 folder and
select the sinegen.vhd file. Set Target Language to VHDL. Ensure that Copy sources into
the project box are selected. Click Next.
6. Click Add Files, navigate to the Vivado_Debug/src/lab4 folder, and select the
sine_high.xci, sine_low.xci, and sine_mid.xci files. Click Next.
7. Under Default Parts, select Boards and select the Kintex 7 KC705 Evaluation Platform and
the correct version for your hardware. Click Next.
8. Under New Project Summary, ensure all the settings are correct. Click Finish.
9. Once the project is created, in Vivado Flow Navigator, under the Project Manager folder, click
Settings. In the dialog box, in the left panel, click Synthesis. From the pull-down menu on the
right panel, set -flatten_hierarchy to none. Click OK.
10. In Vivado IDE Flow Navigator, under Synthesis Folder, click Run Synthesis.
11. When synthesis completes, the Synthesis Completed dialog box appears. Select Open
Synthesized Design and click OK.
12. Click File → Exit in Vivado IDE. When the OK to exit dialog box pops up, click OK.

Step 4: Create a Post Synthesis Project in

Vivado IDE
1. Launch the Vivado IDE.
2. Click Create Project. This opens up the New Project wizard. Click Next.
3. Set the Project Name to proj_synplify. Click Next.
4. Under Project Type, select Post-synthesis Project. Click Next.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

5. Under Add Netlist Sources, click Add Files, navigate to the Vivado_Debug/synopsys/
rev_1 folder, and select sinegen_demo.edf. Click OK.
6. Add the netlist file created in the previous section. Click Add Files again, navigate to the
proj_synplify_netlist/proj_synplify_netlist.runs/synth1 folder and select
sinegen.dcp.
Add the DCP files created for the sub-module IPs in the previous section. Click Add
Directories again, navigate to the proj_synplify_netlist/
proj_synplify_netlist.srcs/sources_1/ip folder and select the following:
• sine_high
• sine_mid
• sine_low
Click OK in the Add Source Files dialog box. In the Add Netlist Sources dialog box ensure that
Copy Sources into Project is selected. Click Next.
7. Click Add Files, navigate to the Vivado_Debug/src folder, and select the
sinegen_demo_kc705.xdc file. This file has the appropriate constraints needed for this
Vivado project. Click OK in the Add Constraints File dialog box. In the Add Constraints
(optional) dialog box ensure that Copy Constraints into Project is selected. Click Next.
8. Under Default Part, select Boards and select Kintex 7 KC705 Evaluation Platform and the
right version number for your hardware. Click Next.
9. Under New Project Summary, ensure that all the settings are correct and click Finish.
10. In the Sources window, ensure sinegen_demo.edf is selected as the top module.

Step 5: Add More Debug Nets to the Project

1. In Vivado IDE, in the Flow Navigator, select Open Synthesized Design from the Netlist
Analysis folder.
2. Select the Netlist tab in the Netlist window to expand Nets. Select the following nets for
debugging:
• GPIO_BUTTONS_c(2)
• sine (20)
After selecting all the specified nets, right-click the nets and click Mark Debug, as shown in
the following figure.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

3. You should be able to see all the nets that are marked for debug, as shown in the following
figure.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

Running the Set Up Debug Wizard

1. Click the Set up Debug icon in the Debug window or select the Tools menu, and select Set up
Debug. The Set up Debug wizard opens.

2. Click through the wizard to create Vivado logic analyzer debug cores, keeping the default
settings.
Note: In the Specify Nets to Debug dialog box, ensure that all the nets marked for debug have the
same clock domain.

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 Lab 4: Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a
Design

Step 6: Implementing the Design and

Generating the Bitstream
1. In the Flow Navigator, under the Program and Debug drop-down list, click Generate
Bitstream.
2. In the Save Project dialog box, click Save.
3. When the Bitstream generation finishes, the Bitstream Generation Completed dialog box
pops up and Open Implemented Design is selected by default. Click OK.
4. If you get a dialog box asking to close the synthesized design before opening the
implemented design, click Yes.
5. Proceed to Lab 5: Using the Vivado Logic Analyzer to Debug Hardware to complete the rest
of this lab.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

Lab 5

Using the Vivado Logic Analyzer to

Debug Hardware
The final step in debugging is to connect to the hardware and debug your design using the
Integrated Logic Analyzer (ILA). Before continuing, make sure you have the KC705 hardware
plugged into a machine.

In this step, you learn:

• How to debug the design using the AMD Vivado™ logic analyzer.
• How to use the currently supported Tcl commands to communicate with your target board
(KC705).
• How to discover and correct a circuit problem by identifying unintended behaviors of the
push-button switch.
• Useful techniques for triggering and capturing design data.

Step 1: Verifying Operation of the Sine Wave

Generator
After doing some setup work, you use Vivado logic analyzer to verify that the sine wave
generator is working correctly. Your two primary objectives are to verify that:

• All sine wave selections are correct.

• The selection logic works correctly.

Target Board and Server Set Up

• Connecting to the Target Board Remotely: If you plan to connect remotely, you ensure that
the KC705 board is plugged into a machine and you are running an hw_server application on
that machine. If you plan to connect locally, skip steps 1-5 and go directly to the Connecting
to the Target Board Locally section.

1. Connect the Digilent USB JTAG cable of your KC705 board to a USB port on a Windows
system.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

2. Ensure that the board is plugged in and powered on.

3. Power cycle the board to clear the device.
4. Turn DIP switch positions (pin 1 on SW11, De-bounce Enable) to the OFF position.
5. Assuming you are connecting your KC705 board to a 64-bit Windows machine and you
are running the hw_server from the network instead of your local drive, open a cmd
prompt and type the following:
<Xilinx_Install>\Vivado\2020.x\bin\hw_server

Leave this cmd prompt open while the hw_server is running. Note the machine name you
are using. You use this later when opening a connection to this instance of the hw_server
application.

• Connecting to the Target Board Locally: If you plan to connect locally, ensure that the KC705
board is plugged into a Windows machine and perform the following steps:

1. Connect the Digilent USB JTAG cable of your KC705 board to a USB port on a Windows
system.
2. Ensure that the board is plugged in and powered on.
3. Power cycle the board to clear the device.
4. Turn the DIP switch positions (pin 1 on SW11, De-bounce Enable) to the OFF position.

Using the Vivado Integrated Logic Analyzer

1. In the Flow Navigator, under Program and Debug, select Open Hardware Manager.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

2. The Hardware Manager window opens. Click Open Target → Open New Target.

3. The Open New Hardware Target wizard opens. Click Next.

4. In the Hardware Server Settings page, type the name of the server (or select Local server if
the target is on the local machine) in the Connect to field. Click Next.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

Note: Depending on your connection speed, this can take about 10 to 15 seconds.

5. If there is more than one target connected, you see multiple entries in the Select Hardware
Target page. In this tutorial, there is only one target, as shown in the following figure. Click
Next.

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Vivado Design Suite Tutorial: Programming and Debugging 48
 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

6. In the Open Hardware Target Summary page, click Finish as shown in the following figure.

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Vivado Design Suite Tutorial: Programming and Debugging 49
 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

7. Wait for the connection to the hardware to complete. The dialog in the following figure
appears while hardware is connecting.

After the connection to the hardware target is made, the Hardware window appears as in the
following figure.
Note: The Hardware tab in the Debug view shows the hardware target and XC7K325T device detected
in the JTAG chain.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

8. Next, program the XC7K325T device using the previously created .bit bitstream by right-
clicking the XC7K325T device and selecting Program Device as shown in the following
figure.

9. In the Program Device dialog box verify that the .bit and .ltx files are correct for the lab
that you are working on and click Program to program the device as shown in the following
figure.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

CAUTION! The file paths of the bitstream and debug probes to be programmed are different for
different labs. Ensure that the relative paths are correct.

Note: Wait for the program device operation to complete. This can take a few minutes.

10. Ensure that an ILA core was detected in the Hardware panel of the Debug view.

11. The Integrated Logic Analyzer dashboard opens, as shown in the following figure.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

Verifying Sine Wave Activity

1. In the Hardware window, click Run Trigger Immediate to trigger and capture data
immediately as shown in shown in the following figure.

2. In the Waveform window, verify that there is activity on the 20-bit sine signal as shown in
the following figure.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

Displaying the Sine Wave

1. Right-click U_SINEGEN/sine[19:0] signals, and select Waveform Style → Analog as shown in
the following figure.

CAUTION! The waveform does not look like a sine wave. This is because you must change the radix
setting from Hex to Signed Decimal, as described in the following subsection.

2. Right-click U_SINEGEN/sine[19:0] signals, and select Radix → Signed Decimal.

You should now be able to see the high frequency sine wave as shown in the following figure
instead of the square wave.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

Correcting Display of the Sine Wave

To view the mid, and low frequency output sine waves, perform the following steps:

1. Cycle the sine wave sequential circuit by pressing the GPIO_SW_E push button as shown in
the following figure.

2. Click Run Trigger Immediately again to see the new sine selected sine wave. You should see
the mid frequency as shown in the following figure. The sel signal also changed from 0 to 1
as expected.

3. Repeat step 1 and 2 to view other sine wave outputs.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

Note: As you sequence through the sine wave selections, you can see that the LEDs do not light up in
the expected order. You debug this in the next section of this tutorial. For now, verify for each LED
selection that the correct sine wave displays.

Note: The signals in the Waveform window are re-arranged in the previous three figures.

Step 2: Debugging the Sine Wave Sequencer

State Machine (Optional)
As you corrected the sine wave display, the LEDs might not have lit up in sequence as you
pressed the Sine Wave Sequencer button. With each push of the button, there should be a single,
cycle-wide pulse on the GPIO_BUTTONS_re[1] signal. If there is more than one, the behavior
of the LEDs becomes irregular. In this section of the tutorial, use Vivado logic analyzer to probe
the sine wave sequencer state machine, and to view and repair the root cause of the problem.

Before starting the actual debug process, it is important to understand more about the sine wave
sequencer state machine.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

Sine Wave Sequencer State Machine Overview

The sine wave sequencer state machine selects one of the four sine waves to be driven onto the
sine signal at the top-level of the design. The state machine has one input and one output. The
following figure shows the schematic elements of the state machine. Refer to this diagram as you
read the following description and as you perform the steps to view and repair the state machine
glitch.

• The input is a scalar signal called “button”. When the button input equals “1”, the state
machine advances from one state to the next.
• The output is a 2-bit signal vector called “Y”, and it indicates which of the four sine wave
generators is selected.

The input signal button connects to the top-level signal GPIO_BUTTONS_re[1], which is a low-
to-high transition indicator on the Sine Wave Sequencer button. The output signal Y connects to
the top-level signal, sineSel, which selects the sine wave.

Figure 3: Sine Wave Sequence Button Schematic

Viewing the State Machine Glitch

You cannot troubleshoot the issue identified previously by connecting a debug probe to the
GPIO_BUTTON [1] input signal itself. The GPIO_BUTTON [1] input signal is a PAD signal that
is not directly accessible from the FPGA fabric. Instead, you must trigger low-to-high transitions
(rising edges) on the GPIO_BUTTON_IBUF signal, which is connected to the output of the input
buffer of the GPIO_BUTTON [1] input signal.

As described earlier, the glitch reveals itself as multiple low-to-high transitions on the
GPIO_BUTTONS_IBUF_1 signal, but it occurs intermittently. Because it could take several
button presses to detect it, you now set up the Vivado logic analyzer tool to Repetitive Trigger
Run Mode. This setting makes it easier to repeat the button presses and look for the event in the
Waveform viewer.

1. Under the Settings tab for hw_ila_1, configure the following:

• Trigger Mode to BASIC_ONLY
• Capture Mode to BASIC
• Window Data Depth to 1024

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• Trigger position to 512

• Press the + button in the Trigger Setup window and add probe GPIO_BUTTONS_IBUF_1.
Change the Value field to RX by selecting the value RX in the Value field, as shown in the
following figure.

CAUTION! For different labs the GPIO_BUTTONS_IBUF might show up differently or have a
different name such as button_in4_in. This might also show up as two individual bits or two bits
lumped together in a bus. Ensure that you are using bit 1 of this bus to set up your trigger
condition. For example, in case of a two-bit bus, you set the Value field in the Compare Value dialog
box to RX.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

2. Select Enable Auto Re-trigger mode on the ILA debug core as shown as follows.

CAUTION! The ILA properties window can look slightly different for different labs.

When you issue a Run Trigger or a Run Trigger Immediate command after setting the Auto
Retrigger mode, the ILA core does the following repetitively until you disable the Auto
Retrigger mode option:
• Arms the trigger.
• Waits for the trigger.
• Uploads and displays waveforms.
3. On the KC705 board, press the Sine Wave Sequencer button until you see multiple
transitions on the GPIO_BUTTONS_IBUF_1 signal (this could take 10 or more tries). This is a
visualization of the glitch that occurs on the input. An example of the glitch is shown in the
following two figures.

CAUTION! You have to repeat the previous two steps repeatedly to see the glitch. After you see the
glitch, you can observe that the signal glitches are not exactly in the same location as shown in the
following figure.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

Fixing the Signal Glitch and Verifying the Correct

State Machine Behavior
The multiple transition glitch or “bounce” occurs because the mechanical button is making and
breaking electrical contact as you press it. To eliminate this signal bounce, a “de-bouncer” circuit
is required.

1. Enable the de-bouncer circuit by setting DIP switch position on the KC705 board (labeled
De-bounce Enable in Figure 1) to the ON or UP position.
2. Enable the Auto-Retrigger mode on the ILA debug core and click RunTrigger on the ILA core,
and
• Ensure that you no longer see multiple transitions on the GPIO_BUTTON_re[1] signal on a
single press of the Sine Wave Sequencer button.
• Verify that the state machine is working correctly by ensuring that the sineSel signal
transitions from 00 to 01 to 10 to 11 and back to 00 with each successive button press.

Verifying the VIO Core Activity (Only Applicable to

Lab 3)
1. From the Program and Debug section in Flow Navigator, click Open Hardware Manager.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

The Hardware Manager window opens.

2. Click Open a new hardware target.

3. The Open New Hardware Target wizard opens. Click Next.

4. In the Hardware Server Settings page, type the name of the server (or select Local server if
the target is on the local machine) in the Connect to field.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

5. Ensure that you are connected to the right target by selecting the target from the Hardware
Targets page. If there is only one target, that target is selected by default. Click Next.
6. In the Set Hardware Target Properties page, click Next.
7. In the Open Hardware Target Summary page, verify that all the information is correct, and
click Finish.
8. Program the device by selecting and right-clicking the device in the Sources window and
selecting Program Device.

9. In the Program Device dialog box, ensure that the bit file to be programmed is correct. Click
OK.

10. After the FPGA is programmed, you see the VIO and the ILA core in the Hardware window.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

You now have a debug dashboard for the ILA core as shown in the following figure.

11. Click Run Trigger Immediate to capture the data immediately.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

12. Make sure that there is activity on the sine [19:0] signal.
13. Select the sine signal in the Waveform window, right-click and select Waveform Style →
Analog.
14. Select the sine signal in the Waveform window again, right-click and select Radix → Signed
Decimal. You should be able to see the sine wave in the Waveform window.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

15. Instead of using the GPIO_SW push button to cycle through each different sine wave output
frequency, you are going to use the virtual “push_button_vio” toggle switch from the VIO
core.
16. You can now customize the ILA dashboard options to include the VIO window. This allows
you to toggle the VIO output drivers and observe the impact on the ILA waveform window all
in one dashboard. Slide out the Dashboard Options window.

17. Add the VIO window to the ILA dashboard by selecting hw_vio_1.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

Note: The ILA dashboard now contains the VIO window as well.

18. Adjust the Trigger Setup – hw_ila_1 window and the hw_vio_1 window so that they are side
by side, as shown in the following figure.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

19. In the hw_vio_1 window, select the “+” button, and select all the probes under hw_vio_1.
20. Click OK.
Note: The initial values of all the probes.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

21. Note the values on all probes in the hw_vio_1 window.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

22. Set the push_button_reset output probe by right-clicking push_button_reset and select
Toggle Button.
This toggles the output driver from logic from 0 to 1 to 0 as you click. It is similar to the
actual push button behavior, though there is no bouncing mechanical effect as with a real
push button switch.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

The Value field for push_button_reset is highlighted.

23. Click in the Value field to change its value to 1.

24. Follow the previous step to change the push_button_vio to Toggle button as well.
25. Set these two bits of the “sineSel” input probe by right-clicking PROBE_IN0[0] and
PROBE_IN0[1] and selecting LED.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

26. In the Select LED Colors dialog box, pick the Low Value Color and the High Value Color of
the LEDs as you desire and click OK.

27. When finished, your VIO Probes window in the Hardware Manager should look similar to the
following figure.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

28. To cycle through each different sine wave output frequency using the virtual
“push_button_vio” from the VIO core, perform the following simple steps:
a. Toggle the value of the “push_button_vio” output driver from 0 to 1 to 0 by clicking on
the logic displayed under the Value column. You notice the sineSel LEDs changed
accordingly – 0, 1, 2, 3, 0, etc.

b. Click Run Trigger for hw_ila_1 to capture and display the selected sine wave signal from
the previous step.

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 Lab 5: Using the Vivado Logic Analyzer to Debug Hardware

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

Lab 6

Using the ECO Flow to Replace

Debug Probes Post Implementation
This simple tutorial shows you how to replace nets connected to an ILA core in a placed and
routed design checkpoint using the AMD Vivado™ Design Suite Engineering Change Order (ECO)
flow.

Note: To learn more about using the ECO flow, refer to the Debugging Designs Post Implementation chapter
in the Vivado Design Suite User Guide: Programming and Debugging (UG908).

1. Open the Vivado Design Suite, and select File → Open Checkpoint.

2. Open the routed checkpoint that you created in Lab 2: Using the HDL Instantiation Method
to Debug a Design.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

Change the layout in the Vivado Design Suite toolbar drop-down to ECO.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

Note: The Flow Navigator window now changes to ECO Navigator with a different set of options.

3. In the ECO Navigator window, click Replace Debug Probes to bring up the Replace Debug
Probes dialog box. Note the Debug Hub and ILA cores in the design.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

IMPORTANT! AMD strongly recommends that you do not replace the clock nets associated with ILA
and Debug Hub cores.

4. In the Replace Debug Probes dialog box, highlight the probes whose nets you want to
change. In this lab you replace the GPIO_BUTTONS_dly[0] net that is probed.
5. Click the Edit Probes button to the right of the GPIO_BUTTONS_dly[0] probe net to bring up
the Choose Nets dialog box.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

6. In the Choose Nets dialog box, choose the U_DEBOUNCE_0/clear net to replace the existing
GPIO_BUTTONS_dly[0] probe net. Click OK.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

7. Type for “*clear net” in the Name field and Click Find. Notice the U_DEBOUNCE_0 net in the
Found nets area. Select U_DEBOUNCE_0/clear net using the “->” arrow and click OK. The
U_DEBOUNCE_0/clear net to replaces the existing GPIO_BUTTONS_dly[0] probe net.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

8. Now click OK in the Replace Debug Probes dialog. An additional dialog box can appear if the
nets were marked with DONT_TOUCH indicating that it must be removed to proceed. If so,
click Unset Property and Continue.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

IMPORTANT! Check the Tcl Console to ensure that there are no Warnings/Errors.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

9. Save your modifications to a new checkpoint. Use the Save Checkpoint As option in the ECO
Navigator to bring up the Save Checkpoint As dialog box. Specify a file name for the .dcp file
and click OK.

10. Click Write Debug Probes in the ECO Navigator. When the Write Debug Probes dialog
appears, click OK to generate a new .ltx file for the debug probes.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

11. Click Generate Bitstream in the ECO navigator. When the Generate Bitstream dialog appears,
change the bit file name to project_sinegen_demo_routed_debug_changes.bit in
the Bit File field and click OK to generate a new .bit file that reflects the debug probe
changes.

12. Connect to the Vivado Hardware Manager by selecting Open Hardware Manager in the ECO
Navigator.
13. Connect to the local hardware server by following the steps in the Target Board and Server
Set Up section in Lab 5: Using the Vivado Logic Analyzer to Debug Hardware.
Program the device using the .bit file and.ltx files that you created in the previous steps.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

14. Select Window → Debug Probes from the Vivado Design Suite toolbar. Ensure that the
probes that were replaced in the previous steps 8 and 9, are reflected in the probes
associated with hw_ila_1.

15. Run the Trigger on the ILA. Ensure the probes that were replaced in the previous steps 8 and
9, are reflected in the Waveform window as well.

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 Lab 6: Using the ECO Flow to Replace Debug Probes Post Implementation

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

Lab 7

Debugging Designs Using the

Incremental Compile Flow
This lab introduces the AMD Vivado™ Incremental Compile Flow to add/edit/delete debug cores
to an earlier implementation of the design.

Procedure
This lab consists of five generalized steps followed by general instructions and supplementary
detailed steps that allow you to make choices based on your skill level as you progress through
the lab.

If you need help completing a general instruction, go to the detailed steps it, or if you are ready,
simply skip the step-by-step directions and move on to the next general instruction.

The lab has five primary steps as follows:

1. Step 1: Opening the Example Design and Adding a Debug Core

2. Step 2: Compiling the Reference Design
3. Step 3: Create New Runs
4. Step 4: Making Incremental Debug Changes
5. Step 5: Running Incremental Compile

Step 1: Opening the Example Design and

Adding a Debug Core
1. Start the Vivado IDE.
Load the Vivado IDE by doing one of the following:
• Double-click the Vivado IDE icon on the Windows desktop.
• Type vivado in a command terminal.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

From the Getting Started page, click Open Example Project.

2. In the Open Example Project dialog box, click Next.
3. Select the CPU (Synthesized) design template, and click Next.
4. In the Project Name dialog box, specify the following:
• Project name: project_cpu_incremental
• Project location: <Project_Dir>
Click Next.
5. In the Default Part screen, select xc7k70tfbg676-2 and click Next.
6. The New Project Summary screen appears, displaying project details. Review these and click
Finish.
7. When the Vivado IDE opens with the default view, open the Synthesized design.
8. In the Netlist window, select the set of signals specified in the cpuEngine hierarchy and
apply the MARK_DEBUG property by right-clicking and selecting Mark Debug from the
dialog.
cpuEngine/dcqmem_dat_qmem[*],
cpuEngine/dcpu_dat_qmem[*],
cpuEngine/dcqmem_adr_qmem[*],
cpuEngine/du_dsr[*],
cpuEngine/dvr0__0[*],
cpuEngine/du_dsr[*],
cpuEngine/dcqmem_sel_qmem[*]

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

Alternatively, you can use the following Tcl command to set the MARK_DEBUG property on
the signals specified.
set_property mark_debug true [get_nets [list {cpuEngine/
dcqmem_dat_qmem[*]}
{cpuEngine/dcpu_dat_qmem[*]} {cpuEngine/dcqmem_adr_qmem[*]}
{cpuEngine/du_dsr[*]} {cpuEngine/dvr0__0[*]} {cpuEngine/du_dsr[*]}
{cpuEngine/dcqmem_sel_qmem[*]}]]

9. In the Flow Navigator, click Set Up Debug to invoke the Set Up Debug wizard.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

10. When the Set Up Debug Wizard appears, click Next.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

11. When the ILA Core Options screen appears, click Next again.
12. When the Set Up Debug Summary screen appears, ensure that one debug core is created and
click Finish.
13. Check the Debug window to ensure the u_ila_0 core is inserted into the design.

14. Save the new debug XDC commands by selecting File → Constraints → Save or clicking the
Save Constraints button.

Step 2: Compiling the Reference Design

The following are the steps to run implementation on the reference design.

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1. From the Flow Navigator, select Run Implementation.

2. After implementation finishes, the Implementation Complete dialog box opens. Click Cancel.
3. In a project-based design. The Vivado Design Suite saves intermediate implementation
results as design checkpoints in the implementation run directory. You use one of the saved
design checkpoints from the implementation in the incremental compile flow.

TIP: When you re-run the implementation, the previous results are deleted. Save the intermediate
implementation results to a new directory or create a new implementation run for your incremental
compile to preserve the reference implementation run directory.

4. In the Design Runs window, right-click impl_1 and select Open Run Directory from the
popup menu. This opens the run directory in a file browser, as seen in the following figure.
The run directory contains the routed checkpoint (top_routed.dcp) to be used later for
the incremental compile flow. The location of the implementation run directory is a property
of the run.
5. Get the location of the current run directory in the Tcl Console by typing:
get_property DIRECTORY [current_run]

This returns the path to the current run directory that contains the design checkpoint. You
can use this Tcl command and the DIRECTORY property to locate the DCP files needed for
the incremental compile flow.

Step 3: Create New Runs

In this step, you define new synthesis and implementation runs to preserve the results of the
current runs. You make debug-related changes to the design and rerun synthesis and
implementation. If you do not create new runs, Vivado overwrites the current results.

1. From the Vivado toolbar, select Flow → Create Runs to invoke the Create New Runs wizard.
2. In the Create New Runs screen, click Next.
3. The Configure Implementation Runs screen opens, as shown in the following figure. Select
the Make Active check box, and click Next.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

4. From the Launch Options window, select Do not launch now and click Next.

5. In the Create New Runs Summary screen, click Finish to create the new runs.
The Design Runs window displays the new active runs in bold.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

Step 4: Making Incremental Debug Changes

In this step, to add/delete/edit debug cores, you need to reopen the synthesized netlist. Make
debug-related changes to the design using the Set Up Debug wizard.

1. If you have closed the synthesized netlist, go back to the synthesized design using the Flow
Navigator.
2. For this tutorial, assume that you now need to debug some other nets beside the ones
already being debugged. However, you want to reuse the previous place and route results.
Now, you debug the nets fftEngine/fifo_out[*].
3. Apply the MARK_DEBUG property to this bus in the netlist window.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

4. Click Set Up Debug to invoke the Set Up Debug wizard in the Flow Navigator.
5. In the Existing Debug Nets tab, select Continue debugging 110 nets connected to the
existing debug core.

6. Click Next to debug the new unassigned debug nets.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

7. Click Next and ensure the new nets are in the list of Nets to Debug.

8. Click Next and ensure that two debug cores are created, and click Finish.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

9. Save the new debug XDC commands by clicking the Save Constraints button or selecting
File → Constraints → Save from the main Vivado toolbar.

Step 5: Running Incremental Compile

In the previous steps, you have updated the design with debug changes. You could run
implementation on the new netlist, to place and route the design and work to meet the timing
requirements. However, with only minor changes between this iteration and the last, the
incremental compile flow lets you reuse the bulk of your prior debug, placement and routing
efforts. This can reduce the time it takes to meet timing on design iterations. For more
information, refer to Vivado Design Suite User Guide: Implementation (UG904).

1. Start by defining the design checkpoint (DCP) file to use as the reference design for the
incremental compile flow. This is the design from which the Vivado Design Suite draws
placement and routing data.
2. In the Design Runs window, right-click the impl_2 run and select Set Incremental
Implementation from the popup menu. The Set Incremental Implemenation dialog box opens.
3. Select Automatically use the checkpoint from the previous run.
4. Click OK. This information is stored in the INCREMENTAL_CHECKPOINT property of the
selected run. Setting this property tells the Vivado Design Suite to run the incremental
compile flow during implementation.
5. You can check this property on the current run using the following Tcl command:
get_property INCREMENTAL_CHECKPOINT [current_run]

This returns the full path to the top_routed.dcp checkpoint.

TIP: To disable Incremental Compile for the current run, clear the INCREMENTAL_CHECKPOINT
property. This can be done using the Set Incremental Compile dialog box, or by editing the property
directly through the Properties window of the design run, or through the reset_property
command.

6. From the Flow Navigator, select Run Implementation.

This runs implementation on the current run, using the top_routed.dcp file as the
reference design for the incremental compile flow. When the run is finished, the
Implementation Completed dialog box opens.
7. Select Open Implemented Design and click OK. As shown in the following figure, the Design
Runs window shows the elapsed time for implementation run impl_2 versus impl_1.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

Note: This is an extremely small design. The advantages of the incremental compile flow are greater
and significant with larger, more complex designs.

8. Select the Reports tab in the Results window area and under Place Design, double-click
Incremental Reuse Report as shown in the following figure.

The Incremental Reuse Report opens in the Vivado IDE text editor. This report shows the
percentage of reused Cells, Ports, and Nets. A higher percentage indicates more effective
reuse of placement and routing from the incremental checkpoint.

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 Lab 7: Debugging Designs Using the Incremental Compile Flow

In the report, fully reused nets indicate that the entire routing of the nets is reused from the
reference design. Partially reused nets indicate that some of the routing of the nets reuses
routing from the reference design. Some segments re-route due to changed cells, changed
cell placements, or both. Non-reused nets indicate that the net in the current design is not
matched in the reference design.

Conclusion
This concludes the lab. You can close the current project and exit the Vivado IDE.

In this lab, you learned how to run the Incremental Compile Debug flow, using a checkpoint from
a previously implemented design. You inserted a new debug core using the Set Up Debug wizard
on the synthesized netlist. You examined the similarity between a reference design checkpoint
and the current design by examining the Incremental Reuse Report.

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 Lab 8: Using the Vivado Serial Analyzer to Debug Serial Links

Lab 8

Using the Vivado Serial Analyzer to

Debug Serial Links
The Serial I/O analyzer is used to interact with IBERT debug IP cores contained in a design. It is
used to debug and verify issues in high speed serial I/O links.

The Serial I/O Analyzer has several benefits:

• Tight integration with AMD Vivado™ IDE.

• Ability to script during netlist customization/generation and serial hardware debug.
• Common interface with the Vivado Integrated Logic Analyzer (ILA).

The customizable AMD LogiCORE™ IP Integrated Bit Error Ratio Tester (IBERT) core for 7 series
FPGA GTX transceivers is designed for evaluating and monitoring the GTX transceivers. This core
includes pattern generators and checkers that are implemented in FPGA logic, and provides
access to ports and the dynamic reconfiguration port attributes of the GTX transceivers.
Communication logic is also included to allow the design to be run time accessible through JTAG.

In the course of this tutorial, you:

• Create, customize, and generate an Integrated Bit Error Ratio Tester (IBERT) core design using
the Vivado tool.
• Interact with the design using Serial I/O Analyzer. This includes connecting to the target
KC705 board, configuring the device, and interacting with the IBERT/Transceiver IP cores.
• Perform a sweep test to optimize your transceiver channel and to plot data using the IBERT
sweep plot GUI feature.

Design Description
You can customize the IBERT core and use it to evaluate and monitor the functionality of
transceivers for a variety of AMD devices. The focus of this tutorial is on AMD Kintex™ 7 GTX
transceivers. Accordingly, the KC705 target board is used for this tutorial.

The following figure shows a block diagram of the interface between the IBERT Kintex 7 GTX
core interfaces with Kintex 7 transceivers.

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 Lab 8: Using the Vivado Serial Analyzer to Debug Serial Links

• DRP Interface and GTX Port Registers: IBERT provides you with the flexibility to change GTX
transceiver ports and attributes. Dynamic reconfiguration port (DRP) logic is included, which
allows the runtime software to monitor and change any attribute in any of the GTX
transceivers included in the IBERT core. When applicable, readable, and writable registers are
also included. These are connected to the ports of the GTX transceiver. All are accessible at
runtime using the Vivado logic analyzer.

• Pattern Generator: Each GTX transceiver enabled in the IBERT design has a pattern generator
and a pattern checker. The pattern generator sends data out through the transmitter.

• Error Detector: Each GTX transceiver enabled in the IBERT design has a pattern generator and
a pattern checker. The pattern checker takes the data through the receiver and checks it
against an internally generated pattern.

Figure 4: IBERT Design Flow

DRP
DRP
Interface

TxN/TxP
External Serial
JTAG Pattern
Tx Data Loopback via
BSCAN Generator
SMA Cables
Kintex 7 GTX
Transceiver
Error
Rx Data
Detector

TxN/RxP
GTX Port
Detector Ports

X27386-111522

Step 1: Creating, Customizing, and Generating

an IBERT Design
To create a project, use the New Project wizard to name the project, to add RTL source files and
constraints, and to specify the target device.

1. Invoke the Vivado IDE.

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2. In the Quick Start screen, click Create Project to start the New Project wizard, and click Next.
3. In the Project Name page, name the new project ibert_tutorial and provide the project
location (C:/ibert_tutorial). Ensure that Create Project Subdirectory is selected. Click
Next.
4. In the Project Type page, specify the Type of Project to create as RTL Project. Click Next.
5. In the Add Sources page, click Next.
6. In the Add Existing IP page, click Next.
7. In the Add Constraints page, click Next.
8. In the Default Part page, select Boards and select Kintex 7 KC705 Evaluation Platform. Click
Next.
9. Review the New Project Summary page. Verify that the data appears as expected, per the
previous steps. Click Finish.
Note: It might take a moment for the project to initialize.

Step 2: Adding an IBERT Core to the Vivado

Project
1. In the Flow Navigator, click IP Catalog.
The IP catalog opens.

2. In the search field of the IP catalog type IBERT, to display the IBERT 7 series GTX IP.

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3. Double-click IBERT 7 series GTX IP. This brings up the customization GUI for the IBERT.
4. In the Customize IP dialog box, choose the following options in the Protocol Definition tab:
a. Type the name of the component in the Component Name field. In this case, leave the
name as the default name, ibert_7series_gtx_0.
b. Ensure that the Silicon Version is selected as General ES/Production.
c. Ensure that the Number of Protocols option is set to 1.
d. Change the LineRate (Gb/s) to 8.
e. Change DataWidth to 40.
f. Change Refclk (MHz) to 125.
g. Ensure that the Quad Count is set to 2.
h. Ensure Quad PLL box is selected.

5. Under the Protocol Selection tab, update the following selections:

a. For GTX Location QUAD_117, in the Protocol Selected column, click the pull-down menu
and select Custom 1 / 8 Gbps. This should automatically populate Refclk Selection to
MGTREFCLK0 117 and TXUSRCLK Source to Channel 0.

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b. For GTX Location QUAD_118, do the following:

i. In the Protocol Selected column, click the pull-down menu and select Custom 1 / 8
Gbps.
ii. In the Refclk Selection column, change the value to MGTREFCLK0 117.
iii. In the TXUSRCLK Source column, change the value to Channel 0.

6. Click the Clock Settings tab and make the following changes for both QUAD_117 and
QUAD_118:
a. Leave the Source column at its default value of External.
b. Change the I/O Standard column to DIFF SSTL15.
c. Change the P Package Pin to AD12.
d. Change the N Package Pin to AD11.
e. Leave the Frequency (MHz) at its default value of 200.00.

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7. Click the Summary tab and ensure that the content matches the following figure, click OK.

8. When the Generate Output Products dialog box opens, click Generate.

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9. In the Sources window, right-click the IP, and select Open IP Example Design.

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10. In the Open IP Example Design dialog box, and specify the location of your project directory.
Ensure that the Overwrite existing example project is selected and click OK.
Note: This opens a new instance of Vivado IDE with the new example design opened.

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Step 3: Synthesize, Implement, and Generate

Bitstream for the IBERT Design
1. In the newly opened instance of Vivado IDE, click Generate Bitstream in the Flow Navigator.
When the No Implementation Results Available dialog box appears. Click Yes.

When the bitstream generation is complete, the Bitstream Generation Completed dialog box
opens.
2. Select Open Hardware Manager, and click OK.

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3. The Hardware Manager window appears as shown in the following figure.

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Step 4: Interact with the IBERT Core Using

Serial I/O Analyzer
In this tutorial step, you connect to the KC705 target board, program the bitstream created in the
previous step, and use the Serial I/O Analyzer to interact with the IBERT design created in Step
1. You perform some analysis using various input patterns and loopback modes while observing
the bit error count.

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1. Click Open New Target. When the Open Hardware Target wizard opens, click Next.

2. In the Connect to the field, choose Local server. Click Next.

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3. In the Select Hardware Target page, click Next.

There is only one target board, in this case, to connect to, so the default is selected.

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4. In the Open Hardware Target Summary page, review the options that you selected. Click
Finish.

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5. The Hardware window in Vivado IDE should show the status of the target FPGA on the
KC705 board.

6. Select XC7K325T_0(0) in the Hardware window, right-click, and select Program Device.

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7. The Program Device dialog box opens. Make sure that the correct .bit file is selected, and
click Program.

8. The Hardware window now shows the IBERT IP that you customized and implemented from
the previous steps. It contains two QUADS, each of which has four GTX transceivers. These
components of the IBERT are detected while scanning the device after downloading the
bitstream. If you do not see the QUADS select the XC7K325 device, right-click and select
Refresh Device.

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9. Next, create links for all eight transceivers. Vivado Serial I/O analyzer is a link-based analyzer
that allows you to link between transmitter and receiver GTs within the IBERT design. For this
tutorial, link the TX and RX of the same channel. To create a link, right-click the IBERT Core in
the Hardware window and click Create Links.

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The Create Links dialog box opens.

10. Ensure the first transceiver pairs (MGT_X0Y8/TX and MGT_X0Y8/RX) are selected.

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11. Click the “+” button to add a new link. In the Link group description field, type Link Group
SMA. Select the Internal Loopback check box.

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For the first link group, call this Link Group SMA, as this is the only transceiver channel linked
through the SMA cables. The new link shows up in the Links window.

12. Click Create Link again to create link groups for the rest of the transceiver pairs. To do this,
ensure that the transceiver pairs are selected, and click the + sign icon (add new link)
repeatedly until all the links are added to the link group Internal Loopback. Click OK.

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13. After creating the links, they are added to the Links window as shown.

The status of the links indicates an 8.0 Gbps line rate.

For more information about the different columns of the Links windows, see the Vivado
Design Suite User Guide: Programming and Debugging (UG908).
14. Change the GT properties of the rest of the transceivers as described previously.
15. Next, create a 2D scan. Click Create Scan in the Links window.

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The Create Scan dialog box opens. In this dialog box, you can change the various scan
properties. In this case, leave everything to its default value and click OK. For more
information on the scan properties, see Vivado Design Suite User Guide: Programming and
Debugging (UG908).

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The Scan Plot window opens, as shown in the following figure.

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The 2D Scan Plot is a heat map of the BER value.

You can also perform a Sweep test on the links you created earlier.
16. In the Links window, highlight Link 0 under the Link called Link Group SMA, right-click, and
select Create Sweep.

17. The Create Sweep dialog box opens as follows. Various properties for the Sweep test can be
changed in this dialog box. Leave all the values to its default state and click OK.

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Because there are four different Sweep Properties, each of these properties has three
different values (as seen in the Values to Sweep column), a total number of 81 sweep tests
are carried out. The Scans window shows the results of all the scans that are done for the
selected link.

CAUTION! Because there are 81 scans to be done, it could be a few minutes before all the scans are
complete.

To see the results of any scans performed, highlight the scan, right-click, and select Display
Scan Plots.

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The Scan Plots window opens, showing the details of the scan performed.

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Lab 9

Using the Vivado ILA Core to Debug

JTAG-AXI Transactions
This lab illustrates how to insert an ILA core into the JTAG to AXI Master IP core example design,
using the ILA's advanced trigger and capture capabilities.

What is the JTAG to AXI Master IP core?

The AMD LogiCORE™ IP JTAG-AXI core is a customizable core that can generate AXI
transactions and drive AXI signals internal to the FPGA at run-time. This supports all memory-
mapped AXI interfaces (except AXI4-Stream) and Lite protocol and can be selected using a
parameter. The width of the AXI data bus is customizable. This IP can drive any AXI4-Lite or
Memory-Mapped Slave directly. It can also be connected as master to the interconnect. Run-time
interaction with this core requires the use of the AMD Vivado™ logic analyzer feature.

Key Features

• AXI4 master interface

• Option to select AXI4 and AXI4-Lite interfaces
• User controllable AXI read and write enable
• User Selectable AXI data width: 32 and 64
• Vivado Integrated Logic Analyzer Tcl Console interface to interact with hardware

Additional Documentation

JTAG to AXI Master LogiCORE IP Product Guide (PG174) contains additional information

Design Description
This section has three steps as follows:

1. Creating a simple design in IP integrator that includes a System ILA and JTAG-to-AXI master.
2. Programming the AMD Kintex™ 7 FPGA KC705 Evaluation Kit Base Board and interacting
with the JTAG to AXI Master IP core.

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3. Using the ILA Advanced Trigger Feature to Trigger on an AXI Read Transaction.

Step 1: Creating a New Vivado Project and

Generating the IP Integrator Design with
JTAG-to-AXI and System ILA
To create a project, use the New Project wizard to name the project, add RTL source files and
constraints, and specify the target device.

1. Invoke the Vivado IDE.

2. In the Quick Start tab, click Create Project to start the New Project wizard. Click Next.
3. In the Project Name page, name the new project jtag_2_axi_tutorial and provide the
project location (C:/jtag_2_axi_tutorial). Ensure that Create Project Subdirectory is
selected. Click Next.
4. In the Project Type page, specify the Type of Project to create as RTL Project. Ensure that Do
not specify sources at this time is checked. Click Next.
5. In the Default Part page, choose Boards and the Kintex 7 KC705 Evaluation Platform. Click
Next.

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6. In the New Project Summary page, click Finish.

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7. In the leftmost panel of the Flow Navigator, under Project Manager, click Create Block
Diagram. A dialog box appears that allows you to specify a block diagram name. You can
choose to specify a custom name or take the default. Click OK.

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8. In the far right of the window is an empty block diagram design window labeled Diagram.
Click the + sign in the middle of the pane or the + toolbar button to bring up a search
window. In the Search field, type “JTAG to AXI” and double-click it to add the JTAG to AXI
Master to the block diagram.

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9. The JTAG to AXI Master core appears on the IP integrator canvas. Double-click the core to
view the Customization dialog. Review the available settings and click OK to accept the
default core settings.

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10. Following the same process from the previous step, add the additional IP to the block
diagram: AXI BRAM controller and Block Memory Generator. This creates a design using a
simple AXI infrastructure to create AXI transactions that demonstrate the debugging
capabilities of the System ILA core.
11. Before continuing. You need to customize AXI BRAM Controller and Block Memory
Generator. Begin by locating the AXI BRAM Controller in the block diagram canvas and
double-clicking on it. This invokes the Customization Dialog for the IP. Locate the Number of
BRAM interfaces and set the value to 1. Click OK.

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12. Next, locate the Block Memory Generator in the block diagram and double-click as in the
previous step to invoke the Customization dialog. Clear Enable Safety Circuit check box. Click
OK.

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13. At this point, the design should look like the following figure.

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14. Notice the green banner indicating that Designer Assistance is available at the top of the
block diagram canvas. Click the Run Connection Automation button on this banner. When
the Connection Automation window appears, click the radio button for All Automation, and
click OK.

15. The Clocking Wizard and Processor System Reset and an AXI SmartConnect, are auto-
inserted into the design.
Note: The Clocking Wizard clock and reset inputs are disconnected, and the Run Connection
Automation banner persists. These inputs are connected to physical input ports on the FPGA and
wired to buttons on the KC705 board through the customization of the Clocking Wizard.

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16. Invoke the Customization Dialog for the Clocking Wizard by double-clicking the IP in the
block diagram canvas. When the dialog appears, set CLKIN_1 to sys_diff_clk and
EXT_RESET¬_IN to reset. Click OK.
Note: Adding constraints for these ports is unnecessary because the project is generated using an
evaluation board as the target, and the IP allows the constraint information to be selected with the
sys_diff_clk.

17. Locate the green banner indicating that Designer Assistance is Available and click Run
Connection Automation. When the Run Connection Automation dialog appears, select the
button for All Automation. Click OK.
18. Now, sys_diff_clk and reset are connected to external ports. Examine the connectivity of
the design and it might be necessary to monitor AXI transactions between the JTAG to AXI
master and the AXI BRAM Controller slave. This is possible if a System ILA is added to probe
the AXI bus between the AXI BRAM Controller and the JTAG to the AXI master.

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19. To add a System ILA to the design, click the Add IP (+) button as in the previous steps. Search
for System ILA and double-click to add it to the block diagram. When it appears in the block
diagram canvas, double-click on it to invoke the Customization Dialog. Ensure that both
Capture Control and Advanced Trigger are selected. Also, set the Number of Comparators to
the value 3. Click OK.

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20. Connect the System ILA SLOT_0_AXI port and the S_AXI port on the AXI BRAM Controller.
Do this by clicking on the SLOT_0_AXI port and clicking again on the S_AXI port on the AXI
BRAM Controller.

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21. When the Run Connection Automation banner appears, click it and select All Automation.
Click OK.
Note: The clk and resetn ports on the System ILA are connected to the AXI clock and the AXI reset.

22. In the upper left side of the Vivado IDE, click File → Save Block Design. Select File → Close
Block Design in the same menu to close the block design.
23. In the sources window, right-click on design_1 block design and select Create HDL Wrapper.
Allow Vivado IDE to manage the wrapper, and click OK.
24. In the Flow Navigator on the left side of the Vivado IDE, click Generate Bitstream.
25. Click OK to implement the design.
26. Wait until the Vivado Status window shows write_bitstream complete.
27. In the Bitstream Generation Completed dialog, select Open Hardware Manager, and click
OK.

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Step 2: Program the KC705 Board and Interact

with the JTAG to AXI Master Core
1. Connect your KC705 board's USB-JTAG interface to a machine with AMD Vivado™ IDE and
cable drivers installed and power up the board.
2. The Hardware Manager window opens. Click Open New Target. The Open New Hardware
Target dialog opens.

3. In the Connect to field, choose Local server, and click Next.

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Note: Depending on your connection speed, this can take about 10 to 15 seconds.

4. If more than one target is connected to the hardware server, you see multiple entries on the
Select Hardware Target page. In this tutorial, only one target is shown in the following figure.
Leave these settings at their default values, and click Next.

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5. Leave these settings at their default values as shown. Click Next.

6. In the Open Hardware Target Summary page, click Finish, as shown in the following figure.

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Wait for the connection to the hardware to complete. After the hardware target is connected,
the Hardware dialog shown in the following figure opens.
Note: The Hardware tab in the Debug view shows the hardware target and XC7K325T device detected
in the JTAG chain.

7. Next, program the previously created XC7K325T device using the .bit bitstream file by
right-clicking the XC7K325T device, and selecting Program Device as shown in the following
figure.
8. In the Program Device dialog, verify that the .bit file is correct for the lab on which you are
working. Click Program to program the device.

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Note: Wait for the program device operation to complete. This can take a few minutes.

9. Verify that the JTAG to AXI Master and ILA cores are detected by locating the hw_axi_1 and
hw_ila_1 instances in the Hardware Manager window.

10. You can communicate with the JTAG to AXI Master core via Tcl commands only. You can
issue AXI read and write transactions using the run_hw_axi command. However, before
issuing these transactions, it is important to reset the JTAG to the AXI Master core. Because
the aresetn input port of the jtag_axi_0 core instance is not connected to anything, you need
to use the following Tcl commands to reset the core:
reset_hw_axi [get_hw_axis hw_axi_1]

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11. The next step is to create a 4-word AXI burst transaction to write to the first four locations of
the BRAM:
set wt [create_hw_axi_txn write_txn [get_hw_axis hw_axi_1] -type WRITE -
address C0000000 -len 128 -data {44444444_33333333_22222222_11111111}]

where:
• write_txn is the name of the transaction.
• [get_hw_axis hw_axi_1] returns the hw_axi_1 object.
• -address C0000000 is the start address.
• -len 128 sets the AXI burst length to 128 words
• -data {44444444_33333333_22222222_11111111} is the data to be written.
Note: The data direction is MSB to the left (that is, address 3) and LSB to the right (that is, address 0).
The data is repeated from the LSB to the MSB to fill the entire burst.

12. The next step is to set up a 128-word AXI burst transaction to read the contents of the first
four locations of the AXI-BRAM core:
set rt [create_hw_axi_txn read_txn [get_hw_axis hw_axi_1] -type READ -
address C0000000 -len 128]

where:
• read_txn is the name of the transaction.
• [get_hw_axis hw_axi_1] returns the hw_axi_1 object.
• -address C0000000 is the start address.
• -len 128 sets the AXI burst length to 4 words.
13. After creating the transaction, you can run it as a write transaction using the run_hw_axi
command:
run_hw_axi $wt

This command should return the following:

INFO: [Labtools 27-147] : WRITE DATA is :
44444444333333332222222211111111…

14. After creating the transaction, you can run it as a read transaction using the run_hw_axi
command:
run_hw_axi $rt

This command should return the following:

INFO: [Labtools 27-147] : READ DATA is :
44444444333333332222222211111111…

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Step 3: Using ILA Advanced Trigger Feature to

Trigger on an AXI Read Transaction
1. In the ILA – hw_ila_1 dashboard, locate the Trigger Mode Settings area and set Trigger mode
to ADVANCED_ONLY.
2. In the Capture Mode Settings area, set the Trigger position to 512.
3. In the Trigger State Machine area, click the Create new trigger state machine link.

4. In the New Trigger State Machine File dialog box, set the name of the state machine script to
txns.tsm.

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5. A basic template of the trigger state machine script is displayed in the Trigger State Machine
gadget. Expand the trigger state machine gadget in the ILA dashboard. Copy the following
script after line 17 of the state machine script and save the file.
# The "wait_for_arvalid" state is used to detect the start
# of the read address phase of the AXI transaction which
# is indicated by the axi_arvalid signal equal to '1'
#
state wait_for_arvalid:
if (design_1_i/system_ila_0/U0/net_slot_0_axi_arvalid == 1'b1) then
goto wait_for_rready;
else
goto wait_for_arvalid;
endif
#
# The "wait_for_rready" state is used to detect the start
# of the read data phase of the AXI transaction which
# is indicated by the axi_rready signal equal to '1'
#
state wait_for_rready:
if (design_1_i/system_ila_0/U0/net_slot_0_axi_rready == 1'b1) then
goto wait_for_rlast;
else
goto wait_for_rready;
endif

#
# The "wait_for_rlast" state is used to detect the end
# of the read data phase of the AXI transaction which
# is indicated by the axi_rlast signal equal to '1'.
# Once the end of the data phase is detected, the ILA core
# will trigger.
#
state wait_for_rlast:
if (design_1_i/system_ila_0/U0/net_slot_0_axi_rlast == 1'b1) then
trigger;
else
goto wait_for_rlast;
endif

Note: Use the state machine to detect the various phases of an AXI read transaction:

• Beginning of the read address phase

• Beginning of the read data phase
• End of the read data phase
6. Arm the trigger of the ILA by right-clicking the hw_ila_1 core in the Hardware Manager
window and selecting Run Trigger.

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 Lab 9: Using the Vivado ILA Core to Debug JTAG-AXI Transactions

7. In the Trigger Capture Status window, the ILA core waits for the trigger to occur and that the
trigger state machine is in the wait_for_a_valid state.
Note: The pre-trigger capture of 512 samples are completed successfully.

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8. In the Tcl Console, run the read transaction you set up in the previous section of this tutorial.
run_hw_axi $rt

Note: The ILA core has triggered, and the trigger mark is on the sample where the axi_rlast signal is
equal to '1', as the trigger state machine program intended.

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

Lab 10

Using the Vivado Serial Analyzer to

Debug PS-GTR Serial Links
IBERT AMD UltraScale+™ PS-GTR (IBERT PS-GTR) transceiver can evaluate and monitor PS-GTR
transceivers in AMD Zynq™ UltraScale+™ MPSoC devices. With this feature, you can accomplish
these tasks:

• Perform eye scans with user data

• Change PS-GTR settings
• View link status
• Check the “lock” status of all phase-locked loops (PLLs) used by all PS-GTR lanes

IBERT PS-GTR transceiver does not provide these capabilities:

• Perform eye scans with raw pseudo-random binary sequence (PRBS) data patterns
• Measure Bit Error Ratio (no bit or error counters)

This solution is purely software-based, meaning that no IP or logic is required in the

programmable logic (PL) of the device. This documentation guides you through the setup of the
PS-GTR Transceivers by creating a first-stage boot loader (FSBL). It demonstrates how to load the
FSBL into the Zynq UltraScale+ MPSoC and use IBERT PS-GTR.

TIP: This is a supported feature in AMD Vivado™ Design Suite 2017.2 and above.

IBERT PS-GTR Flow

The IBERT PS-GTR Bring-up and subsequent EyeScan involve three different components:

1. Generating Zynq UltraScale+ MPSoC PS Xilinx Support Archive (XSA) file from the Vivado
tool after configuring the PS-GTR.
2. Using the AMD Vitis™ AMD Software Command-line Tool (XSCT) flow to generate an FSBL
file using the XSA file.
3. Using the FSBL file with Vivado Serial I/O Analyzer to bring up IBERT PS-GTR.

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

Tools Required

• Vivado
• Vitis
• XSCT (Part of the Vitis tool)

Board/Part/Components Required

• ZCU102 Rev 1.0 board

• XCZU9EG-FFVB1156 production device
• PCIe®
○ A PCIe card that has at least x4 lanes

○ PCI Express 4x Male to PCIe 16x Female Riser Cable if PCIe card is larger than x4

• SATA
○ SanDisk 128 GB SATA SSD Drive

○ SATA connector cable

○ 4 Pin Molex to SATA Power Cable Adapter

• USB
○ SanDisk Ultra 32 GB USB 3.0 Flash Drive

○ USB 3.0 Type A Female to Micro Male Adapter

Required Files

• FSBL executable and linkable format file (ELF File) (Created using the following instructions),
which configures the PS-GTR
• Configuration Bitstream File (Optional file that can be needed to custom configure the FPGA
depending on the board setup)
• Tcl script to generate the FSBL and modify C-source for USB Support (when available)

Assumptions

1. FSBL should always target Cortex®-A53 processor as R5 (psu_cortexr5_0) is exclusively used

by IBERT PS-GTR.
2. Physical devices such as SATA drive, PCIe card, etc. are needed for validation.
3. This tutorial targets the ZCU102, if targeting a different evaluation kit or a custom board
some configurations will be different to accommodate hardware differences.

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

Step 1: Generating a Zynq UltraScale+ MPSoC

PS Xilinx Support Archive
1. Open the Vivado IDE.
2. Click Create Project, and click Next.

3. Set your project name, and specify the project directory. Click Next.
4. Select Project type as RTL project.
5. Select do not specify sources at this time checked, and click Next.
6. To choose the board, click the board icon, and select Zynq UltraScale+ ZCU102 Evaluation
board, with Board Rev 1.0. Click Next.

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7. The project summary displays. To create the project, click Finish.

8. In the Flow Navigator, select Create Block Design. You can specify the design name and
directory, but it is not necessary for a local project directory. Click OK to create the block
design.

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

9. An empty design diagram is displayed. Click the Add IP button to add IP. Select the IP based
on the selected board (for the ZCU102 evaluation board, search for Zynq UltraScale+
MPSoC) and double-click the selected IP.

10. In the design diagram window, select Run Block Automation. Click OK to continue creating
the ZCU102 design.

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11. When the design diagram appears, use the following steps to validate the design:
a. Connect maxihpm0_fpd_aclk and maxihpm1_fpd_aclk together to pl_clk0, as
shown in the following figure.
i. Select maxihpm0_fpd_aclk and drag it to maxihpm1_fpd_aclk.
ii. Select maxihpm1_fpd_aclk and drag it to pl_clk0.
b. Right-click the Zynq UltraScale+ MPSoC block and select Validate Design to validate the
design. It says validation is successful. Click OK.

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12. Customize the design by double-clicking the Zynq UltraScale+ MPSoC block and configuring
the parameters. There are four valid GT configurations for the ZCU102 board, as shown in
the following table.

Table 2: Supported PS-GTR Connector Functionality

ICM Settings PCIe USB SATA

SEL (S3,2,1,0) DP Connector
(Lane 0,1,2,3) Connector Connector Connector
0000 PCIe.0, PCIe.1, PCIe Gen2 x4 N.C. N.C. N.C.
PCIe.2, PCIe.3
1111 DP.1, DP.0, USB, N.C. DP.0, DP.1 USB0 SATA1
SATA
1100 PCIe.0, PCIe.1, PCIe Gen2 x2 N.C. USB0 SATA1
USB, SATA
1110 PCIe.0, DP.0, USB, PCIe Gen2 x1 DP.0 USB0 SATA1
SATA

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13. Select the settings based on your requirements by double-clicking the Zynq UltraScale+
MPSoC block to customize GT Lane configuration.
14. Select I/O Configuration → High Speed. Select one of the four combinations using the
settings in the following screenshots.
a. PCIe – Display Port - USB - SATA (Default Vivado preset)

b. PCIe–PCIe - USB - SATA

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c. Display Port – Display Port - USB - SATA

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d. PCIe–PCIe - PCIe - PCIe (PCIe x4)

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

15. Click OK when finished customizing the GT Lane configuration.

16. Do not click Run Block Automation again, even though the banner reappears. If used, the
customized values are reset.
17. Click the Sources tab on the top left of the Block Design window.
a. Under the Block Designs group, click IP Sources.
b. Right-click design_1 and click Create HDL Wrapper.

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18. Leave the option Let Vivado manage wrapper and auto-update selected. Click OK in the
dialog to create the HDL wrapper.
19. Right-click design_1_i in the IP Sources tab, and click Generate Output Products.
20. Click Generate to generate with the default options in the panel.
21. After the generation is complete, click OK.
22. Select File → Export → Export Hardware.

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23. In the Export Hardware Platform wizard, select a Fixed platform type. Click Next.
24. On the next page, select Pre-Synthesis for the platform output type.
25. Leave the XSA name as design_1_wrapper, and choose a location to store the exported XSA,
preferably in a new directory.

Step 2: Using AMD Software Command-line

Tool Flow to Generate a First Stage Boot
Loader
XSCT is an interactive and scriptable command-line interface to the Vitis tool. The XSCT flow
requires running a Tcl script.

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Generating Using the AMD Software Command-line Tool Automated Flow

To create an FSBL for the Cortex-A53 #0 (64-bit) automatically (and modify the
xfsbl_main.c/h files if a USB is present) using the provided script, use the following steps:

1. Copy the src/lab10/xsct_create_fsbl.tcl script to the directory where the XSA file
is located. You can modify the Tcl script if you change the default name of the XSA file in the
Vivado tool. You can also change the script if the compiler options are different.
2. Open a terminal on Linux or command prompt on Windows.
3. Change the directory into the directory where the XSA file is located.
4. Call xsct from the Vitis tool install area.
% xsct xsct_create_fsbl.tcl

5. The location of the generated ELF File prints out when the script completes.

Step 3: ZCU102 Board Settings

USB Jumper Setting Requirements for HOST Mode on ZCU102

1. Make sure the following jumpers are correctly set for USB to be in HOST mode (refer to
ZCU102 Evaluation Board User Guide (UG1182)).
a. J7 – ON
b. J113 – 1-2
c. J110 – 2-3
2. Refer to the following image for jumper settings on a ZCU102 Rev 1.0 board.

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

Using FSBL with Serial I/O Analyzer to Bring

Up IBERT PS-GTR
1. Connect all the physical devices such as SATA Drive, PCIe® card, and USB device based on
your selection from the four valid GT configurations for ZCU102 prior to loading the FSBL.
Hot swap or hot plug is not supported.
2. Open Vivado.
3. Open hardware manager and connect to a board with a Zynq UltraScale+ device. The
following example shows connecting to a board on a remote machine, so hw_server needs to
be running on the remote machine before it can connect.

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4. Verify the ARM_DAP is visible in the hardware device list and click Next, and click Finish.

5. Right-click the ARM_DAP device in the hardware tree and select Configure IBERT GTR.

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6. When the dialog box opens, you must provide the FSBL ELF file created in the previous steps
and optionally a configuration file (a bitstream, if your design requires one). You can also reset
the system before configuring with the Reset Zynq option checked. Click OK when done.
Note: The Reset Zynq option leaves the ARM_DAP in a bad state on early versions of Zynq UltraScale+
devices (for example, ZU9EG es1). If that occurs, power cycle the board and keep the Reset Zynq
option unchecked.

7. config_hw_sio_gts is executed with the selected settings. refresh_hw_device is

called to rescan the device for new debug cores. The IBERT should be configured as shown in
the following example.

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8. The Auto-detect links option does not work for PS-GTR. You can manually create links by
using Create Links as shown in the following figure.

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

9. Create links for all four lanes with each lane’s TX connected to the same lane’s RX, as shown
in the following figure.
Click OK when done.

10. The following figure shows the Serial I/O Links view where Status shows all the four lanes as
linked.

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

Note: The Link 1 PLL Status shows Not Locked, because it uses the Link 0 PLL as required by PCIe
protocol.

11. Right-click on any link and select Create Scan.

12. Select the appropriate parameters for EyeScan and perform the EyeScan. For example, the
following figure is performing EyeScan on Lane L1 (Link 1). Once the EyeScan completes, the
eye from -1UI to +1UI is displayed.
Note: Although the Create Scan pop up shows -0.5UI to +0.5UI, the EyeScan displayed is from -1UI to
+1UI.

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13. The following figure is a sample EyeScan performed on Lane L1.

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

Note: The value reported by Open UI % is a percentage of the entire horizontal axis, which is 2UI wide
for the PS-GTR transceiver.

Troubleshooting
Known Issues
1. By default, FSBL does not enumerate USB as that is something Linux drivers would do. To put
USB in link state without Linux, a small modification is required in the FSBL C-code. This
modification still does not enumerate the device, it only brings the USB into link state.
2. The EyeScan does not have a built-in time-out mechanism. If your link is poor (for example, if
L*_TM_DIG_8.EYESURF_ENABLE != 1), the EyeScan hangs without providing a user. No
results are returned in this case.
3. If the EyeScan progress is not moving, ensure the following parameters for all lanes are set for
EyeScan to function correctly.
Note: * represents the lane number (as in, for Lane 0, the parameter would be L0).

Click on the lane in the hardware tree and click on the properties tab. There is a search
button you can use to find the following properties.
a. L*_TM_MISC3.CDR_EN_FPL = 0
b. L*_TM_MISC3.CDR_EN_FFL = 0
c. L*_TM_DIG_8.EYESURF_ENABLE = 1
Also check the values of the following parameters, which ensures the Eye Scan circuit is
operational.
d. L*_PLL_LOCK = 1
e. L*_TM_SAMP_STATUS4.E_SAMP_PH0_CALIB_CODE is non-zero value
f. L*_TM_SAMP_STATUS5.E_SAMP_PH180_CALIB_CODE is non-zero value

Notes
1. As mentioned in Assumptions, IBERT PS-GTR uses the psu_cortexr5_0 core, so no other
applications should use this core.
2. TCM0 and TCM1 memory are combined to form a unified memory for IBERT PS-GTR. Any
other processor core should not access this memory while IBERT PS-GTR is running.

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 Lab 10: Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links

3. The error counter is 16-bits, and the sample counter is 32-bits. Each sample can have 8 bits
of error count. Therefore on the edges, the error counter can saturate with a sample count
value of 8192. PS-GTR does not stop the sample counter even if the error counter saturates.
A prescale=0 produces 8192 samples and thus total samples of 8192 *8 (65536), and thus
the outside edges of the eye could show a BER of e-01 or less depending on the prescale
selected.
4. The EyeScan assumes there is a link present. If there is no link, the EyeScan cannot complete.
Canceling the EyeScan stops the command sequence, but the state of the previous point scan
is unknown.
5. If you run EyeScan and because of no link, the EyeScan does not complete, set the register
L*_TM_MISC_ST_0.EYE_SURF_RUN to 0 for the given lane before you run the EyeScan again.
6. If you run EyeScan on a lane that is either powered down or Display Port, it immediately
stops, and the scan is marked as incomplete. EyeScan does not work in either scenario.

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 Appendix A: Additional Resources and Legal Notices

Appendix A

Additional Resources and Legal

Notices

Finding Additional Documentation

Technical Information Portal

The AMD Technical Information Portal is an online tool that provides robust search and
navigation for documentation using your web browser. To access the Technical Information
Portal, go to https://docs.amd.com.

Documentation Navigator

Documentation Navigator (DocNav) is an installed tool that provides access to AMD Adaptive
Computing documents, videos, and support resources, which you can filter and search to find
information. To open DocNav:

• From the AMD Vivado™ IDE, select Help → Documentation and Tutorials.
• On Windows, click the Start button and select Xilinx Design Tools → DocNav.
• At the Linux command prompt, enter docnav.

Note: For more information on DocNav, refer to the Documentation Navigator User Guide (UG968).

Design Hubs

AMD Design Hubs provide links to documentation organized by design tasks and other topics,
which you can use to learn key concepts and address frequently asked questions. To access the
Design Hubs:

• In DocNav, click the Design Hubs View tab.

• Go to the Design Hubs web page.

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 Appendix A: Additional Resources and Legal Notices

Support Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Support.

Revision History
The following table shows the revision history for this document.

Section Revision Summary

06/12/2024 Version 2024.1
Design Files Updated design files.
IBERT PS-GTR Flow Added a bullet point.

Please Read: Important Legal Notices

The information presented in this document is for informational purposes only and may contain
technical inaccuracies, omissions, and typographical errors. The information contained herein is
subject to change and may be rendered inaccurate for many reasons, including but not limited to
product and roadmap changes, component and motherboard version changes, new model and/or
product releases, product differences between differing manufacturers, software changes, BIOS
flashes, firmware upgrades, or the like. Any computer system has risks of security vulnerabilities
that cannot be completely prevented or mitigated. AMD assumes no obligation to update or
otherwise correct or revise this information. However, AMD reserves the right to revise this
information and to make changes from time to time to the content hereof without obligation of
AMD to notify any person of such revisions or changes. THIS INFORMATION IS PROVIDED "AS
IS." AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE
CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES,
ERRORS, OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY
DISCLAIMS ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, OR
FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY
PERSON FOR ANY RELIANCE, DIRECT, INDIRECT, SPECIAL, OR OTHER CONSEQUENTIAL
DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF
AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

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 Appendix A: Additional Resources and Legal Notices

AUTOMOTIVE APPLICATIONS DISCLAIMER

AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT

WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS
THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A
SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262
AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING
OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST
SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION
WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO
APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT
LIABILITY.

Copyright

© Copyright 2012-2024 Advanced Micro Devices, Inc. AMD, the AMD Arrow logo, Kintex,
UltraScale+, Versal, Vitis, Vivado, Zynq, and combinations thereof are trademarks of Advanced
Micro Devices, Inc. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, PrimeCell,
Mali, and MPCore are trademarks of Arm Limited in the US and/or elsewhere. PCI, PCIe, and PCI
Express are trademarks of PCI-SIG and used under license. The DisplayPort Icon is a trademark
of the Video Electronics Standards Association, registered in the U.S. and other countries. Other
product names used in this publication are for identification purposes only and may be
trademarks of their respective companies.

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