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Vivado Design Suite Tutorial

Design Analysis and Closure Techniques

Vivado Design Suite

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Table of Contents
Tutorial Overview........................................................................................................... 4
Navigating Content by Design Process.................................................................................... 4
Introduction................................................................................................................................. 4
Tutorial Description.....................................................................................................................4
Software Requirements.............................................................................................................. 5
Locating Tutorial Design Files....................................................................................................5

Chapter 1: Setting Waivers with the Vivado IDE...........................................6

Introduction................................................................................................................................. 6
Step 1: Starting the Vivado IDE..................................................................................................6
Step 2: Generating the CDC Report.......................................................................................... 7
Step 3: Waiving a Single CDC Violation.....................................................................................8
Step 4: Generating a Report for Waived Violations...............................................................12
Step 5: Generating a Text Report with Details for Waived Violations.................................13
Step 6: Waiving Multiple CDC Violations................................................................................ 14
Step 7: Exporting Waivers........................................................................................................ 17
Step 8: Using the create_waiver Command........................................................................... 18
Step 9: Waiving Multiple CDC Violations................................................................................ 19
Step 10: Waiving Multiple DRC Violations.............................................................................. 21
Step 11: Generating a Summary Report for Waived Violations...........................................26
Step 12: Using Waiver Commands.......................................................................................... 29
Summary.................................................................................................................................... 30

Chapter 2: Using Report QoR Suggestions and Report QoR

Assessment for Timing Closure........................................................................31
Introduction............................................................................................................................... 31
Step 1: Understanding the Design.......................................................................................... 32
Step 2: Running Report QoR Assessment.............................................................................. 34
Step 3: Running Report QoR Suggestions..............................................................................38
Step 4: Understanding the Report.......................................................................................... 39
Step 5: Run with Suggestions.................................................................................................. 43
Step 6: Accumulating Suggestions..........................................................................................47

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 Step 7: Automatically Running QoR Suggestions..................................................................49
Summary.................................................................................................................................... 51

Chapter 3: Running ML Strategies ..................................................................... 53

Introduction............................................................................................................................... 53
Step 1: Generating an ML Strategy RQS File.......................................................................... 53
Step 2: Creating ML Strategy Runs..........................................................................................55
Summary.................................................................................................................................... 57

Chapter 4: Intelligent Design Runs.................................................................... 59

Introduction............................................................................................................................... 59
Step 1: Creating Intelligent Design Runs............................................................................... 59
Step 2: Navigating Intelligent Design Runs........................................................................... 62
Step 3: Analyzing the Reports and Log File............................................................................65
Step 4: Final Analysis.................................................................................................................68
Summary.................................................................................................................................... 70

Chapter 5: Using the Dataflow Viewer............................................................. 71

Step 1: Opening the Project and Understanding the Design.............................................. 71
Step 2: Navigating the Dataflow Viewer ................................................................................ 77
Step 3: Generating Dataflow Paths ........................................................................................ 79
Step 4: Floorplanning ...............................................................................................................84
Step 5: Correlating Long Congestion with Dataflow Daths ................................................ 87
Summary.................................................................................................................................... 98

Appendix A: Additional Resources and Legal Notices............................. 99

Finding Additional Documentation......................................................................................... 99
Support Resources.................................................................................................................. 100
Revision History....................................................................................................................... 100
Please Read: Important Legal Notices................................................................................. 100

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 Tutorial Overview

Tutorial Overview

Navigating Content by Design Process

AMD Adaptive Computing documentation is organized around a set of standard design
processes to help you find relevant content for your current development task. You can access
the AMD Versal™ adaptive SoC design processes on the Design Hubs page. You can also use the
Design Flow Assistant to better understand the design flows and find content that is specific to
your intended design needs.

• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware
platform, creating PL kernels, functional simulation, and evaluating the AMD Vivado™ timing,
resource use, and power closure. Also involves developing the hardware platform for system
integration. Topics in this document that apply to this design process include:

• Chapter 2: Using Report QoR Suggestions and Report QoR Assessment for Timing Closure
• Chapter 3: Running ML Strategies
• Chapter 4: Intelligent Design Runs

Introduction
This tutorial uses the AMD Vivado™ design rules checker (report_drc), clock domain crossing
checker (report_cdc), and quality of results enhancer (report_qor_suggestions) to
analyze example designs for issues, and shows you how to take corrective actions. It also outlines
how to run ML strategies and intelligent design runs (IDRs).

Tutorial Description
Lab 1 walks you through creating waivers for (clock domain crossing) CDC, methodology, and
DRC (design rule check) violations.

Lab 2 is a guide to using the report_qor_suggestions (RQS) command.

Note: The designs used in this tutorial are intended to exhibit issues for demonstration purposes, and
should not be used as a reference for designs outside this tutorial.

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 Tutorial Overview

Software Requirements
This tutorial requires that the 2023.1 AMD Vivado™ Design Suite software release or later is
installed.

Lab 1 to lab 3 requires installing AMD UltraScale+™ and lab 4 requires installing AMD
UltraScale™ family.

For a complete list of system and software requirements, see the Vivado Design Suite User Guide:
Release Notes, Installation, and Licensing (UG973).

Locating Tutorial Design Files

1. Download the reference design files from the AMD website.
2. Extract the ZIP file contents into any write-accessible location.
This tutorial refers to the location of the extracted ZIP file contents as <Extract_Dir>.

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 Chapter 1: Setting Waivers with the Vivado IDE

Chapter 1

Setting Waivers with the Vivado IDE

Introduction
In the AMD Vivado™ Design Suite, you can use the waiver mechanism to waive clock domain
crossing (CDC), design rule check (DRC), or methodology check violations. After a violation is
waived, it is no longer reported by the report_cdc, report_drc, or report_methodology
commands. Waived checks are also filtered out from the mandatory DRCs run at the start of the
implementation commands, such as opt_design, place_design, and route_design. For
more information, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure
Techniques (UG906).

IMPORTANT! The content of the waiver is built with the objects that exist when the waiver is created.
However, if an instance referenced inside a waiver is replicated by AMD Vivado™, the replicated instance is
automatically added to the waiver and saved in subsequent checkpoints and XDC.

This lab shows how to set waivers with the Vivado integrated design environment (IDE) using
both menu commands and the Tcl Console. The lab focuses on CDC waivers, but the methods for
waiving DRC and methodology violations are similar.

Step 1: Starting the Vivado IDE

This lab uses a Vivado design checkpoint (.dcp file) that is a snapshot of a design. When you
launch the Vivado IDE using a design checkpoint, a subset of the Vivado IDE functionality is
available.

TIP: To launch the Vivado Tcl Shell on Windows, select Start → All Programs → Xilinx Design Tools →
Vivado <version> → Vivado <version> Tcl Shell.

1. From the command line or the Vivado Tcl Shell, change to the directory where the lab
materials are stored:
cd <Extract_Dir>/Lab1

2. To start the Vivado IDE with the design checkpoint loaded, enter the following:
vivado my_ip_example_design_placed.dcp

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 Chapter 1: Setting Waivers with the Vivado IDE

TIP: You can disregard the critical warnings about the unbounded GT locations.

Step 2: Generating the CDC Report

In this step, you generate the CDC report to view the associated CDC violations.

1. Select Reports → Timing → Report CDC.

2. In the Report CDC dialog box, leave the default settings as-is, and click OK.

The Summary (by clock pair) section of the CDC Report appears as follows.

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 Chapter 1: Setting Waivers with the Vivado IDE

The Summary (by CDC type) section appears as follows.

Step 3: Waiving a Single CDC Violation

The my_ip_glblclk to my_ip_axi_aclk clock pair includes one Critical CDC-10 violation
due to combinational logic on the CDC path. This step covers how to waive the CDC-10
violation.

1. To view a schematic of the violation, select the CDC-10 row in the CDC Report, and click the
Schematic toolbar button .
Note: Alternatively, press F4 to generate the schematic. However, using the toolbar button provides a
more detailed schematic that includes all the levels of the downstream synchronizer.

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 Chapter 1: Setting Waivers with the Vivado IDE

2. To waive the violation, select the CDC-10 row in the CDC Report, right-click, and select
Create Waiver.
3. In the Create Waiver dialog box, enter a description, and click OK.

IMPORTANT! A waiver tracks the date the waiver was added, the user that added the waiver, and a
description of why the violation was waived. The date is automatically added by the system. The Tags
field is an optional description or list of keywords that can be used for documentation purposes.

4. After the waiver is created, check the CDC Report.

To indicate that a waiver was created, the CDC-10 row is gray and disabled.
Note: Rows are only disabled in the Report CDC result window from which the waivers were created.

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 Chapter 1: Setting Waivers with the Vivado IDE

5. To see the impact of the CDC-10 waiver, select Reports → Timing → Report CDC to rerun
Report CDC.
Note: When a waiver is created or deleted, rerun Report CDC, Report DRC, or Report Methodology to
see the updated results.

6. See the CDC Report to view the updated information.

The differences from the previous Summary by clock pair and Summary by type sections are
highlighted in red in the following figures.

You can also view a summary with the list of waived endpoints.

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 Chapter 1: Setting Waivers with the Vivado IDE

The detailed section for the my_ip_glblclk to my_ip_axi_aclk CDC shows that the
Critical CDC-10 was replaced with an Info CDC-3.

7. Select the new CDC-3 row, and click the Schematic toolbar button . If F4 is used to open
the schematic, double-click the Q pin of the output register to expand the schematic to
match what is shown in the following figure.
The CDC path includes a 5-level synchronizer on the output of the selected destination
register. This is the reason the CDC-10 was replaced with CDC-3 for this topology, as shown
in the following figure.

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 Chapter 1: Setting Waivers with the Vivado IDE

IMPORTANT! By default, Report CDC only reports a single violation per endpoint and per clock pair.
When multiple violations apply to the same endpoint, only the violation with the highest precedence is
reported. Because CDC-10 has a higher precedence than CDC-3, only CDC-10 is reported when both
CDC-10 and CDC-3 apply to the same endpoint. For more information on CDC rules precedence, see
this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

TIP: To report all of the CDC violations for each endpoint regardless of the precedence rules, use the
command line option -all_checks_per_endpoint. However, unsafe rules are not reported on a
register if at least one safe rule on the same register is detected.

Step 4: Generating a Report for Waived

Violations
You can generate a report for the CDC, DRC, or methodology check violations that were waived.
This step shows how to generate a report for waived CDC violations using the Tcl Console as
well as the Vivado IDE menu commands.

Generating a Text Report for Waived Violations

1. In the Tcl Console, enter:
report_cdc -waived

2. In the CDC report, verify that a single CDC-10 violation is listed, because only one waiver
was created.

Generating a Vivado IDE CDC Report for Waived

Violations
1. Select Reports → Timing → Report CDC.
2. In the Report CDC dialog box, enable Report only waived paths, and click OK.
3. In the CDC Report, check the Summary (by clock pair) and CDC Details to verify that a single
CDC-10 violation is listed.

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 Chapter 1: Setting Waivers with the Vivado IDE

Note: The icon next to the violation shows that the violation was waived .

Step 5: Generating a Text Report with Details

for Waived Violations
In this step, you generate text reports with additional details, including a list of all of the rules and
all of the violations regardless of the waivers.

Generating a List of Rules with Waived Violations

1. In the Tcl Console, enter:
report_cdc -details -show_waiver

2. Verify that the my_ip_glblclk to my_ip_axi_aclk CDC-10 violation is waived and the
two CDC-3 violations are not waived.
Note: In the text report, all of the rules are reported, whether they were waived or not. The Waived
column indicates the status of the rule.

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 Chapter 1: Setting Waivers with the Vivado IDE

Generating a List of All Violations Regardless of the

Waivers
1. In the Tcl Console, enter:
report_cdc -no_waiver

2. In the text report, verify that the table matches the original report from Report CDC before
the CDC-10 waiver was created.

TIP: You can also generate a list of all violations regardless of the waivers from the Vivado IDE. Select
Reports → Timing → Report CDC. In the Report CDC dialog box, enable Ignore all waivers, and click
OK.

Step 6: Waiving Multiple CDC Violations

Note: Before resuming step 6, go to cdc_2 window.

The my_ip_axi_aclk to my_ip_drpclk CDC includes two critical CDC-11 violations. This
step covers how to waive both CDC-11 violations simultaneously.

1. To waive the violations, select the CDC-11 rows in the CDC Report, right-click, and select
Create Waiver.

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 Chapter 1: Setting Waivers with the Vivado IDE

2. In the Create Waiver dialog box, enter a description, and click OK.

In the Timing Report, the two selected rows are disabled when the waivers are created.
Note: One waiver is created for each selected row. In this example, two waivers are created.

3. Select Reports → Timing → Report CDC to rerun Report CDC. In the Report CDC dialog box,
make sure that Report only waived paths is unchecked, and click OK.
4. In the CDC Report, look at the my_ip_axi_aclk to my_ip_drpclk CDC.
The two critical CDC-11 violations were replaced with two Info CDC-9 violations. Based on
the CDC precedence rules, waiving CDC-11 unmasks CDC-9 for this circuit.

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 Chapter 1: Setting Waivers with the Vivado IDE

5. To view a schematic of the violation, select the CDC-9 row in the CDC Report, and click the
Schematic toolbar button .
6. Verify that there is a 5-level synchronizer on the destination clock domain.

7. Compare the new Summary (by type) information with the information from the previous
CDC Report.
In the updated CDC Report, the two CDC-11 violations are no longer listed. Instead, there
are two new CDC-9 violations.

8. Look at the Summary (by waived endpoints) information.

In the updated CDC Report, there are three waived endpoints. This number is different from
the number of waived violations (2), because CDC-11 is a multi-bit violation.

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 Chapter 1: Setting Waivers with the Vivado IDE

9. Generate different text reports and compare the results with previous reports.
For example, you can run the following Tcl commands:
report_cdc -details
report_cdc -details -waived
report_cdc -details -show_waiver
report_cdc -details -no_waiver

The following report was generated using the report_cdc -details -waived Tcl
command and shows that three violations were waived.

Step 7: Exporting Waivers

In this step, you export waivers with the write_waivers Tcl command.

Note: The XDC output file can be imported using the read_xdc or source Tcl commands.

1. To export the CDC waivers, enter: write_waivers -type cdc waivers.xdc.

TIP: Alternatively, because there are no DRC or methodology waivers, you can enter:

write_waivers waivers.xdc or write_xdc -type waiver waivers.xdc.

2. Open the waivers.xdc file to view the three waivers.

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 Chapter 1: Setting Waivers with the Vivado IDE

Note: The following example is reformatted to better show the different command line options.

create_waiver -type CDC -id {CDC-10} -user "AMD" \

-desc "This is a safe CDC per review with the team" \
-from [get_pins i_my_ip_support_block/jesd204_i/inst/i_my_ip/i_tx/
i_tx_counters_32/got_sysref_r_reg/C] \
-to [get_pins {i_my_ip_support_block/jesd204_i/inst/
sync_tx_sysref_captured/syncstages_ff_reg[0]/D}] \
-timestamp "<timestamp>" ;#1

create_waiver -type CDC -id {CDC-11} -user "AMD" \

-desc "Safe fanout. Circuitry has been released" \
-from [get_pins {i_my_ip_support_block/jesd204_i/inst/
i_my_ip_reset_block/stretch_reg[10]/C}] \
-to [get_pins {i_my_ip_support_block/i_jesd204_phy/inst/
jesd204_phy_block_i/sync_rx_reset_data/xpm_cdc_async_rst_inst/
arststages_ff_reg[0]/CLR}] \
-timestamp "<timestamp>" ;#1

create_waiver -type CDC -id {CDC-11} -user "AMD" \

-desc "Safe fanout. Circuitry has been released" \
-from [get_pins {i_my_ip_support_block/jesd204_i/inst/
i_my_ip_reset_block/stretch_reg[10]/C}] \
-to [get_pins {i_my_ip_support_block/i_jesd204_phy/inst/
jesd204_phy_block_i/sync_tx_reset_data/xpm_cdc_async_rst_inst/
arststages_ff_reg[0]/CLR}] \
-timestamp "<timestamp>" ;#2

Step 8: Using the create_waiver Command

Waivers added from the Report CDC dialog box are created using the create_waiver
command. You can view these commands as follows.

Note: You can use the create_waiver command line command for CDC, DRC, and methodology
waivers. The options differ slightly depending on whether you are creating a CDC, DRC, or methodology
waiver. For more information, including information on the different options, see the create_waiver
command in the Vivado Design Suite Tcl Command Reference Guide (UG835).

1. Open the Vivado journal file (vivado.jou) to see the three distinct create_waiver
commands issued by the Vivado IDE.
2. Scroll through the history of the Tcl Console to see the same three create_waiver
commands.

TIP: The -from and -to options are used to specify the startpoints and endpoints. When a waiver
is set from the Report CDC dialog box, both -from and -to are specified to match the exact
violation. However, you can specify a CDC waiver using only the -from option or only the -to
option, but more paths might be waived than expected.

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 Chapter 1: Setting Waivers with the Vivado IDE

Step 9: Waiving Multiple CDC Violations

In this step, you waive multiple CDC violations simultaneously.

1. In the CDC Report, view the my_ip_axi_aclk to my_ip_glblclk CDC under CDC
Details.
This crossing has five CDC-14 violations that are multi-bit violations. The five CDC-14
violations all start from the same two register clock pins:
i_my_ip_support_block/jesd204_i/inst/tx_cfg_test_modes_reg[2:1]/C

TIP: You can sort the table by the column ID to more easily see the five CDC-14 violations.

2. Because i_my_ip_support_block/jesd204_i/inst/
tx_cfg_test_modes_reg[*]/C matches five pins and you only need to target two of
those five pins, construct the list of startpoints as follows:
set startpoints [list \
[get_pins i_my_ip_support_block/jesd204_i/inst/
tx_cfg_test_modes_reg[1]/C] \
[get_pins i_my_ip_support_block/jesd204_i/inst/
tx_cfg_test_modes_reg[2]/C] \
]

3. To waive the five CDC-14 violations, use the create_waiver Tcl command with the -from
option:
create_waiver -type {CDC} -id {CDC-14} -user {AMD} -desc {No more CDC
14!} -from $startpoints

4. From the Vivado IDE, select Reports → Timing → Report CDC to rerun Report CDC.
5. In the CDC Report, verify that the CDC-14 violations are no longer reported in the Summary
section.

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 Chapter 1: Setting Waivers with the Vivado IDE

6. To report only the waived violations, enter:

report_cdc -details -waived

The following figure shows the waived CDC violations in two different tables. The first table
shows the 5 CDC-14 violations waived as multi-bit violations. The second table shows the 10
single-bit violations, calculated by multiplying the 5 multi-bit violations by 2 bits per multi-bit
violation.

7. To export all the waivers inside a script and verify that a total of four waivers were added,
enter:
write_waivers -type cdc waivers.xdc -force

Note: Because the waivers.xdc file already exists, the -force option must be specified to override
the file.

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 Chapter 1: Setting Waivers with the Vivado IDE

TIP: Alternatively, because there are no DRC or methodology waivers, you can enter:

write_waivers waivers.xdc -force

or

write_xdc -type waiver waivers.xdc -force

The list of waivers inside waivers.xdc appears as follows.

8. To import the waivers.xdc file, enter:

read_xdc waivers.xdc

The following warnings show that the duplicate waivers were not added to the existing
waivers. Only waivers that are exact duplicates of existing waivers are rejected.
WARNING: [Vivado_Tcl 4-935] Waiver ID 'CDC-10' is a duplicate and will
not be added again.
WARNING: [Vivado_Tcl 4-935] Waiver ID 'CDC-11' is a duplicate and will
not be added again.
WARNING: [Vivado_Tcl 4-935] Waiver ID 'CDC-11' is a duplicate and will
not be added again.
WARNING: [Vivado_Tcl 4-935] Waiver ID 'CDC-14' is a duplicate and will
not be added again.

Step 10: Waiving Multiple DRC Violations

In this step, you waive multiple DRC violations simultaneously.

1. Select Reports → Report DRC.

2. In the Report DRC dialog box, leave all settings at their default, and click OK.

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 Chapter 1: Setting Waivers with the Vivado IDE

3. In the DRC Report, right-click UCIO#1, and select Create Waiver to create a waiver for the
UCIO-1 violations.
Note: The UCIO#1 violation combines 115 individual violations into a single violation. Similarly, the
NSTD#1 violation covers 113 ports.

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 Chapter 1: Setting Waivers with the Vivado IDE

4. In the Create Waiver dialog box, look at the output in Tcl Command Preview, and click OK.

5. To generate the drc_waivers.xdc file and verify that the waiver is waiving all 115 objects,
enter:
write_waivers -type DRC drc_waivers.xdc

6. In the XDC file, look at the expanded port list, and check that some of the strings from the
violations message were converted to wildcards (*).
Strings are automatically converted to wildcards for UCIO-1, NSTD-1, TIMING-15, and
TIMING-16 type violations. For UCIO-1, the numbers of objects in the violations are replaced
with wildcards, because the numbers of elements are not meaningful.

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 Chapter 1: Setting Waivers with the Vivado IDE

7. To delete the DRC waiver and rewrite the waiver using wildcards to target a subset of the
ports objects, enter:
delete_waivers [get_waivers -type drc]
create_waiver -type DRC -id {UCIO-1} -user "AMD" -desc "Waive selected
UCIO violations" -objects [get_ports { s_axi_rdata[*] s_axi_wdata[*]
s_axi_araddr[*] } ] -strings { "*" } -strings { "*" }

Note: This command only covers a subset of the original 115 objects.

8. Select Reports → Report DRC to rerun Report DRC.

9. In the Report DRC dialog box, select Display only waived violations to report only waived
violations, and click OK.

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 Chapter 1: Setting Waivers with the Vivado IDE

In the DRC Report, verify that only 68 violations are waived out of 115.

IMPORTANT! You cannot waive READONLY or NODISABLE violations. For example, if you enter:

create_waiver -type DRC -id RTSTAT-1 -description "Waive RTSTAT-1"

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 Chapter 1: Setting Waivers with the Vivado IDE

The Vivado tools issue the following error:

ERROR: [Vivado_Tcl 4-934] Waiver ID 'RTSTAT-1' is READONLY or

NODISABLE and cannot be waived.
These Factory designations specify that a check is required and may
not be overridden by user action.

Step 11: Generating a Summary Report for

Waived Violations
This step covers how to use the report_waivers Tcl command to generate a summary report
for CDC, DRC, and methodology waivers.

IMPORTANT! Before running the report_waivers command, you must rerun Report CDC, Report
DRC, or Report Methodology to ensure that added or removed waivers are included in the statistics
reported by report_waivers.

1. To rerun Report CDC, enter:

report_cdc

2. To rerun Report DRC, enter:

report_drc

Note: You do not need to rerun Report Methodology, because no methodology waivers were set.

3. To create a summary report, enter:

report_waivers

By default, report_waivers reports only waived violations. The following figure shows the
UCIO-1, CDC-10, CDC-11, and CDC-14 rules that have defined waivers.

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 Chapter 1: Setting Waivers with the Vivado IDE

Note the number of waived objects and total violations:

• The aggregating DRCs are reported as 1 violation per object inside the violation. Because
there are 113 objects in NSTD-1, 115 objects in UCIO-1, 1 in RTDAT-13, and 1 in
AVAL-326, a total number of 240 DRC violations are reported in the summary table.
• The Report Summary table reports all of the violations.
• The Report Details tables only report the check IDs that have one or more waivers.
4. To generate detailed tables with all of the rules, including rules with no waivers, enter:
report_waivers -show_msgs_with_no_waivers

The following figure shows the report with all DRC and CDC rules reported in the Report
Details.

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 Chapter 1: Setting Waivers with the Vivado IDE

5. To run Report Methodology, enter:

report_methodology

6. To generate detailed tables with all of the rules, including rules with no waivers, enter:
report_waivers -show_msgs_with_no_waivers

The exact statistics are reported, as shown in the following figure.

Note: This figure does not include the Report Details (CDC) section.

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 Chapter 1: Setting Waivers with the Vivado IDE

Step 12: Using Waiver Commands

In this step, you run additional commands related to the waivers.

1. To return a collection of CDC waiver objects, enter:

get_waivers -type cdc

The following CDC waivers are returned:

CDC-10#1 CDC-11#1 CDC-11#2 CDC-14#1

2. To filter the list of waivers to only return CDC-14 waivers, enter:

get_waivers -filter {ID == CDC-14}
CDC-14#1

3. To report all of the properties on a CDC waiver object, enter:

report_property [lindex [get_waivers -type cdc] end]

The following properties are returned:

Property Type Read-only Value
CLASS string true cdc_waiver
DESCRIPTION string false No more CDC-14!
ID string true CDC-14
INDEX string true 1
IS_SCOPED bool true 0
NAME string true CDC-14#1
OBJECT_COUNTS string true pins:2

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SCOPE string true

TAGS string false
TIME string true <timestamp>
TYPE string true CDC
USED_CNT string true 10
USER string true AMD

Note: You cannot retrieve the design objects attached to a waiver object.

4. To delete all of the previously created CDC-14 waivers, enter:

delete_waivers [get_waivers -filter {ID == CDC-14}]

Note: After a waiver object is deleted, the waiver no longer applies and the violations that it waived are
reported again.

5. To delete all of the remaining CDC waivers, enter:

delete_waivers [get_waivers -type cdc]

Summary
In this lab, you accomplished the following:

• Waived CDC and DRC violations

• Generated reports for waived violations
• Exported waivers
• Used waiver commands

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 Chapter 2: Using Report QoR Suggestions and Report QoR Assessment for Timing
Closure

Chapter 2

Using Report QoR Suggestions and

Report QoR Assessment for Timing
Closure

Introduction
The report_qor_suggestions (RQS) command enables the AMD Vivado™ Design Suite
tools to analyze a design and provide automated solutions for enhancing quality of results (QoR).
The command can be run on an open design after synthesis or after any stage in the
implementation flow. The RQS command evaluates the design and suggests fixes or
improvements. Recommendations from RQS can take the following forms:

• RQS objects. These objects can add switches to a given command, or properties to a given
design object. They also allow you to add implementation strategies customized for the design
using machine learning algorithms.
• Text recommendations that require user intervention.

Using the same analysis techniques, the report_qor_assessment (RQA) command assesses
the likelihood that a design meets its timing requirements and provides a quick summary of
design metrics.

This lab covers how to do the following:

• Analyze the QoR assessment report.

• Analyze the QoR suggestion report.
• Export suggestions to an RQS file.
• Add an RQS file to synthesis and implementation runs.
• Accumulate suggestions in an RQS file by generating suggestions at different implementation
stages or on different runs.
• Add the AUTO_RQS property to a project-based design run and automatically accrue
suggestions.

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Step 1: Understanding the Design

This lab uses an architected design to demonstrate some of the features of RQS. Suggestions are
triggered by the design of the RTL and the placement of blocks using floorplanning. The design
contains the following modules:

• Clocking Module: The main clocking circuit for the design resides in
clocking_module.vhd. For simplicity, RST is tied to GND. LOCKED is registered and tied
to an output port. The structure of this block is shown in the following figure.

• Reg CLKA to CLKB Module: This module contains a synchronous CDC for a large bus. It
registers input data using CLKA and then passes it to a register on the CLKB domain to be
passed to the output. Registering large buses on different related clock domains can impact
hold slack (WHS/THS) and setup slack (WNS/TNS).

• Bit Expander and Bit Reducer Modules: These modules enable the expansion and contraction
of internal data widths so that the design does not run out of I/Os. The modules take an
arbitrary data width and expand or contract it to or from a desired size. The contraction logic
creates many logic levels.

The following steps cover opening the project and examining the placement of the floor-planned
modules.

1. In the Vivado Design Suite, go to File → Project → Open and select the project located in
<extract_Dir>/Lab2/project_2.

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2. In the Flow Navigator, click Run Synthesis and wait for synthesis to complete.
3. In the Flow Navigator, click Open Synthesized Design.
4. In the Netlist view, look at the hierarchy.

5. In Device view, look at the pblock. This has been added to control placement of the
reg_clka_to_clkb modules and force a poor clock skew.

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Step 2: Running Report QoR Assessment

In this step, you run the report_qor_assessment command on the open design. This step
can be run after any stage of the implementation process: synth_design, opt_design,
place_design, phys_opt_design, and route_design. It provides an assessment score
that details the likelihood of the design closing timing, as well as a quick first analysis returning
items that need to be further investigated.

1. With the design open, click Reports → Report QoR Assessment....

2. In the Report QoR Assessment dialog box, select Report Passing Metrics and click OK.

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The equivalent Tcl command is as follows:

report_qor_assessment -exclude_methodology_checks -name qor_assessments -
max_paths 100 -full_assessment_details

This opens up the assessment report, with three main sections providing the following:
• Assessment summary
• Difficult timing paths requiring investigation
• Objects with DONT_TOUCH properties that prevent tool optimizations
3. In the first section of the report, select RQA Summary.

This section has the score marked as "2 - Implementation may complete. Timing will not
meet". It also recommends running report_qor_suggestions. The RQA command
understands when suggestions are available and can offer the guidance to check them.
4. Select Assessment Details.

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This section lists the items that have led to the assessment score of 2. Because the option to
Report passing metrics was selected, items marked as OK are shown. Typically, only items
marked REVIEW are shown. In this example, you can see WNS and TNS metrics marked for
review, as well as paths above their net/LUT budget.
Timing paths usually offer the values that are achievable in the best case scenarios. Not all
paths can achieve these values. Net and LUT budget checks substitute net or LUT values with
more typical values, and also penalize paths that are more challenging due to a netlist profile
or a resource being less sparse. The result is two checks performed under this item. Look at
all of these paths before continuing.
5. Select Net/LUT budget under Challenging Timing Paths.

Scroll across the screen to see all the path characteristics reported. The following items are of
particular interest:
• SuggestionIds: These IDs correspond to suggestions that, if triggered, impact this path.

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• Net Check Slack: This is the slack when the path is substituted with higher net delay
values.
• LUT Check Slack: This is the slack when LUTs are substituted with higher LUT delay
values.
6. Double-click on the path to bring up the Timing Path report. You can also press F4 to show a
schematic. All of these items use standard Vivado cross probing. At this stage, you can also
explore other items in the report.
7. In the Design Runs window, select impl_1, expand the Implementation Run Properties
window, and select the Properties tab. Locate the MIN_RQA_SCORE property.

When the MIN_RQA_SCORE property is set, an implementation run will be terminated if

RQA is run and the assessment score value is less than the value specified. As the minimum
RQA score is 1, MIN_RQA_SCORE must be set to 2 or greater to have an impact.
Edit the value of MIN_RQA_SCORE and set this to 3.
8. Next, the implementation run must generate the QoR Assessment report.
In the implementation Run Properties box, select the Reports tab. In the Report Strategy pull
down menu, select the Timing Closure Report Strategy. This is only one way of setting the
run to generate the report. Other methods are:
a. Creating a custom report strategy.
b. Adding report_qor_assessment to a Tcl hook. This must run the report in the run
directory to be effective.
9. Launch the impl_1 run.
After opt_design is complete, the report_qor_assessment command is run and the
run should terminate. You should see the following in the Design Runs status column:

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The log file should have the following message:

INFO: [runtcl 7-1] RQA Score (opt_design): 2 (RQA score tolerance: 3)

ERROR: [runtcl 8-1] Flow terminated - RQA score threshold not met after
'opt_design' step

The following message appears when the flow successfully passes the check:

INFO: [runtcl 7-1] RQA Score (opt_design): 2 (RQA score tolerance: 2)

INFO: [runtcl 9-1] Flow continues - RQA score threshold met after
'opt_design' step

10. Update the MIN_RQA_VALUE to 1. Revert the reports back to Vivado Implementation
Default Reports and reset the run.

Step 3: Running Report QoR Suggestions

This step covers running the report_qor_suggestions command to generate a report. The
command can be run on an open design at any stage of the implementation flow after synthesis.
In project mode, this is typically after synthesis or implementation. In non-project mode, this can
be after synth_design, link_design, opt_design, place_design, phys_opt_design,
or route_design.

1. In the Vivado IDE, from the pull-down menus, click Reports → Report QoR Suggestions... to
bring up the dialog box shown in the following figure.

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2. Click OK to run the command. The report opens automatically in the integrated design
environment (IDE). Due to the interactive nature of the report, only one instance of the
report can be open at any time. The equivalent Tcl command is as follows:
report_qor_suggestions -max_paths 100 -file rqs.rpt

Note: By default, the RQS command reports on the 100 worst failing paths per clock group. You can
change the number of paths that RQS uses for the analysis of timing-critical paths by modifying the -
max_paths switch. Increasing this number generates more suggestions, but on paths that are reducing in
criticality.

Step 4: Understanding the Report

This step explains the different sections of the generated QoR Suggestions report. On the left of
the report window, you can navigate to the different sections of the report; on the right, more
information is provided.

1. In the Suggestion Report, select GENERATED. This brings up the report section shown in the
following figure.

The GENERATED section provides a list of all the suggestions that have been generated at
this stage of the current run. Each suggestion has a description that details the reason for the
suggestion. For each suggestion, the following information is also provided.

Table 1: RQS Summary Column Description

Item Description Comment

GENERATED_AT This shows what stage of the design As you progress through the design stages, the decisions
the suggestion was generated at. that the tool makes are based on the information
Typical values are place_design or available at the time. Information accuracy increases after
route_design. placement and again after routing.

APPLICABLE_FOR This stage must be rerun for the Most suggestions are executed at either synth_design
suggestion to take effect. or place_design.

AUTOMATIC Indicates if the suggestion is Automatic suggestions either recommend a switch to the
executed automatically or if manual tool or a property to be added to a cell or net.
intervention is required.

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Table 1: RQS Summary Column Description (cont'd)

Item Description Comment

INCREMENTAL Indicates if the suggestion is Non-incremental friendly suggestions must be already
FRIENDLY optimized for the incremental flow. present in the reference checkpoint. If you want to add
non-incremental friendly suggestions, an updated
reference checkpoint must be used.
SCOPE Indicates the target synthesis run Allows a single RQS file to be used on top-level and sub-
level. GLOBALSCOPE is top level. module out of context (OOC) synthesis runs. Only
Otherwise, a sub-module is targeted. applicable to synthesis suggestions.

The other sections of the report usually provide details about the individual suggestions that
have been generated.
2. Click the RQS_XDC_1_1 hyperlink. This takes you to the detailed section for this suggestion.

The suggestion description says that the timing constraint is too tight for the given path(s).
The path has a large negative slack that stands out in a timing report. Timing paths use net
delays that are optimal. This gives the tools the correct order to place and route them. Close
analysis shows this is a 600 MHz path with high logic levels. This path needs to be fixed.

3. Click the back arrow button ( ) to go back to the GENERATED view.

4. In the GENERATED view, click the RQS_TIMING-33_2-1 row. You can see this is an
AUTOMATIC suggestion that is applicable for synth_design (see the APPLICABLE_FOR
column). This indicates that you must rerun the synth_design command to make use of
this suggestion.

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When you select the row in the GENERATED view, the suggestion object is selected and the
properties can be seen in the QoR Suggestion Properties window. If you examine the
COMMAND property, you can confirm that it generates a retiming forward property for
synth_design.

5. In the GENERATED view, click the RQS_TIMING-33_2-1 ID to go to the details table for that
suggestion. Careful examination of the Endpoint column confirms that this is the same path
that was mentioned for RQS_XDC-1-1.

6. In the GENERATED view, you can see the remaining suggestions. The RQS_CLOCK-9
suggestion is applicable for place_design. The RQS_TIMING-44 suggestion is similar to
the existing one.

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7. Only select the four suggestions highlighted in the following image to written to the RQS
suggestion object file:

8. Click Write Suggestions. When the Write Suggestions to Project dialog box opens, ensure it
is set to write to the rqs_report.rqs file in the utils_1 directory, as shown in the
following figure. Select Copy sources to project.

9. Examine the Sources window. The RQS file has been added to the utils_1 fileset. This
ensures that the file is captured using the get_files command and recognized in the next
step when you add the file to a run.

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Step 5: Run with Suggestions

In this step, you add a suggestion to a run and examine what happens when a suggestion is
applied and how it is reported.

1. In the Design Runs window, right-click on the synthesis run, select Copy Run, and click OK.
Do the same for the implementation run, but update the synthesis run name to the new one
you have just created, and click OK.

2. In the Design Runs window, right-click the new synth_1_copy_1 run and select Set QoR
Suggestions.

3. Specify the suggestion file as the RQS file added to the project from the previous step and
click OK.

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4. Repeat steps 2 and 3 for the implementation run, making sure to specify the new synthesis
run as the parent run. Specify the same RQS file for each run. There is a slightly different
dialog box for implementation.

5. In the Design Runs window, right-click synth_1_copy and select Make Active.
6. In the Flow Navigator, click Run Synthesis.
7. Because this design takes a long time to route, you only run to place_design and analyze
at this stage. When synthesis is complete, in the Design Runs window, right-click on the new
implementation run and select Launch Step To → place_design.

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8. With the implementation running, select the Design Runs window. Right-click the
synth_1_copy synthesis run and click Open Run.
9. When the run has opened, select Reports → QoR Assessment... and click OK.
10. Click RQA Summary. The score has improved from 2 to 3.

11. Click Assessment Details. The Net and LUT budget score has been reduced but not
eliminated. This is a consequence of the high frequency that paths are being forced to run at
in this design.

12. Close the synthesized design.

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13. When place_design is finished, examine the very top of the implementation log file for
the new implementation run. It provides a table summary of the suggestions that have been
read in. This summary helps you confirm that what has been read in is what you expect.

1. Read QOR Suggestions Summary

-------------------------------

Read QOR Suggestions Summary

+---------------------------------------------+---------------+-------+
| Suggestion Summary | Incr Friendly | Total |
+---------------------------------------------+---------------+-------+
| Total Number of Enabled Suggestions | 1 | 4 |
| Automatic | 1 | 4 |
| Manual | 0 | 0 |
| APPLICABLE_FOR | | |
| synth_design | 0 | 3 |
| opt_design | 0 | 0 |
| That overlap with synthesis suggestions | 0 | 0 |
| place_design | 1 | 1 |
| postplace_phys_opt_design | 0 | 0 |
| route_design | 0 | 0 |
| postroute_phys_opt_design | 0 | 0 |
| ML Strategy | 0 | 0 |
| Total Number of Disabled Suggestions | 0 | 0 |
+---------------------------------------------+---------------+-------+

14. Go to Select File → Checkpoint → top_placed.dcp in the impl_1_copy_1 run directory. Do

not close the current project.
15. In the new instance of the Vivado tools, select Reports → Report QoR Suggestions ... and
click OK.
16. In the new report, there are more sections under Suggestion Report:
• GENERATED: New suggestions are listed in this section.
• EXISTING: Suggestions that existed previously but have not been applied are listed in this
section (not shown).
• APPLIED: Suggestions that have been applied are listed in this section.
• FAILED TO APPLY: Suggestions that apply to design objects that no longer exist are listed
in this section (not shown).

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17. Click APPLIED and select the details table for one of the items. For APPLIED suggestions, the
timing path summary is still available but it is not possible to cross probe to other views in
Vivado because some items might have changed.

Step 6: Accumulating Suggestions

You can now review the newly generated suggestions and add them to the RQS file.

1. Click GENERATED. The RQS_CLOCK-15 message reports high THS paths but does not
provide an automatic suggestion.
2. Examine RQS_CLOCK-2-1. This suggestion recommends changing the clock buffers to
BUFGCE_DIV to improve the timing path uncertainty. It is highly recommended to implement
this. Because this suggestion is not automated, however, it requires an RTL edit. If you wish,
you can make the recommendation and see the improvement, but this step can be skipped.
The next steps focus on the automated suggestions.
3. Click on RQS_CLOCK-1-1 to view the detailed report. This suggestion applies
CLOCK_DELAY_GROUP to related clocks. In this report, you can see that there is a high
clock skew and failing slack.

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Clock skew is difficult to identify before place_design because the skew estimate depends
heavily on placement. As a consequence, RQS does not offer this suggestion unless a design
is placed. Whenever there is a change in information level, it might be advisable to run
report_qor_suggestions. The following summarizes the changes as you progress
through the tool flow:
• Clocking estimates are accurate after place_design.
• Congestion is available after placement and improves further after routing.
• Timing estimates improve throughout the flow and are impacted by the number of paths
analyzed.
4. Click Write Suggestions. When suggestions are written, the APPLIED status is reset. All the
previous suggestions and the new RQS_CLOCK-1-1 suggestion are combined into one file.
You can overwrite the previous file and reuse the runs, or create a new file and new runs.
5. Select the file location to overwrite the existing file. You can find out the location of this by
selecting it in the sources window. Alternatively, it should be at the following location if you
have followed the steps carefully: <extract_dir>/Lab2/project_2/
project_2.srcs/utils_1/imports/project_2.
You are now at the point where you know the fundamentals in handling RQS files and
accumulating suggestions. If you have time, rerun implementation through to
route_design and examine the impact of the latest suggestion. Alternatively, generate
alternative suggestions by running report_qor_suggestions on your own design.
6. Close the run.
7. In the Design Runs window, right-click the implementation run impl_1_copy_1 and select
Launch to → Route Design. When routing is complete, right-click and select Generate ML
Strategies. Doing this generates three RQS files that each contain one ML strategy
suggestion, the APPLIED suggestions, and optionally any GENERATED suggestions.

8. After the generation is complete, in the Design Runs window, right-click the implementation
run impl_1_copy_1 and select Create ML Strategy Runs. This creates three implementation
runs, each targeting a different ML-based implementation strategy.

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Step 7: Automatically Running QoR

Suggestions
In this section you run the AUTO_RQS flow, where suggestions are generated at the end of an
implementation run and automatically added to the run when it is reset.

1. In the Design Runs window, copy the original synthesis and implementation run again using
the right-click menu.
2. In the Design Runs window, right-click impl_2 → Set QoR Suggestions.
3. Select Automatically apply QoR suggestions from the previous run and Apply suggestions to
the parent Synthesis run.

4. You can now launch the runs. Suggestions are only generated at the end of route_design
using this method. The picture the flow sees can be different to the previous steps, so you
can expect different results. In addition, all AUTO suggestions generated or regenerated at
route_design are applied.
5. Launch the runs. This step takes some time because it launches the full implementation flow.
6. When the run is complete, go to the Reports tab and select the QoR Suggestions report.

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This report is generated automatically when the AUTO RQS flow is enabled. There is also
automatic writing of QoR suggestions. The suggestions written to the RQS file have one of
the following properties:
• GENERATED_AT or REGENERATED_AT equal to the final flow step, which can be
route_design or postroute_phys_opt
• AUTOMATIC
• APPLIED
7. Reset the implementation run. This makes the synthesis run out of date at the same time.
Because the option to apply suggestions to the parent synthesis run is selected, the RQS file
also reads in this run.
8. Right-click impl_1_copy_2 and launch the implementation run, also selecting the option to
restart the synthesis run.
9. With the run launched, select impl_1_copy_2 in the Design Runs window. Examine the
RQS_FILES property on the Implementation Run Properties window. During the reset run
process in step 7, the RQS file is copied from the run directory to the utils_1 fileset. The
RQS_FILES property is updated if required at the same time. RQS files in the implementation
run directory are deleted when the run is reset.
If the RQS_FILES property previously pointed to a different file, all the APPLIED suggestions
from this file are copied to the new RQS file and subsequently, this RQS file is no longer
required and is dropped.
10. Select Implementation Run Properties and then the Reports tab. After the design
initialization step is run, a report is made available that contains the QoR suggestions that
have been read into the run from the RQS file. Select this report.

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11. In the report, you can see that ML strategies have been generated. In the case of the
AUTO_RQS flow, the required RQS files are generated for you automatically. These files are
combined with all the suggestions that are currently APPLIED, as well as the suggestions that
meet the criteria outlined above to be added when the run is reset.

12. In the Design Runs window, right-click impl_1_copy_2 → Open Run Directory . Locate the
MLStrategy directory and confirm that there are three RQS files inside it. Close the folder.
13. In the Design Runs window, right-click impl_1_copy_2 → Create ML Strategy Runs. Doing
this creates three runs and automatically sets the RQS file and directives for you. ML
strategies are covered in more detail in the following lab.
14. When the implementation run completes, new suggestions are generated. Using only
impl_1_copy_2, repeat steps 6 to 10 for a clearer understanding of how the RQS file is
updated with the new suggestions.

Summary
In this lab, you achieved the following:

• Using RQA, you conducted an assessment before and after improvements were implemented,
examining an improvement in the score.

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• Using RQS, you conducted a complex analysis of a demonstration design. You first examined
the reports that showed RQS recommendations to solve implementation problems, then you
generated an RQS file and added it to a project implementation run. The Vivado
implementation tools executed the suggestions automatically for you. You subsequently
performed further analysis and generated further suggestions, accumulating them in the RQS
file.

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 Chapter 3: Running ML Strategies

Chapter 3

Running ML Strategies

Introduction
The report_qor_suggestions command can generate an implementation design strategy
that is predicted to be optimal for the design using machine learning algorithms. In this tutorial,
you look at:

• How to generate ML strategy suggestions.

• How to setup the implementation run to use ML strategy suggestions.
• Reporting specifics related to ML strategies.

Step 1: Generating an ML Strategy RQS File

This step shows the process of opening a routed design with QoR suggestions and generating a
new RQS file with strategies. For details on the design, refer to Step 1: Understanding the
Design.

1. In the Vivado Design Suite, go to File → Project → Open and select the project located in
<extract_Dir>/Lab3/project_2.

2. In the Flow Navigator, click Open Implemented Design.

3. From the pull-down menus, select Reports → Report QoR Assessment, and click OK.

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 Chapter 3: Running ML Strategies

4. In the RQA Summary table, you see the QoR Assessment Score and Flow Guidance. This
table helps identify optimal candidate designs that can effectively leverage ML strategy
suggestions. QoR assessment scores of 3 and above have a chance to meet timing. Designs
with an RQA score of less than 3 are not prevented from generating ML strategies.
5. Click ML Strategy Availability. This table details the required directives for the reference run
to generate strategies.

The status for all directives must be listed as OK to generate strategies. The requirements are
as follows:
• The opt_design directive value must be either Default or Explore.
• The place_design, phys_opt_design, and route_design conditions must be the
same as each other and must be set to either Default or Explore.
6. In the Design Runs window, confirm the strategy is Vivado Implementation Defaults. This
requirement is met when a design has been run with either the Vivado implementation
defaults or the performance_explore strategy.
7. From the pull-down menus, select Reports → Report QoR Suggestions, and click OK.
8. In the QoR suggestion report, select GENERATED. Three new strategies have been
generated.

9. In the Strategy section, select the topmost strategy. Here, you can see the details of the
strategy being suggested. It is possible to set these up manually, but to automate the process
more easily, the recommended flow is to read an RQS file containing strategies and set the
directive to RQS on the implementation commands.

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 Chapter 3: Running ML Strategies

10. Select Write Suggestions to write the following files:

• A top-level RQS file that does not contain strategies (this file can be ignored)
• An RQS file for each strategy as well as any other QoR suggestions (written to the
MLStrategy directory).
Generating the strategy RQS files is the first part of a two-step process. This way of
generating the suggestions gives complete control over what other suggestions are in the
RQS file. Other ways to generate these files are as follows:
• Automatic generation using AUTO_RQS flow (as seen in Chapter 2: Using Report QoR
Suggestions and Report QoR Assessment for Timing Closure).
• Clicking Generate ML Strategies from the right-click menu in the Design Runs window.
• Automatic generation at the end of Stage 1: Design Optimization of Intelligent Design
Runs.
• A post-route Tcl hook script that calls both report_qor_suggestions and
write_qor_suggestions.

Step 2: Creating ML Strategy Runs

In this step, you create the ML strategy implementation runs using the files created in Step 1:
Generating an ML Strategy RQS File.

1. In the Design Runs window, select impl_3, then right-click and select Open Run Directory.
2. Search for the MLStrategy directory and examine the contents. You see three RQS files and
three non-project-based Tcl scripts. The RQS files are common for both project and non-
project flows. The non-project scripts are examples of how to use the RQS file.

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 Chapter 3: Running ML Strategies

3. The next step is to generate the ML strategy runs. As long as the files reside in the
<run_directory>/MLStrategy directory, this process can be automated. In the Design
Runs window, right-click the implementation run and select Create ML Strategy runs. Doing
this creates three runs, one for each ML strategy file. Configure the runs to use the RQS
directive and the RQS file to be read into each of them.
4. In the Design Runs window, select impl_3_ML_1.

5. In the Implementation Run Properties window, select the Properties tab and confirm that
RQS_FILES is set.
6. In the Implementation Run Properties window, select the Options and confirm the directive
is set to RQS for the opt_design, place_design, phys_opt_design, and
route_design commands.

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 Chapter 3: Running ML Strategies

You are now set up to run with ML strategies. By the time you have an ML strategy file, you
cannot generate new strategies after design changes, but you can add other suggestions.
7. You are now ready to launch the runs. Select all the ML strategy runs, right-click, and select
Launch Runs.... The runs now proceed in parallel, and complete like a standard run.

Summary
In this lab, you achieved the following:

• Used report_qor_suggestions to generate ML strategies.

• Created the RQS and Tcl files using write_qor_suggestions.

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 Chapter 3: Running ML Strategies

• Sourced the Tcl to set up the ML strategy runs and confirmed the key aspects of setting up an
ML strategy run.

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 Chapter 4: Intelligent Design Runs

Chapter 4

Intelligent Design Runs

Introduction
In this tutorial, you work with intelligent design runs (IDRs). An IDR is a simple-to-use
implementation run that extends the performance of your design by automating QoR
suggestions and ML strategies. These features are applied in a way that maximizes the
improvement in performance.

This lab covers how to:

• Create an IDR.
• Add Tcl hooks to the IDR.
• Examine the log file for an IDR.
• Examine reports for an IDR.
• Create a single pass run from an IDR.

Step 1: Creating Intelligent Design Runs

In this section, you create an example design and an Intelligent Design Run (IDR).

1. First, you need a project. Select Open Example Project.

2. Click Next→ BFT and then select Next again.

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 Chapter 4: Intelligent Design Runs

3. In the next screen, ensure you are working on in a suitable writable directory, and select
Next.
4. For part selection, you must select xcku035-fbva900-2-e and then select Next → Finish.

You should now have an open project that is waiting to be synthesized.

Note: IDRs are not supported for 7 series devices. Selecting the incorrect family requires you to
regenerate the project.

5. This lab aims to demonstrate how to add a Tcl file to an IDR. To do this, add a file to impl_1. In
the Design Runs window, select impl_1.

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 Chapter 4: Intelligent Design Runs

6. In the Implementation Run Properties window, select the Options tab.

7. Scroll to the opt_design tcl.pre option and add the Tcl script <extract_dir>/Lab4/
pre_opt.tcl to the option.

Alternatively, use the following Tcl syntax:

add_files -fileset utils_1 -norecurse <extract_dir>/Lab4/pre_opt.tcl
set_property STEPS.OPT_DESIGN.TCL.PRE [ get_files <extract_dir>/Lab4/
pre_opt.tcl -of [get_fileset utils_1] ] [get_runs impl_1]

8. In the Flow Navigator, click Run Synthesis.

9. The next step is to create the Intelligent Design Run. In the Design Runs window, right-click
on impl_1 → Close Timing using Intelligent Design Runs.

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 Chapter 4: Intelligent Design Runs

If you try this step again to create an additional run, you find that the option is disabled. This
is to prevent the creation of runs that would produce the same results. Runs created from the
same netlist with different directives produce the same results because the IDR controls the
directive, meaning that they are effectively the same.
If you have a different floorplan or speed grade, create different implementation runs. You
can create one IDR from each implementation run.

Step 2: Navigating Intelligent Design Runs

In this step, you learn how to control intelligent design runs and navigate options and reports.

1. Select the Intelligent Design Runs tab at the bottom of the AMD Vivado™ IDE.

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 Chapter 4: Intelligent Design Runs

This window is opened when an IDR is created. If closed, it can be reopened by selecting
Window → Intelligent Design Runs. From this window you can see that there is a hierarchical
nature to Intelligent Design Runs. The top-level run is split into three stages:
• Stage 1: Design Optimization
• Stage 2: Tool Option Exploration
• Stage 3: Last Mile Timing Closure
In this lab, only stage 1 is demonstrated. This is the most complex stage, but can be
completed quickly because you are working with a simple design.
2. Expand Stage 2: Tool Option Exploration.

There are three runs underneath this stage. These runs can be run in parallel if your compute
resources allow.
3. Right-click i_impl_1_1 → Launch Runs and select how you normally run jobs. Click OK.

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 Chapter 4: Intelligent Design Runs

4. Select impl_1_1 and view the Properties in the Implementation Run Properties window. A
PARENT property is set to synth_1. As is the case with a normal implementation run, there is
a dependency on the synthesis run to complete when this is set. If the RTL code is modified,
the run goes out of date.
5. Click the Design Runs tab and confirm that the synth_1 run is running or finished.
6. Click back to Intelligent Design Runs and right-click on the impl_1_1 top-level run.

The right-click menu from the top-level run is the main way to control the Intelligent Design
Runs. Some options only become available at specific times:
• Reset Runs is only available after a run is launched.
• View Reports is only available after reports are generated.
• Open Run is only available after a run is successfully completed.
• Generate Single Pass Run is only available after a run is successfully completed.
7. Select the lower-level run, i_impl_1_1_rqs, and right-click on it.

When the lower-level run is selected, you can see that there is a reduced set of options. The
Open Run Directory and Open Run options are scoped to the lower-level run. If Open Run is
selected, the best completed routed run is opened.

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 Chapter 4: Intelligent Design Runs

Step 3: Analyzing the Reports and Log File

In this task, you see where to find reports and analyze runs and intermediate checkpoints from
an intelligent design run.

1. If the window is not already open, select Reports → Intelligent Design Run Reports. This
window captures all the metrics that are captured throughout the IDR and provides links to
any generated reports.

The report is broken into two windows. The Flow Progress section is in the top half. This
details which steps have been run and which steps are running currently. This is more
important for an IDR as opposed to a standard implementation run for the following reasons:
• The IDR is a dynamic run, and not all stages are run for every design.
• The steps might be run repeatedly as the run is reset to apply QoR suggestions.
The Flow Statistics section is in the bottom half, and provides the following:
• Hyperlinks to any available reports
• Timing metrics such as WNS/TNS/WHS/THS

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 Chapter 4: Intelligent Design Runs

• RQA score
• Congestion level and tile % metrics for post-place and post-route designs
2. Focus in on the Flow Progress section of the report.

• Green ticks indicate a completed stage.

• Hyphens indicate the stage is not run.
• Circles indicate the stage is running.
Because there are no circle icons, you can infer that the run has completed successfully. Note
also the FIRST_PASS step that is generated for reporting purposes. This special step occurs
when there are no utilization or clock suggestions. Only designs without these suggestions
have this step.
At the bottom, there is a table footer that describes the meaning of the the $ and * notations.
These notations help you identify which runs you are opening when you select Open Run.
3. Look at the Flow Statistics section of the report. This report can be larger, and you can make
more space by reducing the divider between the section above and clicking on the arrows to
reduce sections of the report.

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 Chapter 4: Intelligent Design Runs

On the left of this window are the reports, in the middle are the timing and RQA statistics,
and on the right are the congestion metrics. Statistics are only available if the flow stage has
been run, or if the flow stage generates the statistics. For example, during place, hold
statistics are not generated.
4. Expand FIRST_PASS and click postplace_physopt_first_pass_util.rpt. Pay attention to the
name of this report: postplace_phys_opt indicates the implementation step and first_pass
indicates the flow step. When you are ready, close the report.
5. In the Intelligent Design Runs window, right-click impl_1_1 and select Open Run Directory. In
this directory, open the idr_flow_summary.rpt file. This is the text equivalent to the IDE
report. It contains the same information except the links to the report. When you are ready,
close the file.
6. In the directory explorer, go up one level to the project_1.runs folder. There is a directory for
the main IDR and each of the sub-runs. Click into impl_1_1_rqs. Here, you can see all the
reports and intermediate checkpoints. When you are ready, close the directory explorer.
7. In the Intelligent Design Runs window, select the top-level run impl_1_1.
8. In the Implementation Run Properties window, select the Log tab and maximize the window.
9. Select the search icon and enter "IDR 1-60". Click Next multiple times to navigate through
the log file. This ID highlights the start and end banners that have been added when you
enter and exit a step within Stage 1: Design Optimization.

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 Chapter 4: Intelligent Design Runs

It can be difficult to identify which step you are in as the implementation process goes back
and forth, . These messages can help clarify this.
10. Search for "INFO-TUTORIAL4." This has been inserted by the Tcl script you added in Step 1.
This Tcl script is executed every time opt_design is called. In this case, opt_design is
called only once, so it is similar to a normal flow.

Step 4: Final Analysis

In this task, you see how to analyze the design and create a single pass run.

1. In the Intelligent Design Runs window, right-click on the top-level run, impl_1_1, and then
click Open Run. Doing this opens the best overall run from the three stages. This is also the
best run from stage 1. Stage 2 and stage 3 were not run with this design. The best run and
best stage run are indicated by the $ and * notations.

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 Chapter 4: Intelligent Design Runs

A device view opens where you can generate reports and analyze the design as you would
with a normal implementation run. When you are ready, close the design.
2. In the Intelligent Design Runs window, right-click on the top-level impl_1_1_rqs and click
Open Run Directory. This directory has all the intermediate checkpoints from the stage. You
can open a new instance of Vivado and open the checkpoints for further analysis. If the DCP
is associated with Vivado, you can open the checkpoints by double-clicking on them.
3. When you are finished with analyzing the design, because an IDR can take the equivalent of
many implementation runs to complete, it is recommended to run the required commands
and suggestions in a single implementation run. In the Intelligent Design Runs window, right-
click on the top-level impl_1_1 and select Generate Single Pass Implementation Run.

4. In the Create Single Pass Implementation dialog box, enter a run name, impl1_a, and click
OK.

5. Switch to the Design Runs window. You can see that the new run has been made. Right-click
on the run and select Launch Runs. Confirm that the results are the same as the IDR.
Note: For more difficult runs, you can examine the RQS_FILES property and directives, but because this
is a design that meets timing easily, these are not set.

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 Chapter 4: Intelligent Design Runs

Summary
In this tutorial, you learned how to:

• Create and launch intelligent design runs.

• Analyze reports and checkpoints generated by an IDR.
• Create a single pass flow.

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 Chapter 5: Using the Dataflow Viewer

Chapter 5

Using the Dataflow Viewer

In this tutorial, you learn to use Dataflow Viewer (DFV) to analyze a design. The Dataflow Viewer
allows you to better understand key parts of a design that impact overall place and route quality.
This is achieved by:

1. Identifying wide, high bandwidth buses in the stripped-down dataflow optimized netlist.
2. Identifying the cells associated with these buses whose placement have a significant impact
on the placement quality of the design.
3. Generating paths of multiple cells related to the target wide buses that facilitate a more
holistic view of placement.
4. Generating a floorplan that joins associated cells on a bus together.

Step 1: Opening the Project and

Understanding the Design
Open the following checkpoint within the folder: <extract_dir>/Lab5/
part_filler_dsp_ram_routed.dcp. The design in the project is a module named
part_filler_dsp_ram. This module is a chain of smaller modules that do the following:

Figure 1: Repeat n instances

The design works as follows:

1. There is one memory in the design per DSP. Dummy data is written to and then read from
this memory.

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 Chapter 5: Using the Dataflow Viewer

2. The read data is registered.

3. The registered data is squared in pipelined DSP.
4. The bit expansion is then controlled by doing some rounding.
5. The rounded data is registered.
6. The registered data is written to the next instance, RAM. The chain repeats this.

The blocks highlighted in blue contain cells that are lower level cells, whilst the grey boxes
contain cells that are placement drivers.

The cells are floorplanned to force the datapath to zig-zags through the part. The following image
shows the floorplanning:

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 Chapter 5: Using the Dataflow Viewer

Figure 2: Floorplanning

By design, the floorplan is disorganized with cell placement scattered and cells not in their ideal
positions. The ideal placement for this design is to locate the cells next to each other in the
following order:

1. G_total_RAM_MULTS[1].ram_i
2. G_total_RAM_MULTS[1].mult_i
3. G_total_RAM_MULTS[2].ram_i
4. G_total_RAM_MULTS[2].mult_i

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 Chapter 5: Using the Dataflow Viewer

5. G_total_RAM_MULTS[3].ram_i
6. G_total_RAM_MULTS[3].mult_i

And so on upto G_total_RAM_MULTS[10].mult_i.

1. Select some of the modules in the netlist view and explore the connectivity. In particular look
at the connectivity between RAM[n] -> MULT[n] blocks and MULT[n] -> RAM[n+1]. Pay
particular attention to the longer net bundles between two Pblocks further away.
Alternatively, you can also open the Physical Constraints window and select each Pblock.
2. Next, observe the connectivity between two RAMs. In the Netlist window, select the
following 3 cells:
• G_total_RAM_MULTS[1].ram_i
• G_total_RAM_MULTS[1].mult_i
• G_total_RAM_MULTS[2].ram_i

• Next, right click and create a schematic

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 Chapter 5: Using the Dataflow Viewer

• Next, expand the schematic to have the RAM and DSP leaf cells in view in the schematic
and at least one bit of a bus connecting between cells. Allocate a brief amount of time to
this task. If you encounter challenges beyond this timeframe, it is acceptable to
discontinue your efforts. If successful, the results are such:

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 Chapter 5: Using the Dataflow Viewer

To help you get to this point:

1. First expand back into G_total_RAM_MULTS[1].ram_i
2. In the DSP slice click on the following output pins
a. A1DATA
b. A2A1

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 Chapter 5: Using the Dataflow Viewer

c. V
d. V_DATA
e. X
f. ALU_OUT
g. P
3. Only click on D and Q pins of flops. Use the MSB of the bus when clicking through.
4. Click on the O pin of LUTCY1
This takes around 15 clicks to get between the two cells. It is complicated and confusing
as you go through the LOOKAHEAD and the DSP slice. If you find nets looping around,

ask Vivado to redraw the schematic by clicking on the Regenerate icon .

This simple process demonstrates that tracing between cells can be complex in the
standard view. Be informed, this is a simple design. Next step traces the same path in the
Dataflow Viewer.

Step 2: Navigating the Dataflow Viewer

Following are the steps to create Dataflow Viewer.

1. In the Flow menu, select Open Dataflow Design.

2. This creates the Dataflow Netlist and it becomes the active window. The Netlist window
shows the cells from the dataflow design.
3. Next, select the same 3 cells as previously selected in the Netlist window

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 Chapter 5: Using the Dataflow Viewer

4. Right click and generate a schematic. Click on the input pin of the second RAM and to make

the schematic more readable. click on the redraw symbol. The schematic expansion is
significantly faster than tracing through a standard netlist:

When comparing this to the schematic on the previous page, you understand how this
process is quicker:
• Internal cells are not displayed from within the DSP
• Registers are removed
• LUTs are removed
• Only RAMs and DSPs remain
This netlist simplification translates into a faster navigation speed. This comes at the cost of
low level elements within the design no longer being visible.
5. Click on the hierarchy around the DSP slice and observe the Dataflow Hierarchy Browser.
The following should be shown:

The cross probing within the dataflow viewer functions similarly to other windows in Vivado.
Observe that the Dataflow Hierarchy Browser shows the resource utilization of the selected
hierarchies.
6. Next, in the Cell Properties window, click on Statistics. This shows the following window:

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 Chapter 5: Using the Dataflow Viewer

7. Next, expand the Leaf Cells under the level of selected hierarchy. It only has one cell. The
reason for this is that some statistics are taken from the full design.

8. Next step is to look at switching between designs (to distinguish from switching activity for
power analysis). When you open a dataflow design, there are two netlists loaded into
memory, the parent design and the dataflow design. Only one can be viewed at a time. To see
the other, you need to switch designs. With the G_total_RAM_MULTS[1].mult_i hierarchy
level still selected, click on the design switch icon at the top of the screen. This displays
the parent design, and the selected hierarchy from the dataflow netlist is selected to facilitate
cross probing between different designs. In the netlist window, expand the cells and you can
see the registers.
9. Switch back to the dataflow design using the switch icon.

Note: It slightly changes its appearance and looks like .

Step 3: Generating Dataflow Paths

This step explains how to generate dataflow paths. These are objects that contain paths with
multiple cells.

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 Chapter 5: Using the Dataflow Viewer

1. In the dataflow design, click Edit → Find. When the configuration box opens, change the find
type to dataflow paths using the pull down menu.

2. Click OK. This generates the top 100 paths in the design. It starts by identifying paths of
which the depths are at the value of the -max_depth value, which defaults to 10. Depth can
also be referred to as hops as each cell within the dataflow path is considered a hop. It
returns a dataflow paths window that looks like the following:

3. From the Tcl Console, you can find the syntax used to generate the dataflow paths.
show_objects -name find_1 [get_dataflow_paths -filter \
{ STARTPOINT_REF_NAME =~ "*" } ]

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 Chapter 5: Using the Dataflow Viewer

This is important as in the current version of Vivado the GUI options to generate dataflow
paths are limited. It does not give access to the -to/-from/-through or any of the other
options. Using the Tcl Console, passing the return of the dataflow paths command to the
show_objects command allows you to display paths in the GUI.
4. Now generate a more specific command. You can use the following as your base command:
show_objects -name find_1 [get_dataflow_paths ]

• Add a -from cell object: G_total_RAM_MULTS[1].mult_i/mult_out_reg

• Add a -to cell object: G_total_RAM_MULTS[6].ram_i/ram_name_reg_bram_0
Note: This command only works with leaf cells. You should not use hierarchical cells.

Once finished, you should have a window returned that looks like the following:

The -from, -through and -to can each take a list of cells. You can use the get_cells
command to generate a list of cells and use it as an input for this command.
5. Select the returned path. Next, open the Device window if it is not already open. When the
parent design is placed, placement of the cells in the dataflow netlist is imported and can be
observed in the device view when a dataflow path is selected. In addition, you can also see
the direction of the path between the source and the destination as shown in the following
figure:

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 Chapter 5: Using the Dataflow Viewer

6. Next, right click on the dataflow path and select Mark. This shows that the path between the
source and the destination is a brief step. This design routes around before going between
the two locations. This exclusively displays the beginning and ending points of the route.
7. For this simple design, the following technique works best. Type the following at the Tcl
Console and then select all the returned paths
show_objects [get_dataflow_paths -max_depth 1]

This command returns all paths of length 1 in the design. As the design is small, it is effective
in showing the dataflow from cell to cell through the design.

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 Chapter 5: Using the Dataflow Viewer

To achieve the same thing on a more complex design, you need to source a Tcl script. In the
Lab file directory source the dfv_tutorial.tcl file. This sets up the DFV namespace. You
can then type the following command:
set start_cell [get_cells G_total_RAM_MULTS[1].ram_i/ram_name_reg_bram_0]
::dfv::trace_individual_paths $start_cell 20

8. There are also some other useful switches on the get_dataflow_paths command. For example
you can look at paths between different macros such as RAMs – DSPs. There are two ways to
do this. One way is to look at specific REF_NAMEs and the other is to use the get_cells
command and filter by the types that you are interested in.
In this design, all the RAMs cells have a REF_NAME RAMB18E5_INT. All the DSPs have a
REF_NAME DSP58. The command is therefore:
show_objects [get_dataflow_paths -start_ref_name RAMB18E5_INT \
-end_ref_name DSP58 -max_depth 1]

9. Select all the returned paths. It should produce a device view that looks as the following:

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 Chapter 5: Using the Dataflow Viewer

This sort of picture can be symptomatic of a module that has been reused a lot. Sometimes all
cases might not be thought out and there is a stretching of the path. If you can identify a
common module, you can design for the worst case scenario.
10. The second way to do this is more powerful but requires a bit more coding. Here, using the
get_cells command can achieve the same:
set source_rams [get_cells -hier -filter {PRIMITIVE_GROUP==BLOCKRAM}]
set dest_dsps [get_cells -hier -filter {PRIMITIVE_GROUP==ARITHMETIC}]
show_objects [get_dataflow_paths -from $source_rams -to $dest_dsps \
-max_depth 1]

This produces the same result.

Step 4: Floorplanning
This step explains how floorplanning must be done when using the DFV. As this is a different
design, with different objects, and no timing constraints, information must be gathered in DFV
and floorplanning must be done in the parent design.

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 Chapter 5: Using the Dataflow Viewer

1. Run the following Tcl command:

show_objects [set paths [get_dataflow_paths -max_depth 1]]
select_objects $paths

In the device view, you again see the individual paths that you saw earlier. When you
examine these more closely, you observe that some paths are crossing over each other. For
this, you can alleviate the problem by updating the floorplan. The goal is to move all the items
in the red box to where the green box is:

2. In this design, there is a chain and the indices of the cells increase. Identify the first cell name
in the red box and the last cell name and fill in the blanks. Zoom in within the device view and
select the first cell in the chain in the red box. You should find it is the cell with the following
name G_total_RAM_MULTS[3].mult_i/mult_out_reg. Repeat the process and select
the final cell in the chain:G_total_RAM_MULTS[9].ram_i/ram_name_reg_bram_0.

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 Chapter 5: Using the Dataflow Viewer

3. From the above, you can conclude that you need to floorplan the following cells:

DSPs:
G_total_RAM_MULTS[3].mult_i/mult_out_reg
..
G_total_RAM_MULTS[8].mult_i/mult_out_reg
RAMs:
G_total_RAM_MULTS[4].ram_i/ram_name_reg_bram_0
..
G_total_RAM_MULTS[9].ram_i/ram_name_reg_bram_0

4. You can create a single path using the following syntax, then select the path and filter it so
that only cells are selected
set path [get_dataflow_paths -max_depth 11 \
-from [get_cells G_total_RAM_MULTS[3].mult_i/mult_out_reg] \
-to [get_cells G_total_RAM_MULTS[9].ram_i/ram_name_reg_bram_0]]
show_objects -name single $path
select_objects $path
select_objects [set cells [filter [get_selected_objects] {CLASS==cell}] ]
puts "[join $cells \n]"

The resulting output should print out the cell names that are in the path. These are also
stored in the cells variable:
G_total_RAM_MULTS[3].mult_i/mult_out_reg
G_total_RAM_MULTS[4].ram_i/ram_name_reg_bram_0
G_total_RAM_MULTS[4].mult_i/mult_out_reg
G_total_RAM_MULTS[5].ram_i/ram_name_reg_bram_0
G_total_RAM_MULTS[5].mult_i/mult_out_reg
G_total_RAM_MULTS[6].ram_i/ram_name_reg_bram_0
G_total_RAM_MULTS[6].mult_i/mult_out_reg
G_total_RAM_MULTS[7].ram_i/ram_name_reg_bram_0
G_total_RAM_MULTS[7].mult_i/mult_out_reg
G_total_RAM_MULTS[8].ram_i/ram_name_reg_bram_0
G_total_RAM_MULTS[8].mult_i/mult_out_reg
G_total_RAM_MULTS[9].ram_i/ram_name_reg_bram_0

5. Once you have the cell names, switch designs using the switch icon at the top of the screen.
At the Tcl Console, prove that the variable still exists after switching designs by typing the
following command:
puts “$cells”

6. Next, you have to delete the existing Pblocks in the design. Open the physical constraints
window and delete the Pblocks associated with the above cells. The name is not the same
but similar enough to figure out. You should have a list like the following before deleting
them:

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 Chapter 5: Using the Dataflow Viewer

Once you select these, right click on one and select delete.
7. Next, you need to create a new Pblock with your cells. Use the following syntax to select the
cells: select_objects $cells. Next, with the objects selected, open the Netlist window
and on a selected cell, right click Draw Pblock. Ensure that Assign Selected Cells is checked
and draw a Pblock anywhere in the approximate area. Click through any boxes that pop up.
8. At this point the Pblock is created but not saved. You can either save the constraints or you
can go into the Tcl console and copy the text output and manually add this to your design
constraints.

Step 5: Correlating Long Congestion with

Dataflow Daths
Long congestion is the congestion of only the longer routes in the device which are fewer in
number to the shorter routes. It is typically caused by two reasons:

1. Transporting data buses from one point to another in a device. This is caused by placement of
cells driving or receiving data buses being far away from each other.

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 Chapter 5: Using the Dataflow Viewer

2. Areas of imbalanced cell type resource forcing local modules to be spread. This can force
smaller contained modules to spread and end up using long routes.

This section focuses on long congestion caused by data path placement. When you have long
congestion, the tool switches to shorter routes and consequently it traverses through more
switchboxes. It is a slow process, hence a process to avoid when you have the following
scenarios:

• Timing failures going through long congested areas

• Short congestion overlapping with long congestion

On a design with congestion, when you run report_design_analysis, it displays congested

areas and gives a profile of the cells within the congested area. For short congestion, analysis is
typically contained within the congested area. However, for long congestion, relevant paths not
only start and end within the congested area but might also begin outside it or end outside it.

In this step, you must identify paths within an area, filter them based on direction and length and
finally expand the paths to get a more holistic view of the path.

Note:

The following is to illustrate how to get the congested tiles in a normal design. The tutorial design does not
exhibit congestion.

When you run report design analysis, you are presented with a picture of the following

From this picture you can right click Select tiles and this selects all the tiles.

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 Chapter 5: Using the Dataflow Viewer

From here you can assign to a variable and switch to the dataflow design.

set congested_tiles [get_selected_objects]

1. It is at this point where you resume working on the tutorial design. Run the following
command to set up a congested_tiles variable. This assumes that you have long
congestion in the south direction within these clock regions:
set clk_regions [get_clock_regions [list X1Y3 X2Y3 X3Y3 X4Y3]]
set congested_region [get_tiles -of $clk_regions]
highlight_objects -color cyan $congested_region

This command assigns tiles to the congested_tiles variable and highlight all the tiles. You
should see the following:

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 Chapter 5: Using the Dataflow Viewer

2. Next highlight the paths like you did previously using the following command
set start_cell [get_cells G_total_RAM_MULTS[1].ram_i/ram_name_reg_bram_0]
::dfv::trace_individual_paths $start_cell 20

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 Chapter 5: Using the Dataflow Viewer

You can identify the following paths. Then within the paths, you can see the marked the
paths that you are interested in.

These paths have the following trait

• They can travel through the congested areas.

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 Chapter 5: Using the Dataflow Viewer

• They can travel southwards some distance that is at least one long line in length.

1. Next, identify the single hop dataflow paths that pass through the congested area that you
highlighted previously. The -through, -from and -to switches of the get_dataflow_paths
command only accepts cell objects. Hence, you need to identify the start and end cells.
To identify the cells, firstly, you must identify the areas around the congested region that
could have a start cell and an end cell. Once you have the areas, you can use Tcl to extract
the cell information and generate some paths.
Working on a clock region basis is the most convenient approach. Clock regions are defined
around the congested area, determining the potential locations of the start cells and end cells
of your dataflow path.
Run the following Tcl command:
set direction south
set src_dest_clock_regions [::dfv::find_congested_clock_regions \
$direction $congested_region 0]

This command returns a list of two elements. The first element is a list of clock regions that
represents where you look for the startpoint cell locations, and the second is a list of clock
regions where you look for endpoint cell locations. In the above command, you have
specified that the expansion is 0. This is observed at the following regions:

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 Chapter 5: Using the Dataflow Viewer

2. With this approach, some path‘s startpoints fall outside the Start Area and some endpoints
fall outside the End Area. To capture these, you have to increase the expansion window. Run
the following command, this expands the start and end areas by 1 clock region around the
outside of each area:
set src_dest_clock_regions [::dfv::find_congested_clock_regions \
$direction $congested_region 1]

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 Chapter 5: Using the Dataflow Viewer

This larger area now captures everything you are interested in.
3. Next, run the following command. It does the following:
::dfv::get_all_paths_in_region $src_dest_clock_regions $direction 2 \
$congested_region

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 Chapter 5: Using the Dataflow Viewer

a. Capture all the paths that start and end in the two areas
b. Filter out paths that are less than one long line in south direction
c. Filter out paths that are going in the wrong direction
d. Filter out paths that do not pass through the congestion window
::dfv::get_all_paths_in_region $src_dest_clock_regions $direction 2 \
$congested_region

In addition to filtering out paths that you are not interested in, it takes a given path and
expand it by two hops from the start and destination to provide you with a datapath that
allows you to take a more holistic approach to floorplanning.
4. Select all the paths that are returned. It should look like the following:

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 Chapter 5: Using the Dataflow Viewer

5. The expansion of the paths is two hops at each end. You have:
hop1 → hop2 → congestion path → hop3 → hop4
This is a challenge to correlate. So for the first path, examine the start point cell. Run the
individual path on this cell by running the following command:
set start_cell [get_cells G_total_RAM_MULTS[2].mult_i/mult_out_reg]
::dfv::trace_individual_paths $start_cell 5

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 Chapter 5: Using the Dataflow Viewer

Select the paths that are returned. It shows that this passes through the congested region:

6. Try repeating this analysis for the other paths and confirm that they pass through the
congested region.
7. The next point is to extract the cells that would make up something that could be put in to a
floorplan. Select all the five paths that were returned from the original congestion path.

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 Chapter 5: Using the Dataflow Viewer

Then type the following Tcl:

set cells_to_floorplan [filter [get_sel] {CLASS==cell}]

At the end, you have a variable that contains all the cells that you are interested in. It is
possible to follow some steps in the previous section to floorplan these cells to a new
location.

Summary
In this tutorial, you have:

• Created a dataflow design

• Explored a dataflow design using GUI options, including switching to parent designs and back
leveraging cross probing.
• Created dataflow paths to enable targeted analysis
• Floorplanned cells identified in that dataflow design
• Identified long congestion paths

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 Appendix A: Additional Resources and Legal Notices

Appendix A

Additional Resources and Legal

Notices

Finding Additional Documentation

Technical Information Portal

The AMD Technical Information Portal is an online tool that provides robust search and
navigation for documentation using your web browser. To access the Technical Information
Portal, go to https://docs.amd.com.

Documentation Navigator

Documentation Navigator (DocNav) is an installed tool that provides access to AMD Adaptive
Computing documents, videos, and support resources, which you can filter and search to find
information. To open DocNav:

• From the AMD Vivado™ IDE, select Help → Documentation and Tutorials.
• On Windows, click the Start button and select Xilinx Design Tools → DocNav.
• At the Linux command prompt, enter docnav.

Note: For more information on DocNav, refer to the Documentation Navigator User Guide (UG968).

Design Hubs

AMD Design Hubs provide links to documentation organized by design tasks and other topics,
which you can use to learn key concepts and address frequently asked questions. To access the
Design Hubs:

• In DocNav, click the Design Hubs View tab.

• Go to the Design Hubs web page.

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 Appendix A: Additional Resources and Legal Notices

Support Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Support.

Revision History
The following table shows the revision history for this document.

Section Revision Summary

06/12/2024 Version 2024.1
Chapter 5: Using the Dataflow Viewer Added chapter.

Please Read: Important Legal Notices

The information presented in this document is for informational purposes only and may contain
technical inaccuracies, omissions, and typographical errors. The information contained herein is
subject to change and may be rendered inaccurate for many reasons, including but not limited to
product and roadmap changes, component and motherboard version changes, new model and/or
product releases, product differences between differing manufacturers, software changes, BIOS
flashes, firmware upgrades, or the like. Any computer system has risks of security vulnerabilities
that cannot be completely prevented or mitigated. AMD assumes no obligation to update or
otherwise correct or revise this information. However, AMD reserves the right to revise this
information and to make changes from time to time to the content hereof without obligation of
AMD to notify any person of such revisions or changes. THIS INFORMATION IS PROVIDED "AS
IS." AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE
CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES,
ERRORS, OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY
DISCLAIMS ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, OR
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 Appendix A: Additional Resources and Legal Notices

AUTOMOTIVE APPLICATIONS DISCLAIMER

AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT

WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS
THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A
SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262
AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING
OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST
SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION
WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO
APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT
LIABILITY.

Copyright

© Copyright 2012-2024 Advanced Micro Devices, Inc. AMD, the AMD Arrow logo, Kintex,
UltraScale, UltraScale+, Versal, Vivado, and combinations thereof are trademarks of Advanced
Micro Devices, Inc. Other product names used in this publication are for identification purposes
only and may be trademarks of their respective companies.

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