ECE 545 Required reading

Lecture 5
• P. Chu, RTL Hardware Design using VHDL

Chapter 4, Concurrent Signal Assignment

Dataflow Modeling Statements of VHDL
in VHDL Chapter 6.3, Realization of VHDL Data Types

George Mason University 2

Types of VHDL Description Synthesizable VHDL

VHDL Descriptions
Dataflow VHDL VHDL code
• Testbenches Description synthesizable
behavioral
dataflow structural
(sequential)
Concurrent Components and Sequential statements Dataflow VHDL VHDL code
statements interconnects • Registers
• State machines
Description synthesizable
• Instruction decoders

Subset most suitable for synthesis

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Register Transfer Level (RTL) Design Description Data-Flow VHDL

Today s Topic Concurrent Statements
• simple concurrent signal assignment
(Ü)

Combinational
Logic
Combinational … • conditional concurrent signal assignment
Logic
(when-else)

• selected concurrent signal assignment

(with-select-when)
Registers

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Simple concurrent signal assignment Conditional concurrent signal assignment

<= When - Else

target_signal <= expression;
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

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Selected concurrent signal assignment Data-Flow VHDL

Concurrent Statements
• simple concurrent signal assignment
With –Select-When (Ü)
with choice_expression select
target_signal <= expression1 when choices_1, • conditional concurrent signal assignment
expression2 when choices_2, (when-else)
. . .
expressionN when choices_N;
• selected concurrent signal assignment
(with-select-when)

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Signals
SIGNAL a : STD_LOGIC;

a
1 wire
Wires and Buses
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

b
8 bus

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Merging wires and buses Merging wires and buses
a a
4 4
10 10
b 5 b 5
d = a || b || c d = a || b || c
c c

SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC; SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);

d <= d <= a & b & c;

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Splitting buses Splitting buses

a = d .. a = d9..6
4 4
10 10
d 5 b = d .. d 5 b = d5..1

c=d c = d0
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC; SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);

a <= a <= d(9 downto 6);

b <= b <= d(5 downto 1);
c <= c <= d(0);

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Data-flow VHDL: Example Data-flow VHDL: Example (1)

x LIBRARY ieee ;
y USE ieee.std_logic_1164.all ;
s
cin
ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;
cout cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC ) ;
END fulladd ;

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 Data-flow VHDL: Example (2) Logic Operators
ARCHITECTURE dataflow OF fulladd IS • Logic operators
BEGIN
s <= x XOR y XOR cin ; and or nand nor xor not xnor
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END dataflow ;
equivalent to • Logic operators precedence in VHDL-93
and later
Highest
ARCHITECTURE dataflow OF fulladd IS not
BEGIN and or nand nor xor xnor
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; Lowest
s <= x XOR y XOR cin ;
END dataflow ;

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No Implied Precedence
arith_result <= a + b + c – 1;
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d

Correct
y <= (a and b) or (c and d) ;
RTL Hardware Design Chapter 4 22
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Signal assignment statement with a Data-Flow VHDL

closed feedback loop Concurrent Statements
• a signal appears in both sides of a • simple concurrent signal assignment
concurrent assignment statement (Ü)
• E.g.,
q <= ((not q) and (not en)) or (d and en); • conditional concurrent signal assignment
(when-else)
• Syntactically correct
• Form a closed feedback loop • selected concurrent signal assignment
• Should be avoided (with-select-when)

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Conditional concurrent signal assignment Most often implied structure

When - Else
target_signal <= value1 when condition1 else
When - Else value2 when condition2 else
. . .
target_signal <= value1 when condition1 else
valueN-1 when conditionN-1 else
value2 when condition2 else
valueN;
. . .
valueN-1 when conditionN-1 else
F
valueN; Value N
.… … F
T
Value N-1 T F
Target Signal
T
Value 2
Value 1
Condition N-1

Condition 2
Condition 1

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2-to-1 abstract mux

• sel has a data type of boolean
• If sel is true, the input from T port is connected
to output.
• If sel is false, the input from F port is
connected to output.

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 • E.g., Signed and Unsigned Types

Behave exactly like

STD_LOGIC_VECTOR
plus, they determine whether a given vector
should be treated as a signed or unsigned number.
Require
USE ieee.numeric_std.all;

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Operators Priority of logic and relational operators

• Relational operators compare a = bc

= /= < <= > >=
Incorrect
… when a = b and c else …
equivalent to
• Logic and relational operators precedence
… when (a = b) and c else …
Highest not
= /= < <= > >=
and or nand nor xor xnor Correct
Lowest
… when a = (b and c) else …

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Data-Flow VHDL Selected concurrent signal assignment

Concurrent Statements
• simple concurrent signal assignment
(Ü) With –Select-When
with choice_expression select
• conditional concurrent signal assignment target_signal <= expression1 when choices_1,
(when-else) expression2 when choices_2,
. . .
expressionN when choices_N;
• selected concurrent signal assignment
(with-select-when)

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Most Often Implied Structure Allowed formats of choices_k
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
WHEN value
expression2 when choices_2,
. . .
expressionN when choices_N; WHEN value_1 | value_2 | .... | value N

expression1 choices_1
expression2 choices_2
WHEN OTHERS
target_signal

expressionN choices_N

choice expression

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Allowed formats of choice_k - example

Syntax
• Simplified syntax:
WITH sel SELECT with select_expression select
y <= a WHEN "000", signal_name <=
c WHEN "001" | "111", value_expr_1 when choice_1,
d WHEN OTHERS; value_expr_2 when choice_2,
value_expr_3 when choice_3,
...
value_expr_n when choice_n;

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• select_expression E.g., 4-to-1 mux

– Discrete type or 1-D array
– With finite possible values
• choice_i
– A value of the data type
• Choices must be
– mutually exclusive
– all inclusive
– others can be used as last choice_i

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 E.g., 2-to-22 binary decoder
• Can 11 be used to replace others?

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E.g., simple ALU E.g., Truth table

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Conceptual implementation
– select_expression is with a data type of 5
• Achieved by a values: c0, c1, c2, c3, c4
multiplexing circuit
• Abstract (k+1)-to-1
multiplexer
– sel is with a data type
of (k+1) values:
c0, c1, c2, . . . , ck

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 • E.g.,

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3. Conditional vs. selected signal From selected assignment to

assignment conditional assignment
• Conversion between conditional vs.
selected signal assignment
• Comparison

RTL Hardware Design Chapter 4 51 RTL Hardware Design Chapter 4 52

From conditional assignment to

Comparison
selected assignment
• Selected signal assignment:
– good match for a circuit described by a
functional table
– E.g., binary decoder, multiplexer
– Less effective when an input pattern is given
a preferential treatment

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 – May over-specify for a functional table
based circuit.
• Conditional signal assignment:
– E.g., mux
– good match for a circuit that needs to give
preferential treatment for certain conditions or
to prioritize the operations
– E.g., priority encoder
– Can handle complicated conditions. e.g.,

RTL Hardware Design Chapter 4 55 RTL Hardware Design Chapter 4 56

when-else vs. with-select-when (1) when-else vs. with-select-when (2)

"when-else" should be used when: "with-select-when" should be used when there is

1) there is only one condition (and thus, only one 1) more than one condition
else), as in the 2-to-1 MUX 2) conditions are closely related to each other
2) conditions are independent of each other (e.g., (e.g., represent different ranges of values of the
they test values of different signals) same signal)
3) conditions reflect priority (as in priority 3) all conditions have the same priority (as in the
encoder); one with the highest priority need to 4-to-1 MUX).
be tested first.

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Use of ‘-’ – ‘-’ as output value: help simplification

– E.g.,
• In conventional logic design
‘-’ assigned to 1: a + b
– ‘-’ as input value: shorthand to make table compact ‘-’ assigned to 0: a’b + ab’
– E.g.,

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 • Fix #1:
Use ‘-’ in VHDL 2
2 1
• As input value (against our intuition): 2 0

• Wrong:
• Fix #2:

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• Wrong:
• ‘-’ as an output value in VHDL
• May work with some software

• Fix:

RTL Hardware Design Chapter 6 63 RTL Hardware Design Chapter 6 64

• Major application:
Use and synthesis of ‘Z’ – Bi-directional I/O pins
• Tri-state buffer: – Tri-state bus
– Output with “high-impedance” • VHDL description:
– Not a value in Boolean algebra y <= 'Z' when oe='1' else
– Need special output circuitry (tri-state buffer) a_in;
• ‘Z’ cannot be used as input or manipulated
f <= 'Z' and a;
y <= data_a when in_bus='Z' else
data_b;

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• Separate tri-state buffer from regular code:
– Less clear:
Bi-directional i/o pins
with sel select
y <= 'Z' when "00",
'1' when "01"|"11",
'0' when others;
– better:
with sel select
tmp <= '1' when "01"|"11",
'0' when others;
y <= 'Z' when sel="00" else
tmp;
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Tri-state bus

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• Problem with tri-state bus
– Difficult to optimize, verify and test
– Somewhat difficult to design: “parking”,
“fighting”
• Alternative to tri-state bus: mux

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