Microelectronics Failure Analysis: Desk Reference Fifth Edition Copyright © 2004 ASM International®

The Electronic Device Failure Society Desk Reference Committee, editor, p89-109 All rights reserved.
DOI: 10.1361/mfad2004p089 www.asminternational.org
Electronics and Failure Analysis
Jerry Soden, Jaume Segura†, and Charles F. Hawkins††

Sandia National Labs, Albuquerque, New Mexico USA

†
University of Balearic Islands, Spain
††
University of New Mexico
Albuquerque, New Mexico USA
[email protected]

1. Introduction
Root cause corrective action requires localization of the
Five years ago, we described our knowledge of CMOS IC
failure mechanism and electrical characterization of the
defects, and how they manifested as electronic failures.
circuit failure mode. Therefore, we need a reflexive
The emphasis was on bridge and open defects with a short
knowledge of how CMOS elements respond to defects.
description of parametric failures. Now, with technology
Often circuit depth is lacking so this paper also targets
scaling entering the nanometer regime, parametric failures
failure analysts who need electronic knowledge, but who
are a major concern often presenting difficult detection
may have degree backgrounds in physics, chemistry,
and fail site location. We have thus expanded the section
chemical engineering, materials science, or biology. It
on parametric failures showing the reasons for their
cannot replace a course in electronics, but it puts that
increased significance in advanced process technologies,
knowledge in perspective and provides direction.
and the failure analysis tools available to face the
problem. This article reviews normal transistor operation and then
relates it to electronic behavior in the presence of defects,
In the previous edition of the Microelectronics Desk
such as bridges and opens. These electronic principles are
Reference, we introduced the basic operation of the
then applied to an inexpensive CMOS failure analysis
MOSFET transistor using model equations from long
technique using a power supply signature analysis.
channel transistors. We repeat that work, but expand a
section on short channel transistor modeling, and the 2. MOSFET Operation and Three Bias States
difficulties in its manual problem solving. Our
Figure 1 shows an n-channel transistor cross-section with
descriptions emphasize this manual approach with its
heavily n+ doped drain and source regions and a p-well.
accompanying quick insights into transistor circuit
When the gate voltage (VG) is zero and the source and
behavior.
drain are grounded, only a few thermally generated free
Electronics spans a number of devices, their carriers exist in the p-well and the transistor is in the off-
configurations, and properties. A challenge is to identify state. Effectively, no drain current exists even when a
those electronic subjects essential for failure analysis. voltage is across the drain-source.
Transistor circuits with and without resistors are one
gate
object of our study. A theme is that failure analysts deal (polysilicon) gate
with relatively simple circuits, but go deep in oxide
understanding their operation. Logic circuits must be
source drain
understood, but when a defective circuit gives the final
electronic clues to a defect, they are typically analog. An p-type
bulk
expanded treatment of all these topics can be found in
reference [1]. Fig. 1. n-channel transistor cross section.
When VG is much larger than the drain (VD) source (VS), 2b) and to the right of Lp is the pinchoff or depletion
and bulk (VB) voltages, then electrons (minority carriers) region. The existence of a pinchoff region puts the
from the p-well are attracted to the thin oxide interface transistor in the saturated bias state. A high electric field
(hatched area, Fig. 2a). This second important bias state, exists between LP and the drain with fixed positive
called the non-saturated state, exists when a continuous charges in the drain and fixed negative charges in the
electron inversion region connects the source and drain. substrate (p-well).
The non-saturated state is also called the ohmic or linear Surprisingly, the reverse biased drain-substrate pn
state. If the drain has a positive voltage, then the inverted junction does not prevent charge flow. Many inverted
free electrons drift due to the electric field forming drain electrons in Fig. 2b are caught in the high electric
current. VGS (gate to source voltage) has a minimum value depletion field and accelerated toward the drain. These
necessary to sustain minority carrier inversion and that electrons exit the drain terminal from the high impedance
VGS is defined as the gate threshold voltage Vt. The non- of a reverse biased pn junction.
saturated and off-states exist in CMOS logic circuits when
p-channel transistors use gate voltages that are negative
the clock pulse is off, and all voltages have settled to their
with respect to the source and bulk to generate minority
quiescent values.
carrier (holes) inversion in an n-well. The negative gate
voltage draws holes from the n-well to the thin oxide
G
surface if the gate voltage is greater than the threshold
S D voltage. The n- and p-channel transistors have opposite
terminal polarities for normal operation. The terminology
B and polarity conventions of both transistors are important.
Fig. 2a. Carrier inversion in non-saturated bias state. Failure Analysis and Bias State: Mobile electrons (or
holes) that are accelerated across the saturated state
depletion region cause impact ionization and photon
The saturated state occurs when VD approaches VG. If the
emission that are readily seen in the drain region by
drain voltage in Fig. 2a is increased, then the difference
photoemission microscopy [2]. Normal transistors are in
between VG and VD diminishes in the oxide region near the
the saturated state during most of their logic state
drain. At some point, the local gate to drain voltage
transition (shown later) and emit photons. Transistors in
across the oxide drops below Vt and no inverted carriers
the quiescent portion of the logic cycle are either in the
can exist in this local channel region. Since the n+-doped
nonsaturated-state or off-state so that no photons are
drain has a positive voltage with respect to the p-well, a
emitted. However, bridge and open defects may hold one
reversed bias pn junction exists here between the drain
or more transistors in the saturated state where the
and p-well. Fig. 2b shows this state when VGS > Vt, but
presence of a light emitting transistor indicates proximity
VD > VG - Vt
of a defect. The defect may be a bridge external to the
G transistor that sets up a saturated state bias states. Or IC
defects may lie in the transistor itself. Examples include
S D
gate shorts, soft pn junctions, or an open circuit on one of
the terminals.
B
Review: MOSFETs have three bias or operating states;
Fig. 2b. Carrier inversion in saturated bias state
off, saturated, and non-saturated (or ohmic). CMOS ICs
use all three states. The off and non-saturated states exist
The location where the drain to p-well pn junction touches
when logic gates are in their quiescent period. These
the inversion layer is called the pinchoff point (LP in Fig.
states set the high and low logic voltage levels through the of the correct bias state, we cannot pick the proper model
power rails. The saturated state dominates when the (Eq. 1-3).
transistors are switching. This state has analog voltage
gain >> 1, which is beneficial since it shortens the
switching time. The gate and drain voltage difference
determines if a transistor is in the saturated or
nonsaturated state. p- and n-channel transistors have
similar operating mechanisms except the n-channel uses
electrons as carriers, and the p-channel uses holes.

3. MOSFET Terminal Characteristics

MOSFETs have four terminals: gate, drain, source, and
substrate (or bulk) (Fig. 1). The terminal current and
voltage relations are well defined. Although these
VDS (V)
equations are a bit clumsy, they must be learned (Table 1).
Eq. (1) relates ID to VGS when the transistor is in the Fig. 3. ID versus VDS for a family of VGS curves in an

saturated state. µ is the carrier mobility, ε is the dielectric nMOSFET.

constant of silicon, Tox is gate oxide thickness, W is gate

Eq. (2) is a parabola peaking at the boundary between the
width, and L is gate (channel) length. Eq. (2) relates ID to
VGS and VDS for the nonsaturated state. Eq. (3) states that Table 1. nMOSFET Long Channel Bias State Models.
ID = 0 if VGS < Vt. Eqs. (1) to (3) were developed for "long
State Eq.
channel" transistors that may be approximated for L ≥ 0.5
um. Models for short channel devices (L ≤ 0.5 um) are Saturated ID = µε W (VGS – Vt)2 (1)

more complex to account for electric field and charge 2Tox L

interactions at the smaller dimensions. However, we still
use Eq. (1) and (2) in modern failure analysis since the
Non-Saturated
parameters give physical intuition and good estimations
ID = µ ε W [2(VGS – Vt) VDS – VDS2] (2)
without resort to computer calculations. pMOSFETs have
similar equations, but the voltage and current polarities 2Tox L

are negative. Short channel transistor models are

described later. Off-state ID = 0 for VGS < Vt (3)
We can combine Eq. (1) and (2) to model the terminal
characteristics over a range of gate and drain voltages. saturated and non-saturated regions. The left hand side of
Figure 3 shows a typical ID versus VDS family of curves the parabola is the true operating region of a transistor in
measured on a 0.18 um n-channel transistor. Each curve the non-saturation state while the right hand side is a non-
merges half of a parabola (non-saturated region) with a defined state, and values here are ignored. The bias
flat portion (saturated region). Eq. (2) applies to the condition at the boundary is found by differentiating ID
parabola and Eq. (1) to the flat line. A pinchoff point with respect to VDS in Eq. (2), setting the result to zero,
exists at the intersection of the two curves and exists for and solving for VGS. We then get Eq. (4a) that defines the
each saturated, flat line. We need the relation that defines voltage conditions that put the transistor at the boundary
the boundary of these two bias states. Without knowledge of the two states.
 VGS = VDS + Vt (4a)
Example (Fig. 5): Calculate ID, IS, VDS, and power

The most common use of Eq. (4a) is to define saturated dissipated by the circuit (PDD) and transistor (PT) if Vt = 0.4

and non-saturated states by V, VIN = 1.0 V, and the conduction constant

Saturated State: VGS < VDS + Vt (4b) K’ = µ ε W = 60 µA/V2

2Tox L
Non-Saturated State: VGS > VDS + Vt (4c)
Solution: We don’t know which bias state exists so we
will try the saturated state Eq. (1) and see if the solution is
Bias State Examples: Three transistors are shown in Fig.
consistent with Eq. 4b.
4a-c with terminal voltages. An exercise is to use Eq. (4)
and give the correct bias state. ID = K’[VGS – Vt]2

= 60 µA [1 – 0.4 ]2 = 21.6 µA
2.5 V 0.5 V 0.5 V
V2
1.9 V 2.2 V 0.9 V
Then from Kirchhoff’s Voltage Law,

- 2.3 V -2.5 V VDD = IDRD + VDS (5)

(a) (b) (c) VDS = 3 - (21.6 µA) (20 kΩ) = 2.57 V

Fig. 4a-c. Transistor bias examples. (Vt = 0.4 V) from Eq. (4b), VGS < VDS + Vt

1.0 < 2.57 + 0.4

The transistor is in saturation so the first guess was correct

Fig. 4a is in the saturated state since VGS = 1.9 < 2.5 + 0.4.
and IS = ID = 21.6 uA. The power to the circuit is PDD =
Fig. 4b is in non-saturated state since VGS = (0 – (-2.5)) > (-
VDD·IDD = (3 V) (21.6 µA) = 64.8 µW. The transistor
1.0 – (-2.5)) + 0.4. Fig. 4c lies on the boundary of the
power is PT = VDS·ID = (2.57 V) (21.6 uA) = 55.5 µW.
saturated and non-saturated states, therefore Eq. (1) or (2)
may be used. What if the transistor was in the non-saturated state? We
repeat the procedure assuming that the transistor is in
saturation. Set VGS = 2.5 V and use
Analysis of a Complete Circuit
ID = K’[VGS – Vt]2
Transistors don’t operate in isolation. They require a
power supply (VDD), ground (VSS), an input signal, and a = 60 µA [2.5 – 0.4 ]2 = 264.6 µA
load. The load can be a resistor (Fig. 5) or another V2
transistor. Eqs. (1-3) allow analysis of node voltages and
VDS = 3 - (264.6 µA) (20 kΩ) = -2.29 V
the drain current (ID).
This is an error since VGS > VDS + VT is not consistent with
5V our initial saturated state assumption. Also, a negative
potential is not possible in this circuit. We then start over
20 kΩ again using the non-saturated Eq. (2). Since Eq. (2) has
two unknowns (ID, VDS), we need another equation.
1.5 V
M1 Kirchhoff’s Voltage Law states that the sum of the voltage
drops in a loop in zero. Therefore,

Fig. 5. nMOSFET 20 kΩ load circuit. VDD = IDRD + VDS

 and ID = [VDD – VDS]/RD (6)

Combine Eq. (6) with Eq. (2) below

ID = K’[2(VGS – Vt) VDS – VDS2] (2)

and solve the quadratic equation for two values VDS = 4.47
V, 0.559 V. The solution is VDS = 0.559 V since 4.47 V
violates our non-saturated state assumption, and it is also
larger than VDD. Eq. 4c is satisfied: 2.5 V > 0.559 V + 0.4
V confirming the non-saturated state assumption. ID is
calculated by either Eq. (6) or (2) above as ID = 122.1 µA. VDS (V)

Short Channel Transistors

When transistor channel length shrunk below about 0.5
µm, and especially to 0.35 µm and smaller, then two
phenomena appeared that changed MOSFET transistor
properties. The first was that field strengths in the
channel became large enough to cause charge carrier
velocity saturation. The second was that the nearness of
the transistor structures caused interactions leading to
modulation of threshold voltage and effective channel
length. The characteristics were altered as shown in Fig. 6
that compares long channel transistor ID versus VDS
characteristics on the top with short channel transistor
Fig. 6. Comparison of ID versus VDS for long channel
characteristics on the bottom. We observe that the
transistor (top) with short channel transistor (bottom),
velocity saturation effect converts the ID relation to VGS
from [1].
from a square law to a linear one. There are equally
spaced current lines as VGS increases in short channel
transistors. In addition, the pinchoff point defining the Naturally, the long channel device modeling equations
boundary between the saturated and ohmic regions occurs (Eq. 1,2) change and become more complex as shown in
at lower VDS values on the short channel transistor than for Table 2. Eq. (7) and (8) describe the short channel
the long channel transistor, and the slope of the saturated transistor saturated and non-saturated drain current
current lines is larger for the short channel transistor. respectively. New parameters are included: Ecrit is the
electric field strength at which velocity saturation occurs,
δ is a charge related constant, and θ1 is a gate bias
mobility constant.
 This is a fact of life. Accuracy is extremely important in
Table 2. MOSFET Short Channel Bias State Models
short channel transistors to model pico-second timing, but
that process is opaque to the designer as detailed models
State Eq. and parameters are fed to the computer. These limitations
ID = led us to conclude that the long channel transistor

 2
VDsat  relations (Eq. 1-2) are the only ones that allow reasonable,
 (V − V )V − (1 + δ ) (7) fast manual analysis. They teach us the intuition
W  GS t Dsat
2 
µ0 Cox ×
L eff   necessary to understand saturated and non-saturated
[1 + θ1 (VGS − Vt )]1 + L E 
VDsat
 eff crit 
states, the effect of loads, and insights needed to
understand logic circuits, such as the simple inverter,
[1 + λ (V DS − VDsat )]
NAND and NOR gates, and transmission gates.

Non-Saturated 4. CMOS Inverter

The smallest CMOS logic gate is the inverter having one
ID = n- and one p-channel transistor (Fig. 6a). The transfer

 V2  curves in Fig. 6b illustrate the complementary action of

(VGS − Vt )VDS − DS (1 + δ ) the two transistors. When VIN = 0 V, the n-channel is off
W   2  (8)
µ0Cox and the p-channel with 1 V across the source to gate is
Leff  V 
[1+ θ1(VGS − Vt )]1 + L DSE  driven hard into its non-saturated state. It is a low
 eff crit
resistance switch so VOUT = 1 V (logic high). As VIN rises,
the n-channel will turn on at VIN = Vtn going from off to
Off-state ID = 0 for VGS < Vt (9) the saturated bias state. The gate voltage is above
threshold, but much less than the drain voltage. The p-
channel is in its non-saturated state and drain current is
Simplified Saturated
drawn through both transistors (dotted line). As VIN rises,
the drive voltage to the pMOSFET gate (VSG) drops, and
I D ≈ WC ox (VGS − Vt ) µΕ crit (10)
the pMOSFET current drive strength weakens. Near the
midpoint, a maximum current exists that recedes as VIN
rises, and the p-channel drive strength diminishes. When
(VDD – VIN) < -Vtp, the p-channel is off, IDD and VOUT are
A simpler relation exists for the short channel saturated zero (logic low), and the n-MOSFET is driven hard into
region. If we assume that the (Leff Ecrit) term is small, then non-saturation. The point on the curve where VOUT = VIN
we get Eq. (10). This simplification shows the linear is called the logic threshold voltage VTL. The logic state
relation between ID to (VGS - Vt), the independence of is defined as changed when VIN moves above or below this
channel length, and the influence of channel electric field. point. Figure 6b also shows a transfer curve at VDD = 0.5
This is a popular equation to model short channel V. The slope in transition is steeper, and for this low VDD
transistors, but it is too simplistic to use in manual value, the transient through current is gone.
analysis. The accuracy is poor, and the pinchoff point
defining the boundary between saturation and non-
saturation doesn't match for both bias equations.
Therefore, these equations define short channel models,
but leave us without a back-of-the-envelope technique.
 VDD 5. Test Methods
The electronic response of a defective IC implies
Vin Vout
knowledge of the test stimulus that led to a failure
detection. There are several test methods [1].
1. Functional testing has at least three meanings: (a)
GND
stimulation of the IC in a way that replicates how the
customer will use the part, (b) applying the logic truth
table to the circuit, (c) using the primary inputs pins to
an IC in contrast to using a scan chain test port.
Functional testing cannot replicate customer use. For
example, a 1K SRAM has 21024 possible states. If
these patterns are run at 100 MHz then the test of full
function will take about 10293 years. Complete
functional testing for virtually any IC is numerically
impossible.
2. Stuck-at-fault testing (SAF) uses a test abstraction that
Fig. 6a. Inverter circuit. assumes all failures behave as one of the signal nodes
is clamped to either the power or ground rail. SAF
Fig. 6b. Inverter voltage transfer curves at two VDD values with
patterns apply voltages that represent Boolean logic
voltage and current transfer curve for higher VDD [1].
patterns. A correct response for each pattern is stored
A detailed analysis of the transfer curve using Eq. 1,2 in the tester and then compared with the result
shows that both transistors are in saturation for about the measured on the IC.
middle 50% of the transition. Each transistor is in
3. At-speed testing is the third major voltage-based test
saturation for about 75% of the transition. You can verify
method. The FMAX test applies many functional
this by plotting Eq. 4a overlaid on Fig. 6b for both n-
patterns to the IC and finds the maximum functional
channel (Vtn = 0.8 V) and p-channel (Vtp = -0.8 V)
clock rate. Another test generates delay fault patterns
transistors. The analog voltage gain in the transition
that target either logic gates or signal paths, and
region can be estimated by measuring ∆VOUT / ∆VIN ≈ -
measures the propagation delay.
10-15. Photon emission occurs during all of the transition
4. IDDQ testing measures the power supply current of a
region where one or both transistors emit photons during
CMOS circuit during the quiescent period of the clock
the transition.
cycle. Most defects in CMOS ICs elevate IDDQ above
The power supply current (IDD) and the voltage (VOUT)
its normal value.
shapes should be committed to memory (Fig. 6b).
5. Other test types include I/O pin current and voltage
Defects alter the shape of IDD or VOUT versus VIN. The
levels, set up and hold time measurements,
power supply current IDD is near zero at the quiescent
measurement of power supply current during the
logic states because the drain current is junction leakage
transient period of the clock, and testing at low power
that is in picoamps (pA) for small, single transistors.
supply voltages.
Deep submicron transistors have additional leakage
mechanisms that complicate test and failure analysis [3]. Failure analysts work with ICs that fail one or more of the
tests described above. These assorted tests fall into three
categories: (1) voltage-based tests of logic function at
slow clock rate (scan stuck-at fault testing), (2) at-speed output pin. When failure occurs, one bridge node is
voltage-based testing, (3) parametric tests (IDDQ, pin I/O, correct and the other faulty.
etc.). Modern ICs have parameter variations that can
make test limit setting quite difficult. That issue will be
addressed later, but for now we will assume that these
tests have limits that are easily defined.

6. Electronics Properties of CMOS Bridge and

Open Defects
Fig. 8. Bridge defect across output signal nodes of two
CMOS IC defects have several types with different inverters.
electronic patterns. Defects are classed as bridges, opens,
or parametric delay types [4]. Their properties and
The dominating property of bridge defects is called
response to voltage and current-based testing are
critical resistance [5]. Critical resistance (Rcrit) is the
described.
minimum value above which the circuit functionally
6.1 Bridging Defects
passes. Imagine a 1 GΩ bridge between the output of two
Bridging defects are unintentional shorts between logic gates (Fig. 8). The effect on the signal node voltage
interconnect or power lines. Bridges can be tiny levels is insignificant and if this resistance was reduced to
connections (Fig. 7) or may cover several interconnect 1 MΩ or 10 kΩ, then the effect is still small. We typically
lines. They also occur within the structure of transistors, do not see circuit failures until most bridges get below 2
such as with gate oxide shorts or soft pn junction kΩ. This is surprisingly low, but verified with
breakdowns. Bridges can also occur between metal layers simulations and failure analysis.
stacked on top of each other (vertical shorts).
Figure 9 shows a buffered 2NAND gate in which variable
gate to drain defect resistances (dotted line) were
simulated for the n-channel transistor. Figure 10 shows
the DC transfer curves for several gate-drain bridge
resistances in an n-channel transistor showing that the
circuit is functionally correct above about 1 kΩ ( Rcrit
≈ 1 kΩ). The exact value of Rcrit depends on the relative
current driving power of the pull-up and pull-down
transistors that contend at each end of the bridge. A
stronger current drive transistor dominates a weak one,
Fig. 7. SEM photo of bridge defect between two metal bus and the bridge defect node tied to the weaker transistor
lines. will fail first. Failure is defined as the logic threshold
voltage where the logic state changes. Rcrit goes to zero
when the pull-up and pull-down strengths are equal.
Figure 8 sketches a bridge defect between two logic gates.
The effect of a bridge on functionality depends on bridge
location and its resistance. If the resistance is large (≥ 5
kΩ), then little effect is seen on circuit functionality. A
circuit will fail only when the resistance is sufficiently
small, the nodes of the bridge are driven to opposite logic
states, and the failing signal node can be propagated to an
 VDD

V2
V3

Vin2

Fig. 9. Buffered 2NAND test circuit showing logic response to a

gate-drain defect resistance (dotted line) [4].

Fig. 11. IDDQ response to gate-drain bridge defect (Fig. 9) [4].

Any bridge defect with at least one node tied to a signal

line shows the critical resistance effect. Rail-to-rail
bridges do not, but show a constant IDDQ elevation for all
test vectors. The critical resistance can be calculated for a
given circuit using Eqs. (1-2), but space prevents it being
done here [1].
Gate oxide shorts are defective electrical paths between
the gate material and anything under the thin oxide [6,7].
A gate short is not a zero ohm structure. They can have
Fig. 10. Transfer curves of 2NAND when Rdef across
linear or nonlinear I-V properties. Gate shorts can be
gate to drain terminal is varied (Fig. 9) [1].
severe hard breakdowns, or lightly stressed causing soft
breakdowns. Older technologies had larger transistor gate
Simulations of the effect of bridge resistance on timing capacitance (Cg) driven by larger 5 V power supplies.
showed an effect similar to the static transfer curves. The This led to large energy discharges (0.5 Cg V2) such that
affect on timing was negligible until the bridge defect the oxides ruptured under high stress causing what are
resistance became less than about 1 kΩ [1]. This Rcrit called hard breakdowns. Recent technologies use VDD on
effect explains why many quite dramatic bridge defects do the order of 1 V, and the transistor gate areas are several
not cause circuit failure. It is a reason why voltage-based times less than older generations. Therefore, gate
tests such as, functional, stuck-at, or delay fault are weak capacitive energy discharges are smaller, and failure
in bridge defect detection. The IDDQ test does however analysis labs don’t see the catastrophic gate short as often.
have sensitive detection capability for bridging defects.
The inverter has several forms of hard gate shorts. A
Figure 11 shows mA IDDQ elevation for the circuit shown
connection in the n-channel transistor from an n-doped
in Fig. 9.
gate to an n+drain or n+source creates a parasitic linear
resistor. An n-doped gate to p-well connection creates a
diode that when powered up with positive logic on the
gate forms a parasitic nMOSFET whose gate and drain are
connected. A connection between the source or drain of
the p-channel to their gate also creates a diode. The p-
doped gate to n-well connection creates a diode that forms Detection of softly ruptured ultrathin oxides does not
a parasitic pMOSFET when power is applied. Test appear possible at this time, nor is the reliability status
detection of hard gate shorts is similar to linear bridges. clear. The normal functioning of the transistor with an
Voltage based tests are weak and IDDQ is the only test that ultrathin oxide is not as effected as were the killer
guarantees detection [7]. ruptures of the thicker oxides. The recent ultrathin oxide
Ultrathin oxides in the 15 – 25 Å range show a soft experiments indicate test escapes are likely, but
breakdown in addition to the hard breakdowns of thicker subsequent reliabilities may not be as risky as for
transistor oxides. Soft breakdown in these ultrathin oxides breakdown in older technologies [8-12]. These different
is an irreversible damage to the oxide whose most properties of the transistor oxide demand more studies at
significant effect is the increase in noise of the gate the circuit level to assess the implications of test escapes.
voltage. IDDQ is not elevated for the soft gate-substrate Summary of Bridge Defect Electronics: A bridge defect
ruptures of ultrathin oxides. The noise can show up to four with impedance above critical does not cause functional
orders of magnitude increase after soft breakdown, and failure. It weakens node voltages, elevates IDDQ , worsens
this is the only certain evidence of the irreversible damage noise margins, and is often a reliability risk. The affect on
to ultrathin oxides. Hard oxide breakdowns appear in the propagation delay is negligible until the bridge resistance
advanced technology ultrathin transistor oxides if the gate approaches the critical value. Bridge defects < Rcrit will
is highly stressed, but the soft breakdowns are the object show at least one signal node in error.
of reliability studies.
6.2 Open Defects
Recent studies have turned to the effect of ultrathin gate
Open defects have several forms and their electronic
shorts on IC functionality. This issue is important for
behavior is much more diverse than bridges. Defect
failure analysis. Degraeve, et al., found that uniformly
location and physical dimensions are important open
stressed 2.4 nm gates oxides had a uniform area
variables. Six open defect behavior classes are [1,4]
breakdown [8]. Breakdown over nMOSFET transistor
channels had a high resistance from 105 – 109 Ω, while 1. Transistor with missing gate contact. Fig. 12a shows a
breakdowns over the drain and source had resistances of test structure and its transfer function (Fig. 12b). The

102 – 104 Ω. Since the drain and source gate overlap area circuit is functional, but has a weak high voltage and
was much smaller than the area over the channel, most of an even weaker low voltage. IDDQ is elevated in one
the breakdowns occurred over the channel. By measuring logic state. The capacitive coupling between drain-

breakdowns in 150, 180, and 200 nm transistors, they gate and gate-source forms a capacitive voltage
found that the percentage of gate to drain and source divider. When the drain voltage is sufficiently high,
breakdowns increased as the transistors became smaller. then the divider allows the gate voltage to exceed

The drain and source gate overlap area becomes a larger threshold and the transistor conducts. When the input
fraction of the transistor gate area. The gate to drain or voltage is high, the p-channel shuts off. The n-
source breakdowns were likely to cause hard failure, channel transistor stays on draining charge from the

while the gate to channel breakdown showed no failure load capacitance until VG is no longer above
effects. A 41-stage ring oscillator with seven transistor threshold. Then the output node is a weak logic low
gate ruptures continued to function with a 15% decrease level with a high impedance or floating state as shown

in oscillator frequency. Part of the frequency reduction by the horizontal lines in Fig. 12b.
was due to hot carrier damage during a pre-stress.
Significantly, the ring oscillator did not fail despite having
several gate oxide breakdowns present.
 5V VDD
Interconnect
VIN open
VOUT VIN VfG
VO

GND
Fig. 12a. An open defect (missing contact) at n-MOSFET gate
Fig. 13. An open defect to the logic gate input.
[4].

VOUT (V) IDD 3. Open defect behavior in sequential circuits. Fig. 14

5 VOUT shows a master-slave flip-flop with several possible
1 mA
4 open defect sites. Analysis shows that any of these
IDD

3 1 µA open defects will generally cause behavior consistent

2 with the three classes described above. An open in
1 nA
1 one of the CMOS transmission gate signal lines still

0
1 pA allows functionality as if the gate were a single pass
0 1 2 3 4 5 transistor, but signal strength is degraded. The
VIN (V)
responses of these sequential open defects are either
Fig. 12b. Transfer curves for open gate contact [4]. IDDQ elevation only, functional fail only, or both.

O2
2. An interconnect break affecting both complementary Signal Q
transistors (Fig. 13). This open circuit creates a high O3
impedance or floating node that acquires a steady
Q
state voltage. That voltage is dependent upon local O5
topography, especially parasitic coupling capacitance. O4
O1
The isolated gate can float to either rail potential or
any voltage in between allowing two possible
Fig. 14. Open defects in a sequential circuit.
behavior modes. If it floats to a rail, then that input
node has a stuck-at behavior, and IDDQ is not elevated.
If the floating node acquires an intermediate voltage 4. CMOS Stuck-Open (Memory) Defect. The fifth open
greater than the p- and n-channel transistor thresholds, defect class is peculiar to CMOS and occurs when an
then both transistors are permanently on, IDDQ is open circuit happens in the drain or source of a
elevated, and the output is a weak stuck-at voltage. transistor [13]. This also called the CMOS memory
That form of open is detectable with a stuck-at fault defect. Fig. 15 shows such a defect and its truth table
test or an IDDQ test. response for a 2NAND gate. The first vector (AB =
00) sets the output to a logic high by turning on one p-
channel and turning off both n-channel transistors.
The second vector (AB = 01) drives the output high
through the good p-channel pull-up. The third test
vector (AB = 10) attempts to turn on the defective p-
channel pull-up, but no charge can pass since the
drain has an open circuit defect. The output node
goes into a high impedance state and might be 5. Crack in an interconnect line (Fig. 16). This defect
indeterminate except that the previous logic state was supports circuit functionality, especially for very
a high. The load capacitance holds this high value, narrow cracks [14]. A narrow crack allows electron
and the third test vector is read correctly. The fourth tunneling across the barrier, and ICs with this defect
vector pulls the output node low and the result is type can operate in the hundreds of MHz. They are
dramatic. No error in the truth table occurred for such called tunneling opens. These defects occur more
a flagrant defect! What then is the functionality often in vias and contacts. Cold temperature lowers
problem? FMAX since metal contraction widens the crack and
VDD reduces the tunneling. Conversely, circuits with these
defects run faster at hot temperatures. These unusual
frequency-temperature properties are symptomatic of
an interconnect crack.
C

A CL

A B C
0 0 1
0 1 1
1 0 1
1 1 0 Fig. 16. Metal crack [14].

M M M
1 1 0 Summary of Open Defect Electronics: Six different
1 0 0 behavior patterns were described that are dependent on the
open defect location and size. A comprehensive test for
Fig. 15. Open memory defect in a 2NAND gate and its open defects includes both voltage and current-based
truth table. tests. Inattention to these details can frustrate failure
The defect is detected when the sequence of vectors is analysis.
changed. If AB = 11 is followed by AB = 10, then
7. Parametric Failures
the AB = 10 vector is read at the output as a fail state
Parametric failures are the third and most difficult class of
zero (the previous logic state). Stuck-open defects
defects to detect [1]. Parametric failures have been with
occur and are a difficult failure analysis challenge.
us since the beginning of CMOS technology, but their
The main reason is the conflicting information that
significance is now more serious and growing. Parametric
the IC sends due to the memory response of that
failures have unusual properties that form broad
defective node. IDDQ is often elevated due to design
behavioral patterns. Parametric timing failures fall into
contentions caused by the unintended logic state, or
two classes: (1) intrinsic ICs (free of defects), and (2)
the node drifts with a 1-3 s time constant at room
extrinsic ICs (presence of defects). Intrinsic ICs can fail
temperature and can turn on pairs of load transistors
due to an unfortunate distribution of circuit statistics
[8].
and/or environmental conditions. An extrinsic IC may combinations can be very difficult to detect and screen.
have subtle imperfections in vias or contacts that cause its For example, an IC that is normally on the fast edge of
speed characteristics to worsen at lower temperatures. We the distribution could have a delay defect that puts it
will discuss each class with supporting behavioral data, now at the slow, but acceptable range and the part
and then discuss the challenge of detection. passes. Defective parts that pass function are an
7.1 Intrinsic Parametric Failures: increased reliability risk [22]. Test limits can no longer
rely strictly on single limit approaches, but rather
Two factors cause intrinsic parameter variation:
statistical techniques that improve the test signal-to-
environmental and physical. Environmental factors
noise ratio.
include variation of the power supply levels within the
die, on the board, or during switching activity and also Variations in IC Critical Parameters
from temperature variation across the circuit. Physical Statistical variations in primary IC parameters is a
variation comes from the inherent weaknesses in IC concern not only for functionality, but also for setting test
manufacturing control that allows transistor and limits. It is a primary concern in advanced technology
interconnect variations. These deviations from targeted ICs. A bad die can be within the statistical spread of the
values are limitations or imperfections in process and normal population. Figure 17 shows Vt variation from 8%
mask steps. The random and uncontrollable nature of at the 180 nm die to more than 12% for the 130 nm die
parameter variations may cause these failures to be non- [23]. Keshavarzi, et. al., also presented Leff variation data
systematic from die-to-die, wafer-to-wafer, and even and its impact on IDsat which is the transistor speed
transistor-to-transistor property variation within a die parameter [3]. Transistor Leff intrinsic variation is the
(intra-die variation) [15-18]. For example, a drive primary variable that influences Fmax [24].
transistor with a current strength slightly above nominal
may compensate a slightly high interconnect resistance in
12
a signal path. This same high resistance may lead to an
unacceptable signal delay if the transistor has a driving
8
strength below or at the nominal conductance value. This
leads to inaccuracies that impact circuit quality, and can 4

provoke erroneous behaviors that occur at very specific

circuit states or environmental conditions. Recent 0
0.13 0.18 0.23
technologies show die-to-die reordering of critical paths
Technology Genertion (µm)
[16].
These types of failures can be difficult to detect and Fig. 17. Threshold voltage variation within the die [23].

locate. Several failure analysis experiences with

parametric delay defects showed that one to three months Defect-free ICs also show increased random failures due
of effort may be necessary to locate one defect on an IC. to interconnect properties [24]. These properties include
This is intolerable, and research advances with scanning crosstalk, ground bounce, power line IR droop influence
thermal lasers have reduced this fault location times to on timing or even Boolean failure [25]. Crosstalk errors
well under one hour. [19-21]. arise from poor design rule implementation (a difficult
Present design technology is unable to characterize the problem) or statistical fluctuations in metal line spacing
whole complexity of parameter combinations, so (and metal width) [26-27]. These properties are
present strategies often check only the corner aggravated by the present geometric structure of metal
parameters. Therefore, unfortunate parameter cross-sections in which their height to width ratios (aspect
ratio) are now >2. Metal interconnect aspect ratios of 2-3 difference of about 24% with respect to the faster IC.
make the dominant metal capacitance from sidewall to When the power supply was reduced to VDD = 1.2 V (Fig.
sidewall instead of to the power rails as in older 18b), the propagation delays increased almost three times.
technologies. The break in the curve at the 95% cumulative point is
Although crosstalk and switching noise are traditionally more distinct. These inherent statistical deviations can
categorized as design–related problems, technology- lead to timing failures, especially when deviations exist
scaling complexity has diffused the boundaries between within the die. A slow data path signal combined with a
design and functionality. Designers must take statistical fast clock path to a flip-flop can violate setup times and
variation into account in the designs, accepting that some cause functional failure.
circuits from the same fabrication lot fail, while others do
not. An Intel speaker at the 2003 Design Automation and
Test in Europe Conference cited that 67% of FMAX field
returns on a product were due to cross-talk noise and 20%
were due to IR droop on the power lines. These failures
occur in defect-free parts, but they are just a subset of a
broader class of parametric failures.
Another intrinsic concern is the rate of change in power
supply currents that is now on the order of tens of Amps
per ns. Low VDD with higher di/dt increases the statistical
risk of parametric failures due to inductive power rail
bounce and power supply IR drop, combined with lower
signal margin.
Each technology node has a minimum metal width of
about that technology node number. A 100 nm node has a
minimum metal width of about 100 nm [28]. The
minimum dielectric spacing between minimum metal
geometry is also about 100 nm. The vias and contacts may
have diameters on the order of the metal widths, and since
the intermetal dielectric vertical spacing scales more
slowly, the via and contact aspect ratios tend to get larger. Fig. 18. Cumulative distributions for propagation delay from 25
ICs have hundreds of millions and billions of these wafers with data including 910 die per wafer. (a) VDD = 2.5 V,
structures and defect-free vias cannot be guaranteed. Vias (b) VDD = 1.2 V [29].
and contacts are a difficult challenge for fabrication, test
engineering, and failure analysis.
There is a physical difference between parts in the normal
Figure 18 shows the statistical timing variation on a signal
and outlier distributions. The outliers have defects causing
path measured on twenty-five 0.25 µm technology wafers
delay in addition to the part’s otherwise normal variation.
with cumulative propagation delays measured on 910 die
An important point is that real tests that target delay faults
in each wafer [29]. The initial rise in the plots shows a
do not have the capability and resolution to measure to
near straight line relation to the normal distribution. The
this fine degree for each delay path. Each 2-vector timing
difference in propagation delay between fastest and
test pattern does not have an individual test limit, so that
slowest die at VDD = 2.5 V is about 1.7 ns representing a
delay fault testing typically uses the period of the system
clock, and then adds an amount to account for tester noise of IC capability and also a yield loss. Again, these are
and parameter variance. This can lead to test escapes and statistical variations that were not so important in older
reliability returns from the field. Delay fault testing is a technologies, but they are now. An IC apparently failing
gross test for timing errors. A test limit must take into may be due to environmental influences beyond its
account the slowest parameter measurement. Slower control.
outliers from the fastest die overlap normal data in the Temperature also affects the die speed performance. This
slower die. This is part of the challenge in detecting these is especially so for thermal gradients on the die.
statistical variance failures. Simulations and measurements on high performance chips
Figure 19 shows the sensitivity of FMAX to VDD of an Intel show gradients of 130oC to 50oC on the same die.
1 GHz, 6.6 million transistors, router chip built in 150 nm Temperature data taken from a small, 20,000 transistors
technology. The chip has an approximate 1.8 MHz change test circuit showed temperature-FMAX slopes of –
in FMAX per mV of power supply voltage at VDD = 1.3 V. 13.1 kHz / oC and –12.3 kHz / oC for the fast and slow ICs
Figure 19 shows about a 14% increase in FMAX when VDD [15]. The major effect that slows an IC with temperature
increases 10% from VDD = 1.3 V. The sensitivity is higher rise is the decrease in carrier mobility. A compensating
at the low end VDD and saturates above VDD = 1.6 V. speed effect is that the absolute values of the n- and p-
Bernstein, et al., reported a change in FMAX with VDD of channel transistor threshold voltages decrease as
200 kHz/mV for a 180 nm microprocessor, and gave a temperature rises.
performance rule of thumb that chips vary by 7-9% when 7.2 Extrinsic Parametric Failures:
the power supply varies by about 10% [24]. Vangal, et al.,
We will describe four extrinsic IC mechanisms associated
showed FMAX versus VDD plots for a 130 nm dual-Vt
with parametric failures: (1) resistive vias and contacts,
5 GHz technology with a sensitivity of 11.3 MHz/mV at
(2) metal mousebites, (3) metal slivers, and (4) gate oxide
VDD = 1.0 V [30].
shorts in ultrathin technologies. Typically the most
1600
1600 common extrinsic parametric failures in recent
1400
1400 technologies are the metal vias and contacts, and the
1200
1200
F MAX presence of metal slivers aggravated by Chemical
(MHz) 1000
1000
800
800
Mechanical Polishing (CMP). Slivers are a common
600
600 defect in which a metal particle lies between two metal
400
400 conductors and barely contacts the signal lines.
0.8
0.8 1.0
1.0 1.2
1.2 1.4
1.4 1.6
1.6 1.8
1.8
Mousebites occur when sections of metal are missing
VVDD
D D (v (V)
)
from an interconnect line. Gate shorts shows a variety of
Fig. 19. FMAX versus VDD for a 150 nm IC [15]. responses. Some gate shorts show timing and power
supply dependent failures, and the recent ultrathin oxides
have a unique failure mode questioning the implied
Figure 20 emphasizes that mV noise changes in VDD
reliability risk for some gate oxide shorts.
induced on a critical signal node in normal operation can
Resistive Vias
measurably affect IC speed. A related system problem
occurs when board power supplies have a ± 5% accuracy. Modern ICs can have billions of transistors and perhaps
This could move a test verified 1 GHz IC performance in ten times that number of vias. Modern via aspect ratios
Fig. 20 to an operational range from about 883 MHz to are now > 5, so that defective vias with elevated resistance
1.18 GHz on the board. One protection used by are not surprising. Vias and contacts have different sizes
manufacturers is to guardband the shipped product depending upon the metal level. The vias and contacts at
anticipating power supply influences, but this is wasteful the lowest metal level are the smallest usually close to
minimum feature size. Cracks in flat metal lines also
show properties similar to resistive vias, but are a less
common failure mechanism, particularly with the shunting
barrier metals deposited around the Al or Cu metal
interconnect.
Resistive vias have a unique, but expensive signature. A 7

6
speed parameter (FMAX or prop delay) will show
5
degradation as the temperature is reduced. The problem 4
was severe enough even at 0.25 um technologies to 3

require two temperature testing [31]. 2

1
Metal Mousebites 0
0 20 40 60 80 100
Missing regions of interconnect metal are called
Percent Mousebite
mousebites [1]. They can be due to particle defects,
electromigration, or stress voids. Mousebites have a minor Fig. 20. (Top) Control metal line and normal metal line and one
electrical effect, but are a major reliability risk [15]. with mousebite, (bottom) Voided metal resistance (mΩ) versus
Figure 20 (top) sketches a defect-free and a defective percent metal voiding using R = 70 mΩ/ [15].
(mousebite) section of interconnect. If sheet resistance is
R ≈ 70 mΩ / and a 90% bite is taken out of the middle
Metal Slivers
section, then that line resistance changes from 210 mΩ to
840 mΩ. This major defect in the line would not elevate Metal slivers increased their presence with Chemical

resistance sufficiently to be detected by a speed test. Mechanical Polishing (CMP). A small metal sliver lies
between two interconnect lines barely or not even
Figure 20(bottom) plots the increase in resistance of the
touching them. These slivers can be from any of the
stripe versus fraction of mousebite. The resistance
metals used in IC fab, such Al, Cu, W, or stainless steel.
increases dramatically beyond about 95% voiding. This
When temperature rises, metals expand, and the sliver
observation is useful when visually looking at mousebites
now touches the signal lines. Higher voltages at burn-in
and predicting the impact on failure. These small
can promote the rupture of the high resistance oxide
resistance increases due to mousebites have a negligible
surface of the metals, bonding the three metal elements
affect on RC time constant of that line. Mousebites are
[22]. The bridge resistance is now permanent and low
difficult to detect, but pose an electromigration failure risk
enough to reduce noise margins or even cause functional
due to the increased current density in the stripe.
failure.
These conclusions extend to voided vias and contacts that
Metal slivers resistance can appear low but deceiving.
also show this resistance dependency on volume voiding.
Figure 21 sketches two bus lines with a small bridge sliver
The via or contact must be well voided to cause an RC
connecting them. The size and connectivity of the defect
delay failure sensitive to temperature.
will affect the critical resistance.
 with these techniques have been known to take months or
never.

PICA and laser voltage probing (LVP) achieved some

success over the older approaches [34,35]. PICA can
ferret out subtle picosecond timing delays that cause
functional failures while LVP can measure picosecond
waveforms when it knows the particular signal nodes
affecting the failure. Recently PICA sensitivity has
decreased with lower power supply values for
Fig. 21. Resistance of metal sliver.
nanotechnology ICs.

The resistance of the sliver can be estimated. If we Another approach has reported fail site location of

assume an aluminum sliver then the resistivity ρ = 3.0 uΩ parametric failures using scanning thermal and electron-

cm. If the dimensions of the sliver are: W = 0.2 um, L = hole-pair laser beams [19-21]. This technique powers the

0.4 um, and thickness t = 0.4 um, then the resistance is chip, and then drives it with a digital tester that
repetitively cycles a test pattern. The output signal of the
R = ρL = 150 mΩ (11) pin that shows failure is monitored and adjusted to a pass-
W t fail margin by adjusting VDD, clock frequency, or
This is a small value well below all critical resistances. temperature. A laser then scans the die with either an
However, failure analysis shows that these types of 1140 nm or 1064 nm wavelength while the die image is
defects have from tens to hundreds of ohms [22]. Possible put as background on the monitor. When the laser energy
reasons are that the bonding of the sliver to the bus lines strikes the fail site, then the signal output pin will show a
may not be strong or the material may not be Al, but change of logic state from the margin. A latch driven
chrome or other foreign particulate having higher output of the tester pin modulates the e-beam of the
resistivity. Also, all metals form an oxide at their surface monitor indicating precise location of the fail site. This
that drives up the resistance when two metals touch. technique was successfully reported for resistive via
defects [20] and for defect-free timing failures [19,21].
Gate Oxide Breakdown
When the equipment is set up and the part is mounted in
Hard and soft gate oxide breakdown properties were
the fixture, then diagnosis of fail site can be done in
described earlier. Detection of hard breakdowns requires
minutes.
a current-based test, while soft breakdowns are not
Signature Analysis with IDDQ versus VDD
detectable in an IC. The soft breakdowns in the advanced
technology ultrathin oxides may be a lessened reliability CMOS IC designs with their low quiescent currents

risk. present a unique opportunity for failure analysis. Sandia

National Labs has used IDDQ versus VDD signature analysis
How to Detect Parametric Failure
curves since the late 1970’s to perform a rapid assessment
The source of the parametric failure can be an actual
of failure modes. Figure 22 shows the technique for
defect, or it may be due to a particular transistor or
sweeping the power supply pin voltage, VDD, and
interconnect line. The failure is probably sensitive to
monitoring IDDQ. The IC is first put in a logic state that
temperature, VDD, or clock frequency. Traditional
draws abnormal IDDQ. The input pins at logic 0 are tied to
approaches would examine test data and simulation
ground and the logic high pins are tied to VDD. It is
results. This approach is inefficient, and failure analysis
important that input high pins are at the same voltage as
VDD or there is a risk that input protection circuits can be
damaged. The measurement setup is simple and GATE OXIDE SHORT

conducted essentially under DC conditions. IDDQ

Semiconduct. IDDQ
Analyzer

VDD

Hi VDD (V)
CMOS IC
Lo Fig. 24. Signature of n-channel gate oxide short.

Figure 24 shows an n-channel transistor gate oxide short

Fig. 22. Measurement setup for IDDQ versus VDD defect I-V signature [11]. Conduction doesn’t begin until VDD
signatures. exceeds Vt. The signature now includes contributions
from the defect, the defective transistor, and the driving
IDDQ versus VDD signatures can rapidly indicate clues to transistor. Gate to substrate shorts in n-channel transistors
the nature of the defect. The technique doesn’t pinpoint typically show a pronounced parabolic curve [6]. The
defect location, but can often distinguish bridges from gate short forms a parasitic MOSFET transistor whose
opens and power rail shorts from signal node shorts. A gate and drain are connected. This connection places the
bridge defect with at least one end tied to a signal node device in its saturated state whose ID and VGS response is
will not draw current until VDD rises above transistor defined by a square law (Eq. (1)).
threshold, VT. In contrast, rail to rail bridge defects show Several classes of open defects were described, and their
conduction from the initiation of power. Figure 23 and 24 signatures can also take different forms. Often, an open
illustrates these two types of bridging defect signatures defect signature shows a time instability when the
found in a microprocessor [32]. Figure 23 shows a 1.9 defective IC is powered. Figure 25 shows this type of
MΩ rail to rail short whose I-V curve reflects conduction behavior. Capacitive dividers may delay turn-on of the
of the defect without contributions from driving transistor as shown at ≈ 1.5 V. There is need for more
transistors. This defect will also show a line with same research analyzing open defect signatures.
slope if VDD is driven slightly negative.
25 uA

IDDQ
T
IDDQ
OR
SH
AIL
RR
O WE
P
(2.5 uA / Div.)

0 1 3 5
VDD (V)

Fig. 23. A bridge defect between VDD and VSS.

VDD (V)
Fig. 25. An open defect response.
 Acknowledgements:
1. Sandia National Labs is a multiprogram laboratory
Soft breakdown of pn junctions also has a distinct
operated by Sandia Corporation, a Lockheed Martin
signature (Fig. 26). This defect and most gate oxide
Company, for the United States Department of
shorts are strongly photon emitting.
Energy under contract number DE-AC04-
94AL85000.
2. Jaume Segura acknowledges partial support from the
6 uA
Spanish Ministry of Science and Technology and the
IDDQ Regional European Development Funds (FEDER)
3 uA from the European union (CICYT- TIC02-01238).

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