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4-Bit CPU Documentation

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Mengistu Tarko
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22 views5 pages

4-Bit CPU Documentation

Uploaded by

Mengistu Tarko
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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4-Bit CPU Design and Simulation

Using Proteus Professional


Documentation

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4-Bit CPU Design and Simulation Documentation

This project involves the design and simulation of a 4-bit CPU using Proteus Professional software.

The CPU is designed to perform basic operations such as data transfer, arithmetic, and logic

operations, along with program control instructions. The components are wired together to create a

functional computer architecture capable of executing a predefined set of instructions.

Components and Modules

1. Program Counter (PC): Keeps track of the address of the next instruction to be executed.

2. Memory Address Register (MAR): Holds the address of the memory location being accessed.

3. Main ROM and RAM: ROM contains the program, and RAM stores intermediate data during

execution.

4. Instruction Register (IR): Holds the instruction fetched from memory for decoding and execution.

5. Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.

6. Registers:

- Accumulator (A): Primary working register.

- Register B: Secondary register for two-operand operations.

- Temporary Register: Stores intermediate data.

7. Input and Output Registers: Handles input and output operations.

8. Global Clock: Synchronizes all CPU operations.

9. Stack: Supports subroutine calls and returns.

Instruction Set

| Opcode | Instruction | Description |

|--------|--------------------|--------------------------------------------------|

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|1 | MOV A, BYTE | Move a byte of data into the accumulator. |

|2 | IN A | Input a value into the accumulator. |

|3 | ADD A, B | Add the contents of Register B to the accumulator.|

|4 | OUT A | Output the value in the accumulator. |

|5 | SUB A, B | Subtract Register B from the accumulator. |

|6 | XCHG B, A | Exchange Register B and accumulator contents. |

|7 | INC A | Increment the accumulator. |

|8 | MOV A, [ADDRESS] | Move data from a memory address to the accumulator.|

|9 | AND A, [ADDRESS] | Perform logical AND between accumulator and memory.|

|A | JZ ADDRESS | Jump to address if accumulator is zero. |

|B | PUSH B | Push the contents of Register B onto the stack. |

|C | POP B | Pop the top of the stack into Register B. |

|D | CALL ADDRESS | Call a subroutine at the specified address. |

Operation and Workflow

1. The Global Clock drives the fetch-decode-execute cycle.

2. The Program Counter provides the address of the next instruction.

3. The instruction is fetched from ROM, loaded into the Instruction Register, and decoded.

4. The CPU performs the specified operation using the ALU, Registers, and Memory.

5. Input data is received through the Input Register, and results are output through the Output

Register.

Applications

Applications:

- Educational purposes in understanding CPU operations.

- Basic computation tasks.

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- Simulating real-world CPU operations in a controlled environment.

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