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DLD Assignment#2

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157 views2 pages

DLD Assignment#2

Uploaded by

ibrahimahsan485
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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National University of Computer & Emerging Sciences, Lahore

Department of Electrical Engineering (Fall 2024)

EE1005 – Digital Logic Design (BCS-3A)


Assignment#2
[Total Marks: 100]
CLO-04

Question#1: [5 marks]

Design a 4–to–16-line decoder using two 3–to–8-line decoders and 16 2-input AND gates.

Question#2: [10 marks]

A special 4–to–6-line decoder is to be designed. The input codes used are 000 through 101. For a
given code applied, the output Di, with i equal to the decimal equivalent of the code, is 1 and all
other outputs are 0. Design the decoder with a 2–to–4-line decoder, a 1–to–2-line decoder, and
six 2-input AND gates, such that all decoder outputs are used at least once.

Question#3: [20 marks]

An electronic game uses an array of seven LEDs (light-emitting diodes) to display the results of
a random roll of a die. A decoder is to be designed to illuminate the appropriate diodes for the
display of each of the six die values. The desired display patterns are shown in Figure below.

(a) Use a 3–to–8-line decoder and OR gates to map the 3-bit combinations on inputs X2, X1, and
X0 for values 1 through 6 to the outputs a through g. Input combinations 000 and 111 are don’t-
cares.

(b) Note that for the six die sides, only certain combinations of dots occur. For example, dot
pattern A= { d } and dot pattern B= { a, g } can be used for representing input values 1, 2, and 3
as {A}, {B}, and {A, B}. Define four dot patterns A, B, C, and D, sets of which can provide all
six output patterns. Design a minimized custom decoder that has inputs X2, X1, and X0 and
outputs A, B, C, and D.

Question#4: [5 marks]

Draw the detailed logic diagram of a 3–to–8-line decoder using only NOR and NOT gates.
Include an enable input.
National University of Computer & Emerging Sciences, Lahore
Department of Electrical Engineering (Fall 2024)

Question#5: [10 marks]

(a) Design an 8–to–1-line multiplexer using a 3–to–8-line decoder and an 8 * 2 AND-OR.

(b) Repeat part (a), using two 4–to–1-line multiplexers and one 2-to-1-line multiplexer.

Question#6: [20 marks]

Design a logic circuit that performs the following operations on A (3-bit number) and B (3-bit number)
according to the status of selection bits S1 and S0:

𝑺𝟎 𝑺𝟏 𝑺𝟐 Operation F (Output)
000 Increment A+1
001 Add A+B
010 Multiply A*B
011 A Square 𝐴2
100 B Square 𝐵2
101 Triple 3*A

Question#7: [10 marks]

(a) Design a combinational circuit that compares two 4-bit unsigned numbers A and B to see
whether B is greater than A. The circuit has a one 5-bit output X, so that X= A+B if A < B and
X= A-B if A >= B.

Question#8: [10 marks]

(b) Design a 32x1 MUX with active low enable using dual 4x1 MUXs with active low enables
and 2x1 MUX with low enable. Use minimum extra logic to design the required MUX.

Implement following Boolean functions using 16x1 MUX

(i) 𝐹1(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚 (2,3,6,7,12,13,15)

(ii) 𝐹2(𝐴, 𝐵, 𝐶, 𝐷, 𝐸) = ∑ 𝑚 (2,3,4,5,17,20,21,22,23,24,28,30,31)

Question#9: [10 marks]

Design an optimized combinational circuit to perform the arithmetic operation (2 𝒙 + 4y + 11).


Here, 𝒙 (2-bit) and y (3-bit) are two unsigned numbers. Available resources are 4-bit Adders,
Full Adders (FA), NOT gates, 2-input (AND, OR, NAND, NOR) gates. Show complete
working.

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