Lab 2: Simple Programs in Verilog

Sl No Name ID No
1 Diptanshu . Malviya 2024H1400087H

Exercise 1.1:
Create a Vivado Project and write Verilog code for 4-bit Adder (using Data-Flow
modelling).
Write the test bench for your design by giving at least 4 different test patterns.
Simulate the design to check the functionality

Paste the image of the Verilog code used to implement 4-bit adder.

Answer:

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Paste the image of the test bench Verilog code used to test 4-bit adder.

Answer:

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Paste the wave from images showing the simulation for 4-bit adder.

Answer:

Paste the schematic of the elaborated design (RTL Analysis Open Elaborated design).

Answer:

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Exercise 1.2:
Create a Vivado Project and write Verilog code for 2:4 decoder (using behavioral
modelling).
Write the test bench for your design by giving at least 4 different test patterns.
Simulate the design to check the functionality
A Y0
Y0
A __________
2:4 Y1 B
Y1
B Decoder
Y2
Y3 Y2

Y3

Write the truth table for 2:4 decoder.

B A Y0 Y1 Y2 Y3
0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

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Paste the image of the Verilog code used to implement the decoder.

Answer:

Paste the image of the test bench Verilog code used to test 2:4 decoder.

Answer:

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Paste the wave from images showing the simulation for decoder.

Answer:

Paste the schematic of the elaborated design (RTL Analysis Open Elaborated design).

Answer:

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Exercise 1.3:
Create a Vivado Project and write Verilog code D-Latch.
Write the test bench for your designs
Simulate the design to check the functionality

A D-latch circuit with active high enable (i.e. D-latch is positive level sensitive) is shown in the figure
below.
D W1
n2 n4 Q

En

W2 n5 Qbar
n3
n1
Dn

Partial Verilog code D-latch

Testing of D-latch
For testing the latches and flip-flops a particular waveform might have to be generated as inputs. This
section explains about generation of specific waveforms for driving inputs. For the above example of
D-latch let us assume the following waveforms have to be given as inputs D and En.

En

D
t =0 t =7 t =12 t =20 t =30 t =33 t =40

The simplest way to generate two different waveforms in the test bench is to have two separate initial
blocks. In the wave forms above En is 0 for first 5 time units and then is logic 1 for next 10 time units
and so on. The test bench for the D-latch with above input patterns is shown below. Check the output
for the above test pattern.

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Expected Output

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Paste the waveform images showing the simulation for a D latch for given test bench.

Answer: Click here to enter text.

Paste the schematic of the elaborated design (RTL Analysis Open Elaborated design).

Answer:

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 Exercise 1.4:
1. Create a Vivado Project and write Verilog code D-Flip flop using behavioral modelling.
2. Write the test bench for your designs
3. Simulate the design to check the functionality

D Q

Clk
Rst

Verilog code D Flip-flop

Testing of D Flip-flop
D Flip-flops need clock as one of the inputs. This section explains the generation of clock and other input
patterns for D-flip-flop. For the above example of D Flip-flop let us assume the following waveforms have to
be given as inputs D, Clk and Rst.

t
Important: Flip-flop based circuits should be
initially reset. In the above example Rst is made 0 for
3 time units so that the flip-flop initializes to logic ‘0’.
After 3 time units the Rst is given logic 1 to check the
Clk normal operation of D Flip-flop.
t =5 t =10 Here we have to generate three different
waveforms. The simplest way of doing that is to
3 have three different initial blocks in the test
Rst bench. The partial code for test bench is shown
t =0 t =3
10 below.
7 12
5 6
D
t =0 t =7 t =12 t =22 t =28 t =40

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// Generates Rst

// Generates four Clock cycles with time period of 10 units

// generate D and End simulation after 40 time units

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Paste the waveform images showing the simulation for a D flip-flop for given test bench.

Answer:

Paste the schematic of the elaborated design (RTL Analysis Open Elaborated design).

Answer:

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12
Questions Related to Lab1:

What are the basic building blocks of a basic FPGA called?

Answer: The basic building blocks of FPGA are configurable logic blocks,programmable interconnects and
I/O blocks.

How many different functions will you be able to realize using a 3-input LUT?

Answer: 256 functions .

What is the meaning of Bitstream with respect to FPGA?

Answer: a bitstream refers to a file containing the complete internal configuration state of the
FPGA. This configuration includes details about the hardware logic, routing, and initial values for
registers and on-chip memory (such as Look-Up Tables or LUTs). Essentially, the bitstream acts as a
digital blueprint that determines how the FPGA functions. When you program an FPGA, you load this
bitstream to configure the chip according to your desired functionality. It as the set of instructions
that animates the FPGA circuits

Explain briefly the meaning of “FPGA-based Synthesis”?

Answer: During the FPGA synthesis process, a high description design or an HDL design is converted into a gate
level representation or a logic component. A synthesis tool is a computer program that takes in instructions in the
form of hardware description languages as input and generates a synthesized netlist as an output.

In the test bench for D latch and D flip-flop multiple initial blocks are used. Will the multiple
initial blocks execute sequentially or concurrently?

Answer: The multiple initial blocks execute concurrently.

What is the function of keyword „repeat‟ that is used in test bench of D Flip-flop?

Answer: ‘Repeat’ is used in testbench of verilog code to generate the same sequence for the time we require.

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List the concepts you learnt from this lab (Conclusions/Observations)

Answer: The concepts that I learned are: -

1) The working of Hardware Descriptive language, the difference between HDL and High-level
programming language(C,C++,etc).
2) Different types of modelling methods.
3) Giving inputs in the testbench and observing the outputs through the waveform.

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