Main 8
Main 8
~
After a chip has been completely routed, the layout is usually
improved by using via minimization and over-the-cell routing.
Cluster 1
1 Possible via
location
2
3 i
a b
Cluster 2
j f 3
4
k g c d
5
Cluster 4 l h 6
m n o p
7
Cluster 3
7 4 5 6 2 1
Layer 1
Via location
1
2
3
3
4
5
Layer 2 6
7 4 5 6 2 1
1
2
3
3
4
5
6
7 4 5 6 2 1
yt
xt
(a) (b)
Over-the-cell Routing
To optimally utilize metal2 and metal3 layers over active areas.
To reduce delays
To reduce routing footprint
~
Feedthrough
Upper
cell VDD
row GND
Channel
Lower
VDD
cell
row GND
Vacant terminals
Vacant abutment
(a) (b)
2 2 1 1
1
1 1 1
1 1 1 1
Type II
Net Selection
Among all the nets which are suitable for routing over the cells,
~ a maximum weighted subset is selected, which can be routed in
a single layer.
Over-the-Cell Routing
~
The selected nets are assigned exact geometric routes in the
area over the cells.
Channel Routing
~
The segments selected in the previous step are routed in the
channel using a greedy channel router.
Summary
1. There are two approaches CVM and UVM to minimize the number of vias.
2. In CVM, the topology of the routing solution is xed. Vias can be
minimized only by reassigning the net segments to di erent layers.
~ 3. In UVM, the objective is to nd a routing topology with minimum
number of vias.
4. In standard cell design, Over-the-cell routing has been successfully
used to achieve dramatic reductions in the channel heights.