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kamarajme2006
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Via Minimization and Over-the-Cell Routing

Via Minimization and Over-the-Cell Routing

~
After a chip has been completely routed, the layout is usually
improved by using via minimization and over-the-cell routing.

Algorithms for VLSI Physical Design Automation 8.1 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Reasons for Via Minimization


1. In integrated circuit fabrication, the yield is inversely
related to the number of vias. A chip with more vias has
a smaller probability of being fabricated correctly.
~ 2. Every via has an associated resistance which a ects the
circuit performance.
3. Completion rate of routing is also inversely related to
the number of vias.

Algorithms for VLSI Physical Design Automation 8.2 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Constrained Via Minimization Problem

One kind of the via minization problems is to reduce


the number of vias in a completed detailed routing by
~ re-assigning the wire segments to di erent layers.
This kind of via minimization is called
Constrained Via Minimization (CVM).

Algorithms for VLSI Physical Design Automation 8.3 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

A CVM Problem Instance

Cluster 1
1 Possible via
location
2
3 i
a b
Cluster 2
j f 3
4
k g c d
5
Cluster 4 l h 6
m n o p
7
Cluster 3
7 4 5 6 2 1

Algorithms for VLSI Physical Design Automation 8.4 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

A Valid Layer Assignment

Layer 1
Via location
1
2
3

3
4
5
Layer 2 6

7 4 5 6 2 1

Algorithms for VLSI Physical Design Automation 8.5 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

The Solution to The CVM Problem

1
2
3

3
4
5
6

7 4 5 6 2 1

Algorithms for VLSI Physical Design Automation 8.6 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Unconstrained Via Minimization

If the via minimization is considered without the


restriction of completed routing, it is called
Unconstrained Via Minimization (UVM) or
~ Topological Via Minimization (TVM).
In this approach, the actual layout of wires can be
changed and thus o ers more exibility as
compared to the CVM approach.

Algorithms for VLSI Physical Design Automation 8.7 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Algorithm for Crossing-Channel TVM Problem

Given a crossing channel consisting of a set of nets


N =f 1 2
N ; N ; :::; N n g,
the TVM problem can be solved by rst nding a
~ maximum -planar subset of nets. The -planar subset
k k

of nets can be routed in layers without any vias.


k

Then the remaining nets can be routed in any two


adjacent layers using one via per net.

Algorithms for VLSI Physical Design Automation 8.8 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

An Example of Using The Above Algorithm

yt

xt
(a) (b)

Let N  = 1 [ 2 be a maximum 2-planar subset


S S

of nets for the given problem. The part (a) of the


above shows planar routing of two sets 1 and gure S
~

2 on layer 1 and layer 2, respectively. The remaining nets



S

N ; N  are routed using one via for each net


as shown in the part (b) of the gure.

Algorithms for VLSI Physical Design Automation 8.9 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Over-the-cell Routing
To optimally utilize metal2 and metal3 layers over active areas.
 To reduce delays
 To reduce routing footprint
~

Application to standard Cell and Full Custom design styles

Algorithms for VLSI Physical Design Automation 8.10 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Physical Model for Over-the-Cell Routing

Feedthrough

Upper
cell VDD
row GND

Channel

Lower
VDD
cell
row GND

Algorithms for VLSI Physical Design Automation 8.11 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Basic OTC Routing Algorithm

1. Routing over the cells,


~ 2. Choosing net segments in the channel, and
3. Routing in the channel.

Algorithms for VLSI Physical Design Automation 8.12 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Over-the-Cell Routing Using Vacant Terminals


1. Net Classi cation
2. Vacant Terminal and Abutment Assignment
3. Net Selection
~
4. Over-the-Cell Routing
5. Channel Segment Assignment
6. Channel Routing

Algorithms for VLSI Physical Design Automation 8.13 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

E ect of Using Vacant Terminals in Layout

Vacant terminals

Vacant abutment

(a) (b)

Algorithms for VLSI Physical Design Automation 8.14 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Net Classi cation


Each net is classi ed as one of three types which, intuitively,
~
indicates the diculty involved in routing this net over the cells.
1 1 1 1 1 1

2 2 1 1

Type I Type II Type III

Algorithms for VLSI Physical Design Automation 8.15 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Vacant Terminal and Abutment Assignment


Vacant terminals and abutments are assigned to each net depending
~
on its type and weight. The weight of a net intuitively indicates
the improvement in channel congestion possible if this net can
be routed over the cells.
1 1 1

1
1 1 1
1 1 1 1

Type I 1 Type III

Type II

Algorithms for VLSI Physical Design Automation 8.16 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Net Selection

Among all the nets which are suitable for routing over the cells,
~ a maximum weighted subset is selected, which can be routed in
a single layer.

Algorithms for VLSI Physical Design Automation 8.17 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Over-the-Cell Routing

~
The selected nets are assigned exact geometric routes in the
area over the cells.

Algorithms for VLSI Physical Design Automation 8.18 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Channel Segment Assignment

For multi-terminal nets, it is possible that some net segments are


~
not routed over the cells, and therefore, must be routed in the
channel. In this step, `best' segments are selected for routing in
the channel to complete the net connection.

Algorithms for VLSI Physical Design Automation 8.19 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Channel Routing

~
The segments selected in the previous step are routed in the
channel using a greedy channel router.

Algorithms for VLSI Physical Design Automation 8.20 j


c Sherwani 92
Via Minimization and Over-the-Cell Routing

Summary

1. There are two approaches CVM and UVM to minimize the number of vias.
2. In CVM, the topology of the routing solution is xed. Vias can be
minimized only by reassigning the net segments to di erent layers.
~ 3. In UVM, the objective is to nd a routing topology with minimum
number of vias.
4. In standard cell design, Over-the-cell routing has been successfully
used to achieve dramatic reductions in the channel heights.

Algorithms for VLSI Physical Design Automation 8.21 j


c Sherwani 92

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