Today

• Cover and Place

EDA (CS286.5b) – Linear
• GAMA
• Optimal Tree-based
Day 9 – Area and Time
Simultaneous Optimization • covering for
• …and linear placement
(Cover+Place, Area+Delay)
– Two Dimensional
• Lily

Covering Basics
Covering Review Basic Idea:
• Assume have optimal solution to all
• Use dynamic programming to optimally
subproblems smaller than current problem
cover trees
– problem decomposable into subproblems
• try all ways of implementing current root
– each candidate solution is new gate +
– optimal solution to each are part of optimal
previously solve subtrees
– no interaction between subproblems
– pick best (smallest area, least delay, least
– small number of distinct subproblems power)
– single optimal solution to subproblem
• Break DAG into trees then cover optimally

Placement GaMa - Linear Placement

• How do we integrate placement into this • Problem: cover and place datapaths in rows
covering process? of FPGA-like cells to minimize area, delay
• Datapath width extends along one
dimension (rows)
• Composition is 1D along other dimension
(columns)
• Always covering SIMD row at a time

[Callahan/FPGA’98]

1
 Basic Strategy
• Restrict each subtree to a contiguous set of Simultaneous Placement Benefits
rows
• Know real delay (including routing) during
• Build up placement for subtree during cover
covering
• When consider cover, also consider all sets – make sure crtical logic uses fastest inputs
of arrangments of subtrees
– …shortest paths
– effectively expands library set
• Know adjacency
– can use special resources requiring adjacent
blocks

GaMa Delay Example

GaMa Properties
• Operates in time linear in graph size
– O(|rule set|*|graph nodes|)
• Finds area-optimum for restricted problem
– trees with contiguous subtrees
• As is, may not find delay optimum

GaMa Delay Problem GaMa Results

• Area can affect delay • Comparable result quality (area, time) to
• Doesn’t know when to pick worse delay to running through Xilinx tools
reduce area • Placement done in seconds as opposed to
– make non-critical path subtree slower/smaller minutes to hours for Xilinx
– so overall critical path will be close later – simulated anealing, etc.
• Only tracking single objective – not exploiting datapath regularity
• Fixable as next technique demonstrates

2
 Simultaneous Mapping and
Task
Linear Placement of Trees
• Problem: cover and place standard cell row • Minimize:
minimizing area – Area=gate-width * (gate-height+c*wire-pitch)
• Area: cell width and cut width
• Technique: combine DP-covering with DP-
tree layout

[Lou+Salek+Pedram/ICCAD’97]

Composition Challenge Minimize Area

• Minimum area solution to subproblems • Two components of area:
does not necessarily lead to minimum area – gate-area
solution: – cut-width
• Unclear during mapping when need
– a smaller gate-area
– vs. a smaller cut-width
• at the expense of (local) cell area
– (same problem as area vs. delay in GaMa)

Strategy Dominating/Inferior Solutions

• Recognize that these are incomparable • A solution is dominated if there is another
objectives solution strictly superior in all objectives
– neither is strictly superior to other – A=3, T=2 A=2, T=3
– keep all solutions • neither dominates
– discard only inferior (dominated) solutions – A=3, T=3 A=3, T=2 A=2, T=3
• A=3, T=3 is inferior, being dominated by either of
the other two solutions

3
 Non-Inferior Curve
• Set of dominators defines a curve Strategy
• Keep curve of non-inferior area-cut points
• During DP
– build a new curve for each subtree
– by looking at solution set insersections
• cross product set of solutions from each subtrees
feeding into this subtree

This is a recurring theme -- will often prune work

using dominator curve

Consequences Algorithm: Tree Cover+Place

• More work per graph point • For each tree node from leafs
– keeping and intersecting many points – For each gate cover
• Theory: points(fanin) * gates • For each non-inferior point in fanin-subtrees
– compute optimal tree layout
• Points <= range of solutions in smallest – keep non-inferior points (cutwidth, gate-area)
dimension
• e.g. points <= number of different cut- • Optimal Tree Layout
widths – Yannakakis/JACM v32n4p950, Oct. 1985

Time Notes
Empirical Results
• Computing Optimal Tree layout:
O(Nlog(N)) • Claim: 20% area improvement
• Total: O(cutwidth(fanin) * N*log(N))
• Loose bound
– possible to tighten?
– less points and smaller “N” in tree for earlier
subproblems
– higher fanin -> less depth -> more use of small
“N” for linear layout problems

4
 Strategy
Covering for Area and Delay
• Use same technique as just detailed for
• Previously saw was hard to do DP to – gate-area + cutwidth
– simultaneously optimize for area and delay • I.e. -- at each tree cover
– properly generate area-time tradeoffs – keep all non-inferior points
• Problem: • (effectively the full area-time curve)

– whether or not needed a fast path – as cover, intersect area-time curves to generate
new area-time curve
– not clear until saw speed of siblings
• When get to a node
– can pick smallest implementation for a child
[Chaudhary+Pedram/DAC’92] node that does not increase critical path

Points to Keep
GaMa -- Optimal Delay
• Usually small variance in times
– if use discrete model like LUT delays, only a • Use this technique in GaMa
small number of different times – solve delay problem
– if use continuous model, can get close to
– get good area-delay tradeoffs
optimum by discretizing and keeping a fixed set
– GARP has a discrete timing model
• Similarly, small total variance in area • so already have small spread
– e.g. factor of 2-3 – for conventional FPGA
– discretizing, gets close w/out giving up much • will have to discretize
• Discretized: run in time linear in N
– assuming bounded fanin gates

Covering and Linear Placement

Strategy
for Area and Delay
• Have both • Repeat trick:
– cut-width + gate-area affects – keep non-inferior points in three-space
– delay tradeoff • <cut-width,gate-area,delay>

• Result – Intersect spaces to compute new cover spaces

– have three objectives to minimize – May really need to discretize points to limit
• cut-width
work
• gate-area
• gate-delay

[Lou+Salek+Pedram/ICCAD’97]

5
 Note Empirical Results
• Delay calculation: • Mapping for delay:
– assumes delay in gates and fanout – 20% delay improvement
– fanout effect makes heuristic – achieving effectively same area
• maybe iterate/relax? • (of alternative, not of self targeting area)
– ignores distance
• “Optimal” tree layout algorithm being used
– is optimal with respect to cut-width
– not optimal with respect to critical path wire
length

Two Dimensions? 2D Cover and Place

• Both so far, one-dimensional • Problem: cover and place in 2D to
• One-dimensional minimize area (delay)
– nice layout restrictions • Area: gate area + “wirelength” area
– simple metric for delay • Delay: gate delay + estimated wire delay
– simple metric for area
• How extend to two dimensions?

[Pedram+Bhat/DAC’91]

Strategy
Example • Relax placement during covering
• Initially place unmapped using constructive
• Covering wrt placement matters
placement (like last time)
• Cover via dynamic programming
nand2
• When cover a node,
– fanins already visited
– calculate new placement
nor2
• Periodically re-calculate placement
nand2 • Use estimated/refined placements to get
area, delay

6
 Incremental Placement
Empirical Results
• Place newly covered nodes so as to
• In 1µm
minimize wire lengths (critical path delay?)
– 5% area reduction
– 8% delay reduction
• Not that inspiring
– …but this was in the micron era
– probably have a bigger effect today

Summary Today’s Big Ideas:

• Can consider placement effects while
covering • Simultaneous optimization
• Many problems can’t find optimum by • Multi-dimensional objectives
minimizing single objective – dominating points (inferior points)
– delay (area effects) – use with dynamic programming
– area (cutwidth effects) • Exploit stylized problems can solve
• Can adapt DP to solve optimally
– keep all non-inferior points • Phase Ordering: estimate/iterate
– can keep polynomial time
• if very careful, primarily increase constants